1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4 * Author: Andy Yan <andy.yan@rock-chips.com>
5 */
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/swab.h>
21
22 #include <drm/drm.h>
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_uapi.h>
25 #include <drm/drm_blend.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_debugfs.h>
28 #include <drm/drm_flip_work.h>
29 #include <drm/drm_framebuffer.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_vblank.h>
32
33 #include <uapi/linux/videodev2.h>
34 #include <dt-bindings/soc/rockchip,vop2.h>
35
36 #include "rockchip_drm_drv.h"
37 #include "rockchip_drm_gem.h"
38 #include "rockchip_drm_fb.h"
39 #include "rockchip_drm_vop2.h"
40 #include "rockchip_rgb.h"
41
42 /*
43 * VOP2 architecture
44 *
45 +----------+ +-------------+ +-----------+
46 | Cluster | | Sel 1 from 6| | 1 from 3 |
47 | window0 | | Layer0 | | RGB |
48 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
49 +----------+ +-------------+ |N from 6 layers| | |
50 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
51 | window1 | | Layer1 | | | | | | 1 from 3 |
52 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
53 +----------+ +-------------+ +-----------+
54 | Esmart | | Sel 1 from 6|
55 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+
56 +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 |
57 +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI |
58 | Esmart | | Sel 1 from 6| --------> | | | | +-----------+
59 | Window1 | | Layer3 | +---------------+ +-------------+
60 +----------+ +-------------+ +-----------+
61 +----------+ +-------------+ | 1 from 3 |
62 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI |
63 | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+
64 +----------+ +-------------+ | Overlay2 +--->| Video Port2 |
65 +----------+ +-------------+ | | | | +-----------+
66 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 |
67 | Window1 | | Layer5 | | eDP |
68 +----------+ +-------------+ +-----------+
69 *
70 */
71
72 enum vop2_data_format {
73 VOP2_FMT_ARGB8888 = 0,
74 VOP2_FMT_RGB888,
75 VOP2_FMT_RGB565,
76 VOP2_FMT_XRGB101010,
77 VOP2_FMT_YUV420SP,
78 VOP2_FMT_YUV422SP,
79 VOP2_FMT_YUV444SP,
80 VOP2_FMT_YUYV422 = 8,
81 VOP2_FMT_YUYV420,
82 VOP2_FMT_VYUY422,
83 VOP2_FMT_VYUY420,
84 VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
85 VOP2_FMT_YUV420SP_TILE_16x2,
86 VOP2_FMT_YUV422SP_TILE_8x4,
87 VOP2_FMT_YUV422SP_TILE_16x2,
88 VOP2_FMT_YUV420SP_10,
89 VOP2_FMT_YUV422SP_10,
90 VOP2_FMT_YUV444SP_10,
91 };
92
93 enum vop2_afbc_format {
94 VOP2_AFBC_FMT_RGB565,
95 VOP2_AFBC_FMT_ARGB2101010 = 2,
96 VOP2_AFBC_FMT_YUV420_10BIT,
97 VOP2_AFBC_FMT_RGB888,
98 VOP2_AFBC_FMT_ARGB8888,
99 VOP2_AFBC_FMT_YUV420 = 9,
100 VOP2_AFBC_FMT_YUV422 = 0xb,
101 VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
102 VOP2_AFBC_FMT_INVALID = -1,
103 };
104
105 union vop2_alpha_ctrl {
106 u32 val;
107 struct {
108 /* [0:1] */
109 u32 color_mode:1;
110 u32 alpha_mode:1;
111 /* [2:3] */
112 u32 blend_mode:2;
113 u32 alpha_cal_mode:1;
114 /* [5:7] */
115 u32 factor_mode:3;
116 /* [8:9] */
117 u32 alpha_en:1;
118 u32 src_dst_swap:1;
119 u32 reserved:6;
120 /* [16:23] */
121 u32 glb_alpha:8;
122 } bits;
123 };
124
125 struct vop2_alpha {
126 union vop2_alpha_ctrl src_color_ctrl;
127 union vop2_alpha_ctrl dst_color_ctrl;
128 union vop2_alpha_ctrl src_alpha_ctrl;
129 union vop2_alpha_ctrl dst_alpha_ctrl;
130 };
131
132 struct vop2_alpha_config {
133 bool src_premulti_en;
134 bool dst_premulti_en;
135 bool src_pixel_alpha_en;
136 bool dst_pixel_alpha_en;
137 u16 src_glb_alpha_value;
138 u16 dst_glb_alpha_value;
139 };
140
141 struct vop2_win {
142 struct vop2 *vop2;
143 struct drm_plane base;
144 const struct vop2_win_data *data;
145 struct regmap_field *reg[VOP2_WIN_MAX_REG];
146
147 /**
148 * @win_id: graphic window id, a cluster may be split into two
149 * graphics windows.
150 */
151 u8 win_id;
152 u8 delay;
153 u32 offset;
154
155 enum drm_plane_type type;
156 };
157
158 struct vop2_video_port {
159 struct drm_crtc crtc;
160 struct vop2 *vop2;
161 struct clk *dclk;
162 unsigned int id;
163 const struct vop2_video_port_regs *regs;
164 const struct vop2_video_port_data *data;
165
166 struct completion dsp_hold_completion;
167
168 /**
169 * @win_mask: Bitmask of windows attached to the video port;
170 */
171 u32 win_mask;
172
173 struct vop2_win *primary_plane;
174 struct drm_pending_vblank_event *event;
175
176 unsigned int nlayers;
177 };
178
179 struct vop2 {
180 struct device *dev;
181 struct drm_device *drm;
182 struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
183
184 const struct vop2_data *data;
185 /*
186 * Number of windows that are registered as plane, may be less than the
187 * total number of hardware windows.
188 */
189 u32 registered_num_wins;
190
191 void __iomem *regs;
192 struct regmap *map;
193
194 struct regmap *grf;
195
196 /* physical map length of vop2 register */
197 u32 len;
198
199 void __iomem *lut_regs;
200
201 /* protects crtc enable/disable */
202 struct mutex vop2_lock;
203
204 int irq;
205
206 /*
207 * Some global resources are shared between all video ports(crtcs), so
208 * we need a ref counter here.
209 */
210 unsigned int enable_count;
211 struct clk *hclk;
212 struct clk *aclk;
213
214 /* optional internal rgb encoder */
215 struct rockchip_rgb *rgb;
216
217 /* must be put at the end of the struct */
218 struct vop2_win win[];
219 };
220
to_vop2_video_port(struct drm_crtc * crtc)221 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
222 {
223 return container_of(crtc, struct vop2_video_port, crtc);
224 }
225
to_vop2_win(struct drm_plane * p)226 static struct vop2_win *to_vop2_win(struct drm_plane *p)
227 {
228 return container_of(p, struct vop2_win, base);
229 }
230
vop2_lock(struct vop2 * vop2)231 static void vop2_lock(struct vop2 *vop2)
232 {
233 mutex_lock(&vop2->vop2_lock);
234 }
235
vop2_unlock(struct vop2 * vop2)236 static void vop2_unlock(struct vop2 *vop2)
237 {
238 mutex_unlock(&vop2->vop2_lock);
239 }
240
vop2_writel(struct vop2 * vop2,u32 offset,u32 v)241 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
242 {
243 regmap_write(vop2->map, offset, v);
244 }
245
vop2_vp_write(struct vop2_video_port * vp,u32 offset,u32 v)246 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
247 {
248 regmap_write(vp->vop2->map, vp->data->offset + offset, v);
249 }
250
vop2_readl(struct vop2 * vop2,u32 offset)251 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
252 {
253 u32 val;
254
255 regmap_read(vop2->map, offset, &val);
256
257 return val;
258 }
259
vop2_win_write(const struct vop2_win * win,unsigned int reg,u32 v)260 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
261 {
262 regmap_field_write(win->reg[reg], v);
263 }
264
vop2_cluster_window(const struct vop2_win * win)265 static bool vop2_cluster_window(const struct vop2_win *win)
266 {
267 return win->data->feature & WIN_FEATURE_CLUSTER;
268 }
269
vop2_cfg_done(struct vop2_video_port * vp)270 static void vop2_cfg_done(struct vop2_video_port *vp)
271 {
272 struct vop2 *vop2 = vp->vop2;
273
274 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE,
275 BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
276 }
277
vop2_win_disable(struct vop2_win * win)278 static void vop2_win_disable(struct vop2_win *win)
279 {
280 vop2_win_write(win, VOP2_WIN_ENABLE, 0);
281
282 if (vop2_cluster_window(win))
283 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
284 }
285
vop2_convert_format(u32 format)286 static enum vop2_data_format vop2_convert_format(u32 format)
287 {
288 switch (format) {
289 case DRM_FORMAT_XRGB8888:
290 case DRM_FORMAT_ARGB8888:
291 case DRM_FORMAT_XBGR8888:
292 case DRM_FORMAT_ABGR8888:
293 return VOP2_FMT_ARGB8888;
294 case DRM_FORMAT_RGB888:
295 case DRM_FORMAT_BGR888:
296 return VOP2_FMT_RGB888;
297 case DRM_FORMAT_RGB565:
298 case DRM_FORMAT_BGR565:
299 return VOP2_FMT_RGB565;
300 case DRM_FORMAT_NV12:
301 return VOP2_FMT_YUV420SP;
302 case DRM_FORMAT_NV16:
303 return VOP2_FMT_YUV422SP;
304 case DRM_FORMAT_NV24:
305 return VOP2_FMT_YUV444SP;
306 case DRM_FORMAT_YUYV:
307 case DRM_FORMAT_YVYU:
308 return VOP2_FMT_VYUY422;
309 case DRM_FORMAT_VYUY:
310 case DRM_FORMAT_UYVY:
311 return VOP2_FMT_YUYV422;
312 default:
313 DRM_ERROR("unsupported format[%08x]\n", format);
314 return -EINVAL;
315 }
316 }
317
vop2_convert_afbc_format(u32 format)318 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format)
319 {
320 switch (format) {
321 case DRM_FORMAT_XRGB8888:
322 case DRM_FORMAT_ARGB8888:
323 case DRM_FORMAT_XBGR8888:
324 case DRM_FORMAT_ABGR8888:
325 return VOP2_AFBC_FMT_ARGB8888;
326 case DRM_FORMAT_RGB888:
327 case DRM_FORMAT_BGR888:
328 return VOP2_AFBC_FMT_RGB888;
329 case DRM_FORMAT_RGB565:
330 case DRM_FORMAT_BGR565:
331 return VOP2_AFBC_FMT_RGB565;
332 case DRM_FORMAT_NV12:
333 return VOP2_AFBC_FMT_YUV420;
334 case DRM_FORMAT_NV16:
335 return VOP2_AFBC_FMT_YUV422;
336 default:
337 return VOP2_AFBC_FMT_INVALID;
338 }
339
340 return VOP2_AFBC_FMT_INVALID;
341 }
342
vop2_win_rb_swap(u32 format)343 static bool vop2_win_rb_swap(u32 format)
344 {
345 switch (format) {
346 case DRM_FORMAT_XBGR8888:
347 case DRM_FORMAT_ABGR8888:
348 case DRM_FORMAT_BGR888:
349 case DRM_FORMAT_BGR565:
350 return true;
351 default:
352 return false;
353 }
354 }
355
vop2_afbc_rb_swap(u32 format)356 static bool vop2_afbc_rb_swap(u32 format)
357 {
358 switch (format) {
359 case DRM_FORMAT_NV24:
360 return true;
361 default:
362 return false;
363 }
364 }
365
vop2_afbc_uv_swap(u32 format)366 static bool vop2_afbc_uv_swap(u32 format)
367 {
368 switch (format) {
369 case DRM_FORMAT_NV12:
370 case DRM_FORMAT_NV16:
371 return true;
372 default:
373 return false;
374 }
375 }
376
vop2_win_uv_swap(u32 format)377 static bool vop2_win_uv_swap(u32 format)
378 {
379 switch (format) {
380 case DRM_FORMAT_NV12:
381 case DRM_FORMAT_NV16:
382 case DRM_FORMAT_NV24:
383 return true;
384 default:
385 return false;
386 }
387 }
388
vop2_win_dither_up(u32 format)389 static bool vop2_win_dither_up(u32 format)
390 {
391 switch (format) {
392 case DRM_FORMAT_BGR565:
393 case DRM_FORMAT_RGB565:
394 return true;
395 default:
396 return false;
397 }
398 }
399
vop2_output_uv_swap(u32 bus_format,u32 output_mode)400 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode)
401 {
402 /*
403 * FIXME:
404 *
405 * There is no media type for YUV444 output,
406 * so when out_mode is AAAA or P888, assume output is YUV444 on
407 * yuv format.
408 *
409 * From H/W testing, YUV444 mode need a rb swap.
410 */
411 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
412 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
413 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
414 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
415 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
416 bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
417 (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
418 output_mode == ROCKCHIP_OUT_MODE_P888)))
419 return true;
420 else
421 return false;
422 }
423
is_yuv_output(u32 bus_format)424 static bool is_yuv_output(u32 bus_format)
425 {
426 switch (bus_format) {
427 case MEDIA_BUS_FMT_YUV8_1X24:
428 case MEDIA_BUS_FMT_YUV10_1X30:
429 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
430 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
431 case MEDIA_BUS_FMT_YUYV8_2X8:
432 case MEDIA_BUS_FMT_YVYU8_2X8:
433 case MEDIA_BUS_FMT_UYVY8_2X8:
434 case MEDIA_BUS_FMT_VYUY8_2X8:
435 case MEDIA_BUS_FMT_YUYV8_1X16:
436 case MEDIA_BUS_FMT_YVYU8_1X16:
437 case MEDIA_BUS_FMT_UYVY8_1X16:
438 case MEDIA_BUS_FMT_VYUY8_1X16:
439 return true;
440 default:
441 return false;
442 }
443 }
444
rockchip_afbc(struct drm_plane * plane,u64 modifier)445 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
446 {
447 int i;
448
449 if (modifier == DRM_FORMAT_MOD_LINEAR)
450 return false;
451
452 for (i = 0 ; i < plane->modifier_count; i++)
453 if (plane->modifiers[i] == modifier)
454 return true;
455
456 return false;
457 }
458
rockchip_vop2_mod_supported(struct drm_plane * plane,u32 format,u64 modifier)459 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
460 u64 modifier)
461 {
462 struct vop2_win *win = to_vop2_win(plane);
463 struct vop2 *vop2 = win->vop2;
464
465 if (modifier == DRM_FORMAT_MOD_INVALID)
466 return false;
467
468 if (modifier == DRM_FORMAT_MOD_LINEAR)
469 return true;
470
471 if (!rockchip_afbc(plane, modifier)) {
472 drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n",
473 modifier);
474
475 return false;
476 }
477
478 return vop2_convert_afbc_format(format) >= 0;
479 }
480
vop2_afbc_transform_offset(struct drm_plane_state * pstate,bool afbc_half_block_en)481 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate,
482 bool afbc_half_block_en)
483 {
484 struct drm_rect *src = &pstate->src;
485 struct drm_framebuffer *fb = pstate->fb;
486 u32 bpp = fb->format->cpp[0] * 8;
487 u32 vir_width = (fb->pitches[0] << 3) / bpp;
488 u32 width = drm_rect_width(src) >> 16;
489 u32 height = drm_rect_height(src) >> 16;
490 u32 act_xoffset = src->x1 >> 16;
491 u32 act_yoffset = src->y1 >> 16;
492 u32 align16_crop = 0;
493 u32 align64_crop = 0;
494 u32 height_tmp;
495 u8 tx, ty;
496 u8 bottom_crop_line_num = 0;
497
498 /* 16 pixel align */
499 if (height & 0xf)
500 align16_crop = 16 - (height & 0xf);
501
502 height_tmp = height + align16_crop;
503
504 /* 64 pixel align */
505 if (height_tmp & 0x3f)
506 align64_crop = 64 - (height_tmp & 0x3f);
507
508 bottom_crop_line_num = align16_crop + align64_crop;
509
510 switch (pstate->rotation &
511 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y |
512 DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) {
513 case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
514 tx = 16 - ((act_xoffset + width) & 0xf);
515 ty = bottom_crop_line_num - act_yoffset;
516 break;
517 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
518 tx = bottom_crop_line_num - act_yoffset;
519 ty = vir_width - width - act_xoffset;
520 break;
521 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
522 tx = act_yoffset;
523 ty = act_xoffset;
524 break;
525 case DRM_MODE_REFLECT_X:
526 tx = 16 - ((act_xoffset + width) & 0xf);
527 ty = act_yoffset;
528 break;
529 case DRM_MODE_REFLECT_Y:
530 tx = act_xoffset;
531 ty = bottom_crop_line_num - act_yoffset;
532 break;
533 case DRM_MODE_ROTATE_90:
534 tx = bottom_crop_line_num - act_yoffset;
535 ty = act_xoffset;
536 break;
537 case DRM_MODE_ROTATE_270:
538 tx = act_yoffset;
539 ty = vir_width - width - act_xoffset;
540 break;
541 case 0:
542 tx = act_xoffset;
543 ty = act_yoffset;
544 break;
545 }
546
547 if (afbc_half_block_en)
548 ty &= 0x7f;
549
550 #define TRANSFORM_XOFFSET GENMASK(7, 0)
551 #define TRANSFORM_YOFFSET GENMASK(23, 16)
552 return FIELD_PREP(TRANSFORM_XOFFSET, tx) |
553 FIELD_PREP(TRANSFORM_YOFFSET, ty);
554 }
555
556 /*
557 * A Cluster window has 2048 x 16 line buffer, which can
558 * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
559 * for Cluster_lb_mode register:
560 * 0: half mode, for plane input width range 2048 ~ 4096
561 * 1: half mode, for cluster work at 2 * 2048 plane mode
562 * 2: half mode, for rotate_90/270 mode
563 *
564 */
vop2_get_cluster_lb_mode(struct vop2_win * win,struct drm_plane_state * pstate)565 static int vop2_get_cluster_lb_mode(struct vop2_win *win,
566 struct drm_plane_state *pstate)
567 {
568 if ((pstate->rotation & DRM_MODE_ROTATE_270) ||
569 (pstate->rotation & DRM_MODE_ROTATE_90))
570 return 2;
571 else
572 return 0;
573 }
574
vop2_scale_factor(u32 src,u32 dst)575 static u16 vop2_scale_factor(u32 src, u32 dst)
576 {
577 u32 fac;
578 int shift;
579
580 if (src == dst)
581 return 0;
582
583 if (dst < 2)
584 return U16_MAX;
585
586 if (src < 2)
587 return 0;
588
589 if (src > dst)
590 shift = 12;
591 else
592 shift = 16;
593
594 src--;
595 dst--;
596
597 fac = DIV_ROUND_UP(src << shift, dst) - 1;
598
599 if (fac > U16_MAX)
600 return U16_MAX;
601
602 return fac;
603 }
604
vop2_setup_scale(struct vop2 * vop2,const struct vop2_win * win,u32 src_w,u32 src_h,u32 dst_w,u32 dst_h,u32 pixel_format)605 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
606 u32 src_w, u32 src_h, u32 dst_w,
607 u32 dst_h, u32 pixel_format)
608 {
609 const struct drm_format_info *info;
610 u16 hor_scl_mode, ver_scl_mode;
611 u16 hscl_filter_mode, vscl_filter_mode;
612 uint16_t cbcr_src_w = src_w;
613 uint16_t cbcr_src_h = src_h;
614 u8 gt2 = 0;
615 u8 gt4 = 0;
616 u32 val;
617
618 info = drm_format_info(pixel_format);
619
620 if (src_h >= (4 * dst_h)) {
621 gt4 = 1;
622 src_h >>= 2;
623 } else if (src_h >= (2 * dst_h)) {
624 gt2 = 1;
625 src_h >>= 1;
626 }
627
628 hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
629 ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
630
631 if (hor_scl_mode == SCALE_UP)
632 hscl_filter_mode = VOP2_SCALE_UP_BIC;
633 else
634 hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
635
636 if (ver_scl_mode == SCALE_UP)
637 vscl_filter_mode = VOP2_SCALE_UP_BIL;
638 else
639 vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
640
641 /*
642 * RK3568 VOP Esmart/Smart dsp_w should be even pixel
643 * at scale down mode
644 */
645 if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
646 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
647 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
648 win->data->name, dst_w);
649 dst_w++;
650 }
651 }
652
653 val = vop2_scale_factor(src_w, dst_w);
654 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
655 val = vop2_scale_factor(src_h, dst_h);
656 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
657
658 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
659 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
660
661 vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode);
662 vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode);
663
664 if (vop2_cluster_window(win))
665 return;
666
667 vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
668 vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
669
670 if (info->is_yuv) {
671 cbcr_src_w /= info->hsub;
672 cbcr_src_h /= info->vsub;
673
674 gt4 = 0;
675 gt2 = 0;
676
677 if (cbcr_src_h >= (4 * dst_h)) {
678 gt4 = 1;
679 cbcr_src_h >>= 2;
680 } else if (cbcr_src_h >= (2 * dst_h)) {
681 gt2 = 1;
682 cbcr_src_h >>= 1;
683 }
684
685 hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
686 ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
687
688 val = vop2_scale_factor(cbcr_src_w, dst_w);
689 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
690
691 val = vop2_scale_factor(cbcr_src_h, dst_h);
692 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
693
694 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
695 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
696 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode);
697 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode);
698 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
699 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
700 }
701 }
702
vop2_convert_csc_mode(int csc_mode)703 static int vop2_convert_csc_mode(int csc_mode)
704 {
705 switch (csc_mode) {
706 case V4L2_COLORSPACE_SMPTE170M:
707 case V4L2_COLORSPACE_470_SYSTEM_M:
708 case V4L2_COLORSPACE_470_SYSTEM_BG:
709 return CSC_BT601L;
710 case V4L2_COLORSPACE_REC709:
711 case V4L2_COLORSPACE_SMPTE240M:
712 case V4L2_COLORSPACE_DEFAULT:
713 return CSC_BT709L;
714 case V4L2_COLORSPACE_JPEG:
715 return CSC_BT601F;
716 case V4L2_COLORSPACE_BT2020:
717 return CSC_BT2020;
718 default:
719 return CSC_BT709L;
720 }
721 }
722
723 /*
724 * colorspace path:
725 * Input Win csc Output
726 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
727 * RGB --> R2Y __/
728 *
729 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
730 * RGB --> 709To2020->R2Y __/
731 *
732 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
733 * RGB --> R2Y __/
734 *
735 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
736 * RGB --> 709To2020->R2Y __/
737 *
738 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
739 * RGB --> R2Y __/
740 *
741 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
742 * RGB --> R2Y(601) __/
743 *
744 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
745 * RGB --> bypass __/
746 *
747 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
748 *
749 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
750 *
751 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
752 *
753 * 11. RGB --> bypass --> RGB_OUTPUT(709)
754 */
755
vop2_setup_csc_mode(struct vop2_video_port * vp,struct vop2_win * win,struct drm_plane_state * pstate)756 static void vop2_setup_csc_mode(struct vop2_video_port *vp,
757 struct vop2_win *win,
758 struct drm_plane_state *pstate)
759 {
760 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
761 int is_input_yuv = pstate->fb->format->is_yuv;
762 int is_output_yuv = is_yuv_output(vcstate->bus_format);
763 int input_csc = V4L2_COLORSPACE_DEFAULT;
764 int output_csc = vcstate->color_space;
765 bool r2y_en, y2r_en;
766 int csc_mode;
767
768 if (is_input_yuv && !is_output_yuv) {
769 y2r_en = true;
770 r2y_en = false;
771 csc_mode = vop2_convert_csc_mode(input_csc);
772 } else if (!is_input_yuv && is_output_yuv) {
773 y2r_en = false;
774 r2y_en = true;
775 csc_mode = vop2_convert_csc_mode(output_csc);
776 } else {
777 y2r_en = false;
778 r2y_en = false;
779 csc_mode = false;
780 }
781
782 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
783 vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
784 vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
785 }
786
vop2_crtc_enable_irq(struct vop2_video_port * vp,u32 irq)787 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq)
788 {
789 struct vop2 *vop2 = vp->vop2;
790
791 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
792 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
793 }
794
vop2_crtc_disable_irq(struct vop2_video_port * vp,u32 irq)795 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq)
796 {
797 struct vop2 *vop2 = vp->vop2;
798
799 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
800 }
801
vop2_core_clks_prepare_enable(struct vop2 * vop2)802 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
803 {
804 int ret;
805
806 ret = clk_prepare_enable(vop2->hclk);
807 if (ret < 0) {
808 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
809 return ret;
810 }
811
812 ret = clk_prepare_enable(vop2->aclk);
813 if (ret < 0) {
814 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
815 goto err;
816 }
817
818 return 0;
819 err:
820 clk_disable_unprepare(vop2->hclk);
821
822 return ret;
823 }
824
vop2_enable(struct vop2 * vop2)825 static void vop2_enable(struct vop2 *vop2)
826 {
827 int ret;
828
829 ret = pm_runtime_resume_and_get(vop2->dev);
830 if (ret < 0) {
831 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
832 return;
833 }
834
835 ret = vop2_core_clks_prepare_enable(vop2);
836 if (ret) {
837 pm_runtime_put_sync(vop2->dev);
838 return;
839 }
840
841 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
842 if (ret) {
843 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
844 return;
845 }
846
847 regcache_sync(vop2->map);
848
849 if (vop2->data->soc_id == 3566)
850 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
851
852 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
853
854 /*
855 * Disable auto gating, this is a workaround to
856 * avoid display image shift when a window enabled.
857 */
858 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
859 RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN);
860
861 vop2_writel(vop2, RK3568_SYS0_INT_CLR,
862 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
863 vop2_writel(vop2, RK3568_SYS0_INT_EN,
864 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
865 vop2_writel(vop2, RK3568_SYS1_INT_CLR,
866 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
867 vop2_writel(vop2, RK3568_SYS1_INT_EN,
868 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
869 }
870
vop2_disable(struct vop2 * vop2)871 static void vop2_disable(struct vop2 *vop2)
872 {
873 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
874
875 pm_runtime_put_sync(vop2->dev);
876
877 regcache_mark_dirty(vop2->map);
878
879 clk_disable_unprepare(vop2->aclk);
880 clk_disable_unprepare(vop2->hclk);
881 }
882
vop2_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)883 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
884 struct drm_atomic_state *state)
885 {
886 struct vop2_video_port *vp = to_vop2_video_port(crtc);
887 struct vop2 *vop2 = vp->vop2;
888 struct drm_crtc_state *old_crtc_state;
889 int ret;
890
891 vop2_lock(vop2);
892
893 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
894 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
895
896 drm_crtc_vblank_off(crtc);
897
898 /*
899 * Vop standby will take effect at end of current frame,
900 * if dsp hold valid irq happen, it means standby complete.
901 *
902 * we must wait standby complete when we want to disable aclk,
903 * if not, memory bus maybe dead.
904 */
905 reinit_completion(&vp->dsp_hold_completion);
906
907 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID);
908
909 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
910
911 ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
912 msecs_to_jiffies(50));
913 if (!ret)
914 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
915
916 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
917
918 clk_disable_unprepare(vp->dclk);
919
920 vop2->enable_count--;
921
922 if (!vop2->enable_count)
923 vop2_disable(vop2);
924
925 vop2_unlock(vop2);
926
927 if (crtc->state->event && !crtc->state->active) {
928 spin_lock_irq(&crtc->dev->event_lock);
929 drm_crtc_send_vblank_event(crtc, crtc->state->event);
930 spin_unlock_irq(&crtc->dev->event_lock);
931
932 crtc->state->event = NULL;
933 }
934 }
935
vop2_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * astate)936 static int vop2_plane_atomic_check(struct drm_plane *plane,
937 struct drm_atomic_state *astate)
938 {
939 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane);
940 struct drm_framebuffer *fb = pstate->fb;
941 struct drm_crtc *crtc = pstate->crtc;
942 struct drm_crtc_state *cstate;
943 struct vop2_video_port *vp;
944 struct vop2 *vop2;
945 const struct vop2_data *vop2_data;
946 struct drm_rect *dest = &pstate->dst;
947 struct drm_rect *src = &pstate->src;
948 int min_scale = FRAC_16_16(1, 8);
949 int max_scale = FRAC_16_16(8, 1);
950 int format;
951 int ret;
952
953 if (!crtc)
954 return 0;
955
956 vp = to_vop2_video_port(crtc);
957 vop2 = vp->vop2;
958 vop2_data = vop2->data;
959
960 cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
961 if (WARN_ON(!cstate))
962 return -EINVAL;
963
964 ret = drm_atomic_helper_check_plane_state(pstate, cstate,
965 min_scale, max_scale,
966 true, true);
967 if (ret)
968 return ret;
969
970 if (!pstate->visible)
971 return 0;
972
973 format = vop2_convert_format(fb->format->format);
974 if (format < 0)
975 return format;
976
977 if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 ||
978 drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) {
979 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
980 drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
981 drm_rect_width(dest), drm_rect_height(dest));
982 pstate->visible = false;
983 return 0;
984 }
985
986 if (drm_rect_width(src) >> 16 > vop2_data->max_input.width ||
987 drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
988 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
989 drm_rect_width(src) >> 16,
990 drm_rect_height(src) >> 16,
991 vop2_data->max_input.width,
992 vop2_data->max_input.height);
993 return -EINVAL;
994 }
995
996 /*
997 * Src.x1 can be odd when do clip, but yuv plane start point
998 * need align with 2 pixel.
999 */
1000 if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) {
1001 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
1002 return -EINVAL;
1003 }
1004
1005 return 0;
1006 }
1007
vop2_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)1008 static void vop2_plane_atomic_disable(struct drm_plane *plane,
1009 struct drm_atomic_state *state)
1010 {
1011 struct drm_plane_state *old_pstate = NULL;
1012 struct vop2_win *win = to_vop2_win(plane);
1013 struct vop2 *vop2 = win->vop2;
1014
1015 drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1016
1017 if (state)
1018 old_pstate = drm_atomic_get_old_plane_state(state, plane);
1019 if (old_pstate && !old_pstate->crtc)
1020 return;
1021
1022 vop2_win_disable(win);
1023 vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0);
1024 }
1025
1026 /*
1027 * The color key is 10 bit, so all format should
1028 * convert to 10 bit here.
1029 */
vop2_plane_setup_color_key(struct drm_plane * plane,u32 color_key)1030 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key)
1031 {
1032 struct drm_plane_state *pstate = plane->state;
1033 struct drm_framebuffer *fb = pstate->fb;
1034 struct vop2_win *win = to_vop2_win(plane);
1035 u32 color_key_en = 0;
1036 u32 r = 0;
1037 u32 g = 0;
1038 u32 b = 0;
1039
1040 if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) {
1041 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0);
1042 return;
1043 }
1044
1045 switch (fb->format->format) {
1046 case DRM_FORMAT_RGB565:
1047 case DRM_FORMAT_BGR565:
1048 r = (color_key & 0xf800) >> 11;
1049 g = (color_key & 0x7e0) >> 5;
1050 b = (color_key & 0x1f);
1051 r <<= 5;
1052 g <<= 4;
1053 b <<= 5;
1054 color_key_en = 1;
1055 break;
1056 case DRM_FORMAT_XRGB8888:
1057 case DRM_FORMAT_ARGB8888:
1058 case DRM_FORMAT_XBGR8888:
1059 case DRM_FORMAT_ABGR8888:
1060 case DRM_FORMAT_RGB888:
1061 case DRM_FORMAT_BGR888:
1062 r = (color_key & 0xff0000) >> 16;
1063 g = (color_key & 0xff00) >> 8;
1064 b = (color_key & 0xff);
1065 r <<= 2;
1066 g <<= 2;
1067 b <<= 2;
1068 color_key_en = 1;
1069 break;
1070 }
1071
1072 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en);
1073 vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b);
1074 }
1075
vop2_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)1076 static void vop2_plane_atomic_update(struct drm_plane *plane,
1077 struct drm_atomic_state *state)
1078 {
1079 struct drm_plane_state *pstate = plane->state;
1080 struct drm_crtc *crtc = pstate->crtc;
1081 struct vop2_win *win = to_vop2_win(plane);
1082 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1083 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1084 struct vop2 *vop2 = win->vop2;
1085 struct drm_framebuffer *fb = pstate->fb;
1086 u32 bpp = fb->format->cpp[0] * 8;
1087 u32 actual_w, actual_h, dsp_w, dsp_h;
1088 u32 act_info, dsp_info;
1089 u32 format;
1090 u32 afbc_format;
1091 u32 rb_swap;
1092 u32 uv_swap;
1093 struct drm_rect *src = &pstate->src;
1094 struct drm_rect *dest = &pstate->dst;
1095 u32 afbc_tile_num;
1096 u32 transform_offset;
1097 bool dither_up;
1098 bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false;
1099 bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false;
1100 bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270;
1101 bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90;
1102 struct rockchip_gem_object *rk_obj;
1103 unsigned long offset;
1104 bool afbc_en;
1105 dma_addr_t yrgb_mst;
1106 dma_addr_t uv_mst;
1107
1108 /*
1109 * can't update plane when vop2 is disabled.
1110 */
1111 if (WARN_ON(!crtc))
1112 return;
1113
1114 if (!pstate->visible) {
1115 vop2_plane_atomic_disable(plane, state);
1116 return;
1117 }
1118
1119 afbc_en = rockchip_afbc(plane, fb->modifier);
1120
1121 offset = (src->x1 >> 16) * fb->format->cpp[0];
1122
1123 /*
1124 * AFBC HDR_PTR must set to the zero offset of the framebuffer.
1125 */
1126 if (afbc_en)
1127 offset = 0;
1128 else if (pstate->rotation & DRM_MODE_REFLECT_Y)
1129 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1130 else
1131 offset += (src->y1 >> 16) * fb->pitches[0];
1132
1133 rk_obj = to_rockchip_obj(fb->obj[0]);
1134
1135 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
1136 if (fb->format->is_yuv) {
1137 int hsub = fb->format->hsub;
1138 int vsub = fb->format->vsub;
1139
1140 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub;
1141 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1142
1143 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en)
1144 offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub;
1145
1146 rk_obj = to_rockchip_obj(fb->obj[0]);
1147 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1];
1148 }
1149
1150 actual_w = drm_rect_width(src) >> 16;
1151 actual_h = drm_rect_height(src) >> 16;
1152 dsp_w = drm_rect_width(dest);
1153
1154 if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
1155 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1156 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
1157 dsp_w = adjusted_mode->hdisplay - dest->x1;
1158 if (dsp_w < 4)
1159 dsp_w = 4;
1160 actual_w = dsp_w * actual_w / drm_rect_width(dest);
1161 }
1162
1163 dsp_h = drm_rect_height(dest);
1164
1165 if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
1166 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1167 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
1168 dsp_h = adjusted_mode->vdisplay - dest->y1;
1169 if (dsp_h < 4)
1170 dsp_h = 4;
1171 actual_h = dsp_h * actual_h / drm_rect_height(dest);
1172 }
1173
1174 /*
1175 * This is workaround solution for IC design:
1176 * esmart can't support scale down when actual_w % 16 == 1.
1177 */
1178 if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
1179 if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
1180 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1181 vp->id, win->data->name, actual_w);
1182 actual_w -= 1;
1183 }
1184 }
1185
1186 if (afbc_en && actual_w % 4) {
1187 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1188 vp->id, win->data->name, actual_w);
1189 actual_w = ALIGN_DOWN(actual_w, 4);
1190 }
1191
1192 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1193 dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff);
1194
1195 format = vop2_convert_format(fb->format->format);
1196
1197 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1198 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h,
1199 dest->x1, dest->y1,
1200 &fb->format->format,
1201 afbc_en ? "AFBC" : "", &yrgb_mst);
1202
1203 if (afbc_en) {
1204 u32 stride;
1205
1206 /* the afbc superblock is 16 x 16 */
1207 afbc_format = vop2_convert_afbc_format(fb->format->format);
1208
1209 /* Enable color transform for YTR */
1210 if (fb->modifier & AFBC_FORMAT_MOD_YTR)
1211 afbc_format |= (1 << 4);
1212
1213 afbc_tile_num = ALIGN(actual_w, 16) >> 4;
1214
1215 /*
1216 * AFBC pic_vir_width is count by pixel, this is different
1217 * with WIN_VIR_STRIDE.
1218 */
1219 stride = (fb->pitches[0] << 3) / bpp;
1220 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270))
1221 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1222 vp->id, win->data->name, stride);
1223
1224 rb_swap = vop2_afbc_rb_swap(fb->format->format);
1225 uv_swap = vop2_afbc_uv_swap(fb->format->format);
1226 /*
1227 * This is a workaround for crazy IC design, Cluster
1228 * and Esmart/Smart use different format configuration map:
1229 * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
1230 *
1231 * This is one thing we can make the convert simple:
1232 * AFBCD decode all the YUV data to YUV444. So we just
1233 * set all the yuv 10 bit to YUV444_10.
1234 */
1235 if (fb->format->is_yuv && bpp == 10)
1236 format = VOP2_CLUSTER_YUV444_10;
1237
1238 if (vop2_cluster_window(win))
1239 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1);
1240 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format);
1241 vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap);
1242 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap);
1243 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0);
1244 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0);
1245 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) {
1246 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0);
1247 transform_offset = vop2_afbc_transform_offset(pstate, false);
1248 } else {
1249 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1);
1250 transform_offset = vop2_afbc_transform_offset(pstate, true);
1251 }
1252 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
1253 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
1254 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset);
1255 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1));
1256 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16)));
1257 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
1258 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num);
1259 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror);
1260 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270);
1261 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90);
1262 } else {
1263 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4));
1264 }
1265
1266 vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror);
1267
1268 if (rotate_90 || rotate_270) {
1269 act_info = swahw32(act_info);
1270 actual_w = drm_rect_height(src) >> 16;
1271 actual_h = drm_rect_width(src) >> 16;
1272 }
1273
1274 vop2_win_write(win, VOP2_WIN_FORMAT, format);
1275 vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst);
1276
1277 rb_swap = vop2_win_rb_swap(fb->format->format);
1278 vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap);
1279 if (!vop2_cluster_window(win)) {
1280 uv_swap = vop2_win_uv_swap(fb->format->format);
1281 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap);
1282 }
1283
1284 if (fb->format->is_yuv) {
1285 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4));
1286 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst);
1287 }
1288
1289 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1290 if (!vop2_cluster_window(win))
1291 vop2_plane_setup_color_key(plane, 0);
1292 vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info);
1293 vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info);
1294 vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff));
1295
1296 vop2_setup_csc_mode(vp, win, pstate);
1297
1298 dither_up = vop2_win_dither_up(fb->format->format);
1299 vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up);
1300
1301 vop2_win_write(win, VOP2_WIN_ENABLE, 1);
1302
1303 if (vop2_cluster_window(win)) {
1304 int lb_mode = vop2_get_cluster_lb_mode(win, pstate);
1305
1306 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode);
1307 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1);
1308 }
1309 }
1310
1311 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = {
1312 .atomic_check = vop2_plane_atomic_check,
1313 .atomic_update = vop2_plane_atomic_update,
1314 .atomic_disable = vop2_plane_atomic_disable,
1315 };
1316
1317 static const struct drm_plane_funcs vop2_plane_funcs = {
1318 .update_plane = drm_atomic_helper_update_plane,
1319 .disable_plane = drm_atomic_helper_disable_plane,
1320 .destroy = drm_plane_cleanup,
1321 .reset = drm_atomic_helper_plane_reset,
1322 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1323 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1324 .format_mod_supported = rockchip_vop2_mod_supported,
1325 };
1326
vop2_crtc_enable_vblank(struct drm_crtc * crtc)1327 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc)
1328 {
1329 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1330
1331 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD);
1332
1333 return 0;
1334 }
1335
vop2_crtc_disable_vblank(struct drm_crtc * crtc)1336 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc)
1337 {
1338 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1339
1340 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD);
1341 }
1342
vop2_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adj_mode)1343 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
1344 const struct drm_display_mode *mode,
1345 struct drm_display_mode *adj_mode)
1346 {
1347 drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
1348 CRTC_STEREO_DOUBLE);
1349
1350 return true;
1351 }
1352
vop2_dither_setup(struct drm_crtc * crtc,u32 * dsp_ctrl)1353 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl)
1354 {
1355 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1356
1357 switch (vcstate->bus_format) {
1358 case MEDIA_BUS_FMT_RGB565_1X16:
1359 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1360 break;
1361 case MEDIA_BUS_FMT_RGB666_1X18:
1362 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1363 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
1364 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1365 *dsp_ctrl |= RGB888_TO_RGB666;
1366 break;
1367 case MEDIA_BUS_FMT_YUV8_1X24:
1368 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1369 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1370 break;
1371 default:
1372 break;
1373 }
1374
1375 if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA)
1376 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1377
1378 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL,
1379 DITHER_DOWN_ALLEGRO);
1380 }
1381
vop2_post_config(struct drm_crtc * crtc)1382 static void vop2_post_config(struct drm_crtc *crtc)
1383 {
1384 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1385 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1386 u16 vtotal = mode->crtc_vtotal;
1387 u16 hdisplay = mode->crtc_hdisplay;
1388 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1389 u16 vdisplay = mode->crtc_vdisplay;
1390 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1391 u32 left_margin = 100, right_margin = 100;
1392 u32 top_margin = 100, bottom_margin = 100;
1393 u16 hsize = hdisplay * (left_margin + right_margin) / 200;
1394 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
1395 u16 hact_end, vact_end;
1396 u32 val;
1397
1398 vsize = rounddown(vsize, 2);
1399 hsize = rounddown(hsize, 2);
1400 hact_st += hdisplay * (100 - left_margin) / 200;
1401 hact_end = hact_st + hsize;
1402 val = hact_st << 16;
1403 val |= hact_end;
1404 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val);
1405 vact_st += vdisplay * (100 - top_margin) / 200;
1406 vact_end = vact_st + vsize;
1407 val = vact_st << 16;
1408 val |= vact_end;
1409 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val);
1410 val = scl_cal_scale2(vdisplay, vsize) << 16;
1411 val |= scl_cal_scale2(hdisplay, hsize);
1412 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val);
1413
1414 val = 0;
1415 if (hdisplay != hsize)
1416 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN;
1417 if (vdisplay != vsize)
1418 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN;
1419 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val);
1420
1421 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1422 u16 vact_st_f1 = vtotal + vact_st + 1;
1423 u16 vact_end_f1 = vact_st_f1 + vsize;
1424
1425 val = vact_st_f1 << 16 | vact_end_f1;
1426 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
1427 }
1428
1429 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
1430 }
1431
rk3568_set_intf_mux(struct vop2_video_port * vp,int id,u32 polflags)1432 static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id,
1433 u32 polflags)
1434 {
1435 struct vop2 *vop2 = vp->vop2;
1436 u32 die, dip;
1437
1438 die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1439 dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1440
1441 switch (id) {
1442 case ROCKCHIP_VOP2_EP_RGB0:
1443 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX;
1444 die |= RK3568_SYS_DSP_INFACE_EN_RGB |
1445 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id);
1446 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1447 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1448 if (polflags & POLFLAG_DCLK_INV)
1449 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1450 else
1451 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1452 break;
1453 case ROCKCHIP_VOP2_EP_HDMI0:
1454 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
1455 die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
1456 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
1457 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
1458 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
1459 break;
1460 case ROCKCHIP_VOP2_EP_EDP0:
1461 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
1462 die |= RK3568_SYS_DSP_INFACE_EN_EDP |
1463 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
1464 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
1465 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
1466 break;
1467 case ROCKCHIP_VOP2_EP_MIPI0:
1468 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
1469 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 |
1470 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id);
1471 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1472 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1473 break;
1474 case ROCKCHIP_VOP2_EP_MIPI1:
1475 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX;
1476 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 |
1477 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1478 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1479 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1480 break;
1481 case ROCKCHIP_VOP2_EP_LVDS0:
1482 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX;
1483 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 |
1484 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id);
1485 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1486 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1487 break;
1488 case ROCKCHIP_VOP2_EP_LVDS1:
1489 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX;
1490 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 |
1491 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id);
1492 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1493 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1494 break;
1495 default:
1496 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1497 return;
1498 }
1499
1500 dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
1501
1502 vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1503 vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1504 }
1505
us_to_vertical_line(struct drm_display_mode * mode,int us)1506 static int us_to_vertical_line(struct drm_display_mode *mode, int us)
1507 {
1508 return us * mode->clock / mode->htotal / 1000;
1509 }
1510
vop2_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1511 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
1512 struct drm_atomic_state *state)
1513 {
1514 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1515 struct vop2 *vop2 = vp->vop2;
1516 const struct vop2_data *vop2_data = vop2->data;
1517 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
1518 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1519 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1520 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1521 unsigned long clock = mode->crtc_clock * 1000;
1522 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1523 u16 hdisplay = mode->crtc_hdisplay;
1524 u16 htotal = mode->crtc_htotal;
1525 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1526 u16 hact_end = hact_st + hdisplay;
1527 u16 vdisplay = mode->crtc_vdisplay;
1528 u16 vtotal = mode->crtc_vtotal;
1529 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
1530 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1531 u16 vact_end = vact_st + vdisplay;
1532 u8 out_mode;
1533 u32 dsp_ctrl = 0;
1534 int act_end;
1535 u32 val, polflags;
1536 int ret;
1537 struct drm_encoder *encoder;
1538
1539 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
1540 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
1541 drm_mode_vrefresh(mode), vcstate->output_type, vp->id);
1542
1543 vop2_lock(vop2);
1544
1545 ret = clk_prepare_enable(vp->dclk);
1546 if (ret < 0) {
1547 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
1548 vp->id, ret);
1549 vop2_unlock(vop2);
1550 return;
1551 }
1552
1553 if (!vop2->enable_count)
1554 vop2_enable(vop2);
1555
1556 vop2->enable_count++;
1557
1558 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
1559
1560 polflags = 0;
1561 if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
1562 polflags |= POLFLAG_DCLK_INV;
1563 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1564 polflags |= BIT(HSYNC_POSITIVE);
1565 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1566 polflags |= BIT(VSYNC_POSITIVE);
1567
1568 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
1569 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
1570
1571 rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags);
1572 }
1573
1574 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1575 !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1576 out_mode = ROCKCHIP_OUT_MODE_P888;
1577 else
1578 out_mode = vcstate->output_mode;
1579
1580 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode);
1581
1582 if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
1583 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
1584
1585 if (is_yuv_output(vcstate->bus_format))
1586 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
1587
1588 vop2_dither_setup(crtc, &dsp_ctrl);
1589
1590 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
1591 val = hact_st << 16;
1592 val |= hact_end;
1593 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
1594
1595 val = vact_st << 16;
1596 val |= vact_end;
1597 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
1598
1599 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1600 u16 vact_st_f1 = vtotal + vact_st + 1;
1601 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1602
1603 val = vact_st_f1 << 16 | vact_end_f1;
1604 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
1605
1606 val = vtotal << 16 | (vtotal + vsync_len);
1607 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
1608 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE;
1609 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL;
1610 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN;
1611 vtotal += vtotal + 1;
1612 act_end = vact_end_f1;
1613 } else {
1614 act_end = vact_end;
1615 }
1616
1617 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
1618 (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end);
1619
1620 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
1621
1622 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1623 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
1624 clock *= 2;
1625 }
1626
1627 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
1628
1629 clk_set_rate(vp->dclk, clock);
1630
1631 vop2_post_config(crtc);
1632
1633 vop2_cfg_done(vp);
1634
1635 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1636
1637 drm_crtc_vblank_on(crtc);
1638
1639 vop2_unlock(vop2);
1640 }
1641
vop2_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1642 static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
1643 struct drm_atomic_state *state)
1644 {
1645 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1646 struct drm_plane *plane;
1647 int nplanes = 0;
1648 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1649
1650 drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
1651 nplanes++;
1652
1653 if (nplanes > vp->nlayers)
1654 return -EINVAL;
1655
1656 return 0;
1657 }
1658
is_opaque(u16 alpha)1659 static bool is_opaque(u16 alpha)
1660 {
1661 return (alpha >> 8) == 0xff;
1662 }
1663
vop2_parse_alpha(struct vop2_alpha_config * alpha_config,struct vop2_alpha * alpha)1664 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config,
1665 struct vop2_alpha *alpha)
1666 {
1667 int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1;
1668 int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1;
1669 int src_color_mode = alpha_config->src_premulti_en ?
1670 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1671 int dst_color_mode = alpha_config->dst_premulti_en ?
1672 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1673
1674 alpha->src_color_ctrl.val = 0;
1675 alpha->dst_color_ctrl.val = 0;
1676 alpha->src_alpha_ctrl.val = 0;
1677 alpha->dst_alpha_ctrl.val = 0;
1678
1679 if (!alpha_config->src_pixel_alpha_en)
1680 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1681 else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en)
1682 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1683 else
1684 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1685
1686 alpha->src_color_ctrl.bits.alpha_en = 1;
1687
1688 if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) {
1689 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1690 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1691 } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) {
1692 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1693 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE;
1694 } else {
1695 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL;
1696 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1697 }
1698 alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8;
1699 alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1700 alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1701
1702 alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1703 alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1704 alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1705 alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8;
1706 alpha->dst_color_ctrl.bits.color_mode = dst_color_mode;
1707 alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1708
1709 alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1710 alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode;
1711 alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1712 alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
1713
1714 alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1715 if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
1716 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1717 else
1718 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1719 alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
1720 alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1721 }
1722
vop2_find_start_mixer_id_for_vp(struct vop2 * vop2,u8 port_id)1723 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
1724 {
1725 struct vop2_video_port *vp;
1726 int used_layer = 0;
1727 int i;
1728
1729 for (i = 0; i < port_id; i++) {
1730 vp = &vop2->vps[i];
1731 used_layer += hweight32(vp->win_mask);
1732 }
1733
1734 return used_layer;
1735 }
1736
vop2_setup_cluster_alpha(struct vop2 * vop2,struct vop2_win * main_win)1737 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
1738 {
1739 u32 offset = (main_win->data->phys_id * 0x10);
1740 struct vop2_alpha_config alpha_config;
1741 struct vop2_alpha alpha;
1742 struct drm_plane_state *bottom_win_pstate;
1743 bool src_pixel_alpha_en = false;
1744 u16 src_glb_alpha_val, dst_glb_alpha_val;
1745 bool premulti_en = false;
1746 bool swap = false;
1747
1748 /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
1749 bottom_win_pstate = main_win->base.state;
1750 src_glb_alpha_val = 0;
1751 dst_glb_alpha_val = main_win->base.state->alpha;
1752
1753 if (!bottom_win_pstate->fb)
1754 return;
1755
1756 alpha_config.src_premulti_en = premulti_en;
1757 alpha_config.dst_premulti_en = false;
1758 alpha_config.src_pixel_alpha_en = src_pixel_alpha_en;
1759 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1760 alpha_config.src_glb_alpha_value = src_glb_alpha_val;
1761 alpha_config.dst_glb_alpha_value = dst_glb_alpha_val;
1762 vop2_parse_alpha(&alpha_config, &alpha);
1763
1764 alpha.src_color_ctrl.bits.src_dst_swap = swap;
1765 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
1766 alpha.src_color_ctrl.val);
1767 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
1768 alpha.dst_color_ctrl.val);
1769 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
1770 alpha.src_alpha_ctrl.val);
1771 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
1772 alpha.dst_alpha_ctrl.val);
1773 }
1774
vop2_setup_alpha(struct vop2_video_port * vp)1775 static void vop2_setup_alpha(struct vop2_video_port *vp)
1776 {
1777 struct vop2 *vop2 = vp->vop2;
1778 struct drm_framebuffer *fb;
1779 struct vop2_alpha_config alpha_config;
1780 struct vop2_alpha alpha;
1781 struct drm_plane *plane;
1782 int pixel_alpha_en;
1783 int premulti_en, gpremulti_en = 0;
1784 int mixer_id;
1785 u32 offset;
1786 bool bottom_layer_alpha_en = false;
1787 u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE;
1788
1789 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
1790 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1791
1792 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1793 struct vop2_win *win = to_vop2_win(plane);
1794
1795 if (plane->state->normalized_zpos == 0 &&
1796 !is_opaque(plane->state->alpha) &&
1797 !vop2_cluster_window(win)) {
1798 /*
1799 * If bottom layer have global alpha effect [except cluster layer,
1800 * because cluster have deal with bottom layer global alpha value
1801 * at cluster mix], bottom layer mix need deal with global alpha.
1802 */
1803 bottom_layer_alpha_en = true;
1804 dst_global_alpha = plane->state->alpha;
1805 }
1806 }
1807
1808 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1809 struct vop2_win *win = to_vop2_win(plane);
1810 int zpos = plane->state->normalized_zpos;
1811
1812 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
1813 premulti_en = 1;
1814 else
1815 premulti_en = 0;
1816
1817 plane = &win->base;
1818 fb = plane->state->fb;
1819
1820 pixel_alpha_en = fb->format->has_alpha;
1821
1822 alpha_config.src_premulti_en = premulti_en;
1823
1824 if (bottom_layer_alpha_en && zpos == 1) {
1825 gpremulti_en = premulti_en;
1826 /* Cd = Cs + (1 - As) * Cd * Agd */
1827 alpha_config.dst_premulti_en = false;
1828 alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1829 alpha_config.src_glb_alpha_value = plane->state->alpha;
1830 alpha_config.dst_glb_alpha_value = dst_global_alpha;
1831 } else if (vop2_cluster_window(win)) {
1832 /* Mix output data only have pixel alpha */
1833 alpha_config.dst_premulti_en = true;
1834 alpha_config.src_pixel_alpha_en = true;
1835 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1836 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1837 } else {
1838 /* Cd = Cs + (1 - As) * Cd */
1839 alpha_config.dst_premulti_en = true;
1840 alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1841 alpha_config.src_glb_alpha_value = plane->state->alpha;
1842 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1843 }
1844
1845 vop2_parse_alpha(&alpha_config, &alpha);
1846
1847 offset = (mixer_id + zpos - 1) * 0x10;
1848 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
1849 alpha.src_color_ctrl.val);
1850 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
1851 alpha.dst_color_ctrl.val);
1852 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
1853 alpha.src_alpha_ctrl.val);
1854 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
1855 alpha.dst_alpha_ctrl.val);
1856 }
1857
1858 if (vp->id == 0) {
1859 if (bottom_layer_alpha_en) {
1860 /* Transfer pixel alpha to hdr mix */
1861 alpha_config.src_premulti_en = gpremulti_en;
1862 alpha_config.dst_premulti_en = true;
1863 alpha_config.src_pixel_alpha_en = true;
1864 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1865 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1866 vop2_parse_alpha(&alpha_config, &alpha);
1867
1868 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
1869 alpha.src_color_ctrl.val);
1870 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
1871 alpha.dst_color_ctrl.val);
1872 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
1873 alpha.src_alpha_ctrl.val);
1874 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
1875 alpha.dst_alpha_ctrl.val);
1876 } else {
1877 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
1878 }
1879 }
1880 }
1881
vop2_setup_layer_mixer(struct vop2_video_port * vp)1882 static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
1883 {
1884 struct vop2 *vop2 = vp->vop2;
1885 struct drm_plane *plane;
1886 u32 layer_sel = 0;
1887 u32 port_sel;
1888 unsigned int nlayer, ofs;
1889 struct drm_display_mode *adjusted_mode;
1890 u16 hsync_len;
1891 u16 hdisplay;
1892 u32 bg_dly;
1893 u32 pre_scan_dly;
1894 int i;
1895 struct vop2_video_port *vp0 = &vop2->vps[0];
1896 struct vop2_video_port *vp1 = &vop2->vps[1];
1897 struct vop2_video_port *vp2 = &vop2->vps[2];
1898
1899 adjusted_mode = &vp->crtc.state->adjusted_mode;
1900 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1901 hdisplay = adjusted_mode->crtc_hdisplay;
1902
1903 bg_dly = vp->data->pre_scan_max_dly[3];
1904 vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1905 FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
1906
1907 pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
1908 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
1909
1910 vop2_writel(vop2, RK3568_OVL_CTRL, 0);
1911 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
1912 port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
1913
1914 if (vp0->nlayers)
1915 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX,
1916 vp0->nlayers - 1);
1917 else
1918 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8);
1919
1920 if (vp1->nlayers)
1921 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX,
1922 (vp0->nlayers + vp1->nlayers - 1));
1923 else
1924 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
1925
1926 if (vp2->nlayers)
1927 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX,
1928 (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
1929 else
1930 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
1931
1932 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
1933
1934 ofs = 0;
1935 for (i = 0; i < vp->id; i++)
1936 ofs += vop2->vps[i].nlayers;
1937
1938 nlayer = 0;
1939 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1940 struct vop2_win *win = to_vop2_win(plane);
1941
1942 switch (win->data->phys_id) {
1943 case ROCKCHIP_VOP2_CLUSTER0:
1944 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0;
1945 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id);
1946 break;
1947 case ROCKCHIP_VOP2_CLUSTER1:
1948 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1;
1949 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id);
1950 break;
1951 case ROCKCHIP_VOP2_ESMART0:
1952 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0;
1953 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id);
1954 break;
1955 case ROCKCHIP_VOP2_ESMART1:
1956 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1;
1957 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id);
1958 break;
1959 case ROCKCHIP_VOP2_SMART0:
1960 port_sel &= ~RK3568_OVL_PORT_SEL__SMART0;
1961 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id);
1962 break;
1963 case ROCKCHIP_VOP2_SMART1:
1964 port_sel &= ~RK3568_OVL_PORT_SEL__SMART1;
1965 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id);
1966 break;
1967 }
1968
1969 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
1970 0x7);
1971 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
1972 win->data->layer_sel_id);
1973 nlayer++;
1974 }
1975
1976 /* configure unused layers to 0x5 (reserved) */
1977 for (; nlayer < vp->nlayers; nlayer++) {
1978 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7);
1979 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5);
1980 }
1981
1982 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
1983 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
1984 vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD);
1985 }
1986
vop2_setup_dly_for_windows(struct vop2 * vop2)1987 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
1988 {
1989 struct vop2_win *win;
1990 int i = 0;
1991 u32 cdly = 0, sdly = 0;
1992
1993 for (i = 0; i < vop2->data->win_size; i++) {
1994 u32 dly;
1995
1996 win = &vop2->win[i];
1997 dly = win->delay;
1998
1999 switch (win->data->phys_id) {
2000 case ROCKCHIP_VOP2_CLUSTER0:
2001 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly);
2002 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly);
2003 break;
2004 case ROCKCHIP_VOP2_CLUSTER1:
2005 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly);
2006 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly);
2007 break;
2008 case ROCKCHIP_VOP2_ESMART0:
2009 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly);
2010 break;
2011 case ROCKCHIP_VOP2_ESMART1:
2012 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly);
2013 break;
2014 case ROCKCHIP_VOP2_SMART0:
2015 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly);
2016 break;
2017 case ROCKCHIP_VOP2_SMART1:
2018 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly);
2019 break;
2020 }
2021 }
2022
2023 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2024 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2025 }
2026
vop2_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)2027 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc,
2028 struct drm_atomic_state *state)
2029 {
2030 struct vop2_video_port *vp = to_vop2_video_port(crtc);
2031 struct vop2 *vop2 = vp->vop2;
2032 struct drm_plane *plane;
2033
2034 vp->win_mask = 0;
2035
2036 drm_atomic_crtc_for_each_plane(plane, crtc) {
2037 struct vop2_win *win = to_vop2_win(plane);
2038
2039 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2040
2041 vp->win_mask |= BIT(win->data->phys_id);
2042
2043 if (vop2_cluster_window(win))
2044 vop2_setup_cluster_alpha(vop2, win);
2045 }
2046
2047 if (!vp->win_mask)
2048 return;
2049
2050 vop2_setup_layer_mixer(vp);
2051 vop2_setup_alpha(vp);
2052 vop2_setup_dly_for_windows(vop2);
2053 }
2054
vop2_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)2055 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
2056 struct drm_atomic_state *state)
2057 {
2058 struct vop2_video_port *vp = to_vop2_video_port(crtc);
2059
2060 vop2_post_config(crtc);
2061
2062 vop2_cfg_done(vp);
2063
2064 spin_lock_irq(&crtc->dev->event_lock);
2065
2066 if (crtc->state->event) {
2067 WARN_ON(drm_crtc_vblank_get(crtc));
2068 vp->event = crtc->state->event;
2069 crtc->state->event = NULL;
2070 }
2071
2072 spin_unlock_irq(&crtc->dev->event_lock);
2073 }
2074
2075 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
2076 .mode_fixup = vop2_crtc_mode_fixup,
2077 .atomic_check = vop2_crtc_atomic_check,
2078 .atomic_begin = vop2_crtc_atomic_begin,
2079 .atomic_flush = vop2_crtc_atomic_flush,
2080 .atomic_enable = vop2_crtc_atomic_enable,
2081 .atomic_disable = vop2_crtc_atomic_disable,
2082 };
2083
vop2_crtc_duplicate_state(struct drm_crtc * crtc)2084 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
2085 {
2086 struct rockchip_crtc_state *vcstate;
2087
2088 if (WARN_ON(!crtc->state))
2089 return NULL;
2090
2091 vcstate = kmemdup(to_rockchip_crtc_state(crtc->state),
2092 sizeof(*vcstate), GFP_KERNEL);
2093 if (!vcstate)
2094 return NULL;
2095
2096 __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
2097
2098 return &vcstate->base;
2099 }
2100
vop2_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)2101 static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
2102 struct drm_crtc_state *state)
2103 {
2104 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
2105
2106 __drm_atomic_helper_crtc_destroy_state(&vcstate->base);
2107 kfree(vcstate);
2108 }
2109
vop2_crtc_reset(struct drm_crtc * crtc)2110 static void vop2_crtc_reset(struct drm_crtc *crtc)
2111 {
2112 struct rockchip_crtc_state *vcstate =
2113 kzalloc(sizeof(*vcstate), GFP_KERNEL);
2114
2115 if (crtc->state)
2116 vop2_crtc_destroy_state(crtc, crtc->state);
2117
2118 if (vcstate)
2119 __drm_atomic_helper_crtc_reset(crtc, &vcstate->base);
2120 else
2121 __drm_atomic_helper_crtc_reset(crtc, NULL);
2122 }
2123
2124 static const struct drm_crtc_funcs vop2_crtc_funcs = {
2125 .set_config = drm_atomic_helper_set_config,
2126 .page_flip = drm_atomic_helper_page_flip,
2127 .destroy = drm_crtc_cleanup,
2128 .reset = vop2_crtc_reset,
2129 .atomic_duplicate_state = vop2_crtc_duplicate_state,
2130 .atomic_destroy_state = vop2_crtc_destroy_state,
2131 .enable_vblank = vop2_crtc_enable_vblank,
2132 .disable_vblank = vop2_crtc_disable_vblank,
2133 };
2134
vop2_isr(int irq,void * data)2135 static irqreturn_t vop2_isr(int irq, void *data)
2136 {
2137 struct vop2 *vop2 = data;
2138 const struct vop2_data *vop2_data = vop2->data;
2139 u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM];
2140 int ret = IRQ_NONE;
2141 int i;
2142
2143 /*
2144 * The irq is shared with the iommu. If the runtime-pm state of the
2145 * vop2-device is disabled the irq has to be targeted at the iommu.
2146 */
2147 if (!pm_runtime_get_if_in_use(vop2->dev))
2148 return IRQ_NONE;
2149
2150 for (i = 0; i < vop2_data->nr_vps; i++) {
2151 struct vop2_video_port *vp = &vop2->vps[i];
2152 struct drm_crtc *crtc = &vp->crtc;
2153 u32 irqs;
2154
2155 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
2156 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
2157
2158 if (irqs & VP_INT_DSP_HOLD_VALID) {
2159 complete(&vp->dsp_hold_completion);
2160 ret = IRQ_HANDLED;
2161 }
2162
2163 if (irqs & VP_INT_FS_FIELD) {
2164 drm_crtc_handle_vblank(crtc);
2165 spin_lock(&crtc->dev->event_lock);
2166 if (vp->event) {
2167 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
2168
2169 if (!(val & BIT(vp->id))) {
2170 drm_crtc_send_vblank_event(crtc, vp->event);
2171 vp->event = NULL;
2172 drm_crtc_vblank_put(crtc);
2173 }
2174 }
2175 spin_unlock(&crtc->dev->event_lock);
2176
2177 ret = IRQ_HANDLED;
2178 }
2179
2180 if (irqs & VP_INT_POST_BUF_EMPTY) {
2181 drm_err_ratelimited(vop2->drm,
2182 "POST_BUF_EMPTY irq err at vp%d\n",
2183 vp->id);
2184 ret = IRQ_HANDLED;
2185 }
2186 }
2187
2188 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
2189 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
2190 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
2191 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
2192
2193 for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) {
2194 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) {
2195 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
2196 ret = IRQ_HANDLED;
2197 }
2198 }
2199
2200 pm_runtime_put(vop2->dev);
2201
2202 return ret;
2203 }
2204
vop2_plane_init(struct vop2 * vop2,struct vop2_win * win,unsigned long possible_crtcs)2205 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
2206 unsigned long possible_crtcs)
2207 {
2208 const struct vop2_win_data *win_data = win->data;
2209 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2210 BIT(DRM_MODE_BLEND_PREMULTI) |
2211 BIT(DRM_MODE_BLEND_COVERAGE);
2212 int ret;
2213
2214 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
2215 &vop2_plane_funcs, win_data->formats,
2216 win_data->nformats,
2217 win_data->format_modifiers,
2218 win->type, win_data->name);
2219 if (ret) {
2220 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
2221 return ret;
2222 }
2223
2224 drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs);
2225
2226 if (win->data->supported_rotations)
2227 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0,
2228 DRM_MODE_ROTATE_0 |
2229 win->data->supported_rotations);
2230 drm_plane_create_alpha_property(&win->base);
2231 drm_plane_create_blend_mode_property(&win->base, blend_caps);
2232 drm_plane_create_zpos_property(&win->base, win->win_id, 0,
2233 vop2->registered_num_wins - 1);
2234
2235 return 0;
2236 }
2237
find_vp_without_primary(struct vop2 * vop2)2238 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
2239 {
2240 int i;
2241
2242 for (i = 0; i < vop2->data->nr_vps; i++) {
2243 struct vop2_video_port *vp = &vop2->vps[i];
2244
2245 if (!vp->crtc.port)
2246 continue;
2247 if (vp->primary_plane)
2248 continue;
2249
2250 return vp;
2251 }
2252
2253 return NULL;
2254 }
2255
2256 #define NR_LAYERS 6
2257
vop2_create_crtcs(struct vop2 * vop2)2258 static int vop2_create_crtcs(struct vop2 *vop2)
2259 {
2260 const struct vop2_data *vop2_data = vop2->data;
2261 struct drm_device *drm = vop2->drm;
2262 struct device *dev = vop2->dev;
2263 struct drm_plane *plane;
2264 struct device_node *port;
2265 struct vop2_video_port *vp;
2266 int i, nvp, nvps = 0;
2267 int ret;
2268
2269 for (i = 0; i < vop2_data->nr_vps; i++) {
2270 const struct vop2_video_port_data *vp_data;
2271 struct device_node *np;
2272 char dclk_name[9];
2273
2274 vp_data = &vop2_data->vp[i];
2275 vp = &vop2->vps[i];
2276 vp->vop2 = vop2;
2277 vp->id = vp_data->id;
2278 vp->regs = vp_data->regs;
2279 vp->data = vp_data;
2280
2281 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
2282 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
2283 if (IS_ERR(vp->dclk)) {
2284 drm_err(vop2->drm, "failed to get %s\n", dclk_name);
2285 return PTR_ERR(vp->dclk);
2286 }
2287
2288 np = of_graph_get_remote_node(dev->of_node, i, -1);
2289 if (!np) {
2290 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
2291 continue;
2292 }
2293 of_node_put(np);
2294
2295 port = of_graph_get_port_by_id(dev->of_node, i);
2296 if (!port) {
2297 drm_err(vop2->drm, "no port node found for video_port%d\n", i);
2298 return -ENOENT;
2299 }
2300
2301 vp->crtc.port = port;
2302 nvps++;
2303 }
2304
2305 nvp = 0;
2306 for (i = 0; i < vop2->registered_num_wins; i++) {
2307 struct vop2_win *win = &vop2->win[i];
2308 u32 possible_crtcs = 0;
2309
2310 if (vop2->data->soc_id == 3566) {
2311 /*
2312 * On RK3566 these windows don't have an independent
2313 * framebuffer. They share the framebuffer with smart0,
2314 * esmart0 and cluster0 respectively.
2315 */
2316 switch (win->data->phys_id) {
2317 case ROCKCHIP_VOP2_SMART1:
2318 case ROCKCHIP_VOP2_ESMART1:
2319 case ROCKCHIP_VOP2_CLUSTER1:
2320 continue;
2321 }
2322 }
2323
2324 if (win->type == DRM_PLANE_TYPE_PRIMARY) {
2325 vp = find_vp_without_primary(vop2);
2326 if (vp) {
2327 possible_crtcs = BIT(nvp);
2328 vp->primary_plane = win;
2329 nvp++;
2330 } else {
2331 /* change the unused primary window to overlay window */
2332 win->type = DRM_PLANE_TYPE_OVERLAY;
2333 }
2334 }
2335
2336 if (win->type == DRM_PLANE_TYPE_OVERLAY)
2337 possible_crtcs = (1 << nvps) - 1;
2338
2339 ret = vop2_plane_init(vop2, win, possible_crtcs);
2340 if (ret) {
2341 drm_err(vop2->drm, "failed to init plane %s: %d\n",
2342 win->data->name, ret);
2343 return ret;
2344 }
2345 }
2346
2347 for (i = 0; i < vop2_data->nr_vps; i++) {
2348 vp = &vop2->vps[i];
2349
2350 if (!vp->crtc.port)
2351 continue;
2352
2353 plane = &vp->primary_plane->base;
2354
2355 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL,
2356 &vop2_crtc_funcs,
2357 "video_port%d", vp->id);
2358 if (ret) {
2359 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
2360 return ret;
2361 }
2362
2363 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs);
2364
2365 init_completion(&vp->dsp_hold_completion);
2366 }
2367
2368 /*
2369 * On the VOP2 it's very hard to change the number of layers on a VP
2370 * during runtime, so we distribute the layers equally over the used
2371 * VPs
2372 */
2373 for (i = 0; i < vop2->data->nr_vps; i++) {
2374 struct vop2_video_port *vp = &vop2->vps[i];
2375
2376 if (vp->crtc.port)
2377 vp->nlayers = NR_LAYERS / nvps;
2378 }
2379
2380 return 0;
2381 }
2382
vop2_destroy_crtcs(struct vop2 * vop2)2383 static void vop2_destroy_crtcs(struct vop2 *vop2)
2384 {
2385 struct drm_device *drm = vop2->drm;
2386 struct list_head *crtc_list = &drm->mode_config.crtc_list;
2387 struct list_head *plane_list = &drm->mode_config.plane_list;
2388 struct drm_crtc *crtc, *tmpc;
2389 struct drm_plane *plane, *tmpp;
2390
2391 list_for_each_entry_safe(plane, tmpp, plane_list, head)
2392 drm_plane_cleanup(plane);
2393
2394 /*
2395 * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane()
2396 * references the CRTC.
2397 */
2398 list_for_each_entry_safe(crtc, tmpc, crtc_list, head) {
2399 of_node_put(crtc->port);
2400 drm_crtc_cleanup(crtc);
2401 }
2402 }
2403
vop2_find_rgb_encoder(struct vop2 * vop2)2404 static int vop2_find_rgb_encoder(struct vop2 *vop2)
2405 {
2406 struct device_node *node = vop2->dev->of_node;
2407 struct device_node *endpoint;
2408 int i;
2409
2410 for (i = 0; i < vop2->data->nr_vps; i++) {
2411 endpoint = of_graph_get_endpoint_by_regs(node, i,
2412 ROCKCHIP_VOP2_EP_RGB0);
2413 if (!endpoint)
2414 continue;
2415
2416 of_node_put(endpoint);
2417 return i;
2418 }
2419
2420 return -ENOENT;
2421 }
2422
2423 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
2424 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
2425 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
2426 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
2427 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
2428 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
2429 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
2430 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
2431 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
2432 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
2433 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
2434 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15),
2435 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31),
2436 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
2437 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
2438 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
2439
2440 /* Scale */
2441 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
2442 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31),
2443 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15),
2444 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13),
2445 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3),
2446 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28),
2447 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29),
2448
2449 /* cluster regs */
2450 [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1),
2451 [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0),
2452 [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7),
2453
2454 /* afbc regs */
2455 [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6),
2456 [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9),
2457 [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10),
2458 [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4),
2459 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7),
2460 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8),
2461 [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31),
2462 [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31),
2463 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15),
2464 [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
2465 [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
2466 [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
2467 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
2468 [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
2469 [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
2470 [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
2471 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3),
2472 [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff },
2473 [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff },
2474 [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff },
2475 [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff },
2476 [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff },
2477 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2478 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2479 [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff },
2480 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2481 [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff },
2482 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2483 [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff },
2484 [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff },
2485 };
2486
vop2_cluster_init(struct vop2_win * win)2487 static int vop2_cluster_init(struct vop2_win *win)
2488 {
2489 struct vop2 *vop2 = win->vop2;
2490 struct reg_field *cluster_regs;
2491 int ret, i;
2492
2493 cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs),
2494 GFP_KERNEL);
2495 if (!cluster_regs)
2496 return -ENOMEM;
2497
2498 for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++)
2499 if (cluster_regs[i].reg != 0xffffffff)
2500 cluster_regs[i].reg += win->offset;
2501
2502 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2503 cluster_regs,
2504 ARRAY_SIZE(vop2_cluster_regs));
2505
2506 kfree(cluster_regs);
2507
2508 return ret;
2509 };
2510
2511 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
2512 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0),
2513 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5),
2514 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12),
2515 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14),
2516 [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16),
2517 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31),
2518 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31),
2519 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28),
2520 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31),
2521 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31),
2522 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17),
2523 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15),
2524 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31),
2525 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0),
2526 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1),
2527 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3),
2528 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31),
2529 [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29),
2530 [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31),
2531
2532 /* Scale */
2533 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15),
2534 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31),
2535 [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15),
2536 [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31),
2537 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1),
2538 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3),
2539 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5),
2540 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7),
2541 [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9),
2542 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11),
2543 [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13),
2544 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15),
2545 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17),
2546 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8),
2547 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9),
2548 [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10),
2549 [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11),
2550 [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff },
2551 [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff },
2552 [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff },
2553 [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff },
2554 [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff },
2555 [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff },
2556 [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff },
2557 [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff },
2558 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff },
2559 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff },
2560 [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff },
2561 [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
2562 [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
2563 [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
2564 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
2565 [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
2566 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
2567 [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },
2568 [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff },
2569 };
2570
vop2_esmart_init(struct vop2_win * win)2571 static int vop2_esmart_init(struct vop2_win *win)
2572 {
2573 struct vop2 *vop2 = win->vop2;
2574 struct reg_field *esmart_regs;
2575 int ret, i;
2576
2577 esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs),
2578 GFP_KERNEL);
2579 if (!esmart_regs)
2580 return -ENOMEM;
2581
2582 for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++)
2583 if (esmart_regs[i].reg != 0xffffffff)
2584 esmart_regs[i].reg += win->offset;
2585
2586 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2587 esmart_regs,
2588 ARRAY_SIZE(vop2_esmart_regs));
2589
2590 kfree(esmart_regs);
2591
2592 return ret;
2593 };
2594
vop2_win_init(struct vop2 * vop2)2595 static int vop2_win_init(struct vop2 *vop2)
2596 {
2597 const struct vop2_data *vop2_data = vop2->data;
2598 struct vop2_win *win;
2599 int i, ret;
2600
2601 for (i = 0; i < vop2_data->win_size; i++) {
2602 const struct vop2_win_data *win_data = &vop2_data->win[i];
2603
2604 win = &vop2->win[i];
2605 win->data = win_data;
2606 win->type = win_data->type;
2607 win->offset = win_data->base;
2608 win->win_id = i;
2609 win->vop2 = vop2;
2610 if (vop2_cluster_window(win))
2611 ret = vop2_cluster_init(win);
2612 else
2613 ret = vop2_esmart_init(win);
2614 if (ret)
2615 return ret;
2616 }
2617
2618 vop2->registered_num_wins = vop2_data->win_size;
2619
2620 return 0;
2621 }
2622
2623 /*
2624 * The window registers are only updated when config done is written.
2625 * Until that they read back the old value. As we read-modify-write
2626 * these registers mark them as non-volatile. This makes sure we read
2627 * the new values from the regmap register cache.
2628 */
2629 static const struct regmap_range vop2_nonvolatile_range[] = {
2630 regmap_reg_range(0x1000, 0x23ff),
2631 };
2632
2633 static const struct regmap_access_table vop2_volatile_table = {
2634 .no_ranges = vop2_nonvolatile_range,
2635 .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range),
2636 };
2637
2638 static const struct regmap_config vop2_regmap_config = {
2639 .reg_bits = 32,
2640 .val_bits = 32,
2641 .reg_stride = 4,
2642 .max_register = 0x3000,
2643 .name = "vop2",
2644 .volatile_table = &vop2_volatile_table,
2645 .cache_type = REGCACHE_RBTREE,
2646 };
2647
vop2_bind(struct device * dev,struct device * master,void * data)2648 static int vop2_bind(struct device *dev, struct device *master, void *data)
2649 {
2650 struct platform_device *pdev = to_platform_device(dev);
2651 const struct vop2_data *vop2_data;
2652 struct drm_device *drm = data;
2653 struct vop2 *vop2;
2654 struct resource *res;
2655 size_t alloc_size;
2656 int ret;
2657
2658 vop2_data = of_device_get_match_data(dev);
2659 if (!vop2_data)
2660 return -ENODEV;
2661
2662 /* Allocate vop2 struct and its vop2_win array */
2663 alloc_size = struct_size(vop2, win, vop2_data->win_size);
2664 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2665 if (!vop2)
2666 return -ENOMEM;
2667
2668 vop2->dev = dev;
2669 vop2->data = vop2_data;
2670 vop2->drm = drm;
2671
2672 dev_set_drvdata(dev, vop2);
2673
2674 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop");
2675 if (!res) {
2676 drm_err(vop2->drm, "failed to get vop2 register byname\n");
2677 return -EINVAL;
2678 }
2679
2680 vop2->regs = devm_ioremap_resource(dev, res);
2681 if (IS_ERR(vop2->regs))
2682 return PTR_ERR(vop2->regs);
2683 vop2->len = resource_size(res);
2684
2685 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
2686 if (IS_ERR(vop2->map))
2687 return PTR_ERR(vop2->map);
2688
2689 ret = vop2_win_init(vop2);
2690 if (ret)
2691 return ret;
2692
2693 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut");
2694 if (res) {
2695 vop2->lut_regs = devm_ioremap_resource(dev, res);
2696 if (IS_ERR(vop2->lut_regs))
2697 return PTR_ERR(vop2->lut_regs);
2698 }
2699
2700 vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
2701
2702 vop2->hclk = devm_clk_get(vop2->dev, "hclk");
2703 if (IS_ERR(vop2->hclk)) {
2704 drm_err(vop2->drm, "failed to get hclk source\n");
2705 return PTR_ERR(vop2->hclk);
2706 }
2707
2708 vop2->aclk = devm_clk_get(vop2->dev, "aclk");
2709 if (IS_ERR(vop2->aclk)) {
2710 drm_err(vop2->drm, "failed to get aclk source\n");
2711 return PTR_ERR(vop2->aclk);
2712 }
2713
2714 vop2->irq = platform_get_irq(pdev, 0);
2715 if (vop2->irq < 0) {
2716 drm_err(vop2->drm, "cannot find irq for vop2\n");
2717 return vop2->irq;
2718 }
2719
2720 mutex_init(&vop2->vop2_lock);
2721
2722 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
2723 if (ret)
2724 return ret;
2725
2726 ret = vop2_create_crtcs(vop2);
2727 if (ret)
2728 return ret;
2729
2730 ret = vop2_find_rgb_encoder(vop2);
2731 if (ret >= 0) {
2732 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
2733 vop2->drm, ret);
2734 if (IS_ERR(vop2->rgb)) {
2735 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {
2736 ret = PTR_ERR(vop2->rgb);
2737 goto err_crtcs;
2738 }
2739 vop2->rgb = NULL;
2740 }
2741 }
2742
2743 rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
2744
2745 pm_runtime_enable(&pdev->dev);
2746
2747 return 0;
2748
2749 err_crtcs:
2750 vop2_destroy_crtcs(vop2);
2751
2752 return ret;
2753 }
2754
vop2_unbind(struct device * dev,struct device * master,void * data)2755 static void vop2_unbind(struct device *dev, struct device *master, void *data)
2756 {
2757 struct vop2 *vop2 = dev_get_drvdata(dev);
2758
2759 pm_runtime_disable(dev);
2760
2761 if (vop2->rgb)
2762 rockchip_rgb_fini(vop2->rgb);
2763
2764 vop2_destroy_crtcs(vop2);
2765 }
2766
2767 const struct component_ops vop2_component_ops = {
2768 .bind = vop2_bind,
2769 .unbind = vop2_unbind,
2770 };
2771 EXPORT_SYMBOL_GPL(vop2_component_ops);
2772