1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2020 Marvell.
5 */
6
7 #include <linux/bitfield.h>
8
9 #include "rvu_struct.h"
10 #include "rvu_reg.h"
11 #include "rvu.h"
12 #include "npc.h"
13 #include "rvu_npc_fs.h"
14 #include "rvu_npc_hash.h"
15
16 static const char * const npc_flow_names[] = {
17 [NPC_DMAC] = "dmac",
18 [NPC_SMAC] = "smac",
19 [NPC_ETYPE] = "ether type",
20 [NPC_VLAN_ETYPE_CTAG] = "vlan ether type ctag",
21 [NPC_VLAN_ETYPE_STAG] = "vlan ether type stag",
22 [NPC_OUTER_VID] = "outer vlan id",
23 [NPC_INNER_VID] = "inner vlan id",
24 [NPC_TOS] = "tos",
25 [NPC_IPFRAG_IPV4] = "fragmented IPv4 header ",
26 [NPC_SIP_IPV4] = "ipv4 source ip",
27 [NPC_DIP_IPV4] = "ipv4 destination ip",
28 [NPC_IPFRAG_IPV6] = "fragmented IPv6 header ",
29 [NPC_SIP_IPV6] = "ipv6 source ip",
30 [NPC_DIP_IPV6] = "ipv6 destination ip",
31 [NPC_IPPROTO_TCP] = "ip proto tcp",
32 [NPC_IPPROTO_UDP] = "ip proto udp",
33 [NPC_IPPROTO_SCTP] = "ip proto sctp",
34 [NPC_IPPROTO_ICMP] = "ip proto icmp",
35 [NPC_IPPROTO_ICMP6] = "ip proto icmp6",
36 [NPC_IPPROTO_AH] = "ip proto AH",
37 [NPC_IPPROTO_ESP] = "ip proto ESP",
38 [NPC_SPORT_TCP] = "tcp source port",
39 [NPC_DPORT_TCP] = "tcp destination port",
40 [NPC_SPORT_UDP] = "udp source port",
41 [NPC_DPORT_UDP] = "udp destination port",
42 [NPC_SPORT_SCTP] = "sctp source port",
43 [NPC_DPORT_SCTP] = "sctp destination port",
44 [NPC_LXMB] = "Mcast/Bcast header ",
45 [NPC_IPSEC_SPI] = "SPI ",
46 [NPC_UNKNOWN] = "unknown",
47 };
48
npc_is_feature_supported(struct rvu * rvu,u64 features,u8 intf)49 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf)
50 {
51 struct npc_mcam *mcam = &rvu->hw->mcam;
52 u64 mcam_features;
53 u64 unsupported;
54
55 mcam_features = is_npc_intf_tx(intf) ? mcam->tx_features : mcam->rx_features;
56 unsupported = (mcam_features ^ features) & ~mcam_features;
57
58 /* Return false if at least one of the input flows is not extracted */
59 return !unsupported;
60 }
61
npc_get_field_name(u8 hdr)62 const char *npc_get_field_name(u8 hdr)
63 {
64 if (hdr >= ARRAY_SIZE(npc_flow_names))
65 return npc_flow_names[NPC_UNKNOWN];
66
67 return npc_flow_names[hdr];
68 }
69
70 /* Compute keyword masks and figure out the number of keywords a field
71 * spans in the key.
72 */
npc_set_kw_masks(struct npc_mcam * mcam,u8 type,u8 nr_bits,int start_kwi,int offset,u8 intf)73 static void npc_set_kw_masks(struct npc_mcam *mcam, u8 type,
74 u8 nr_bits, int start_kwi, int offset, u8 intf)
75 {
76 struct npc_key_field *field = &mcam->rx_key_fields[type];
77 u8 bits_in_kw;
78 int max_kwi;
79
80 if (mcam->banks_per_entry == 1)
81 max_kwi = 1; /* NPC_MCAM_KEY_X1 */
82 else if (mcam->banks_per_entry == 2)
83 max_kwi = 3; /* NPC_MCAM_KEY_X2 */
84 else
85 max_kwi = 6; /* NPC_MCAM_KEY_X4 */
86
87 if (is_npc_intf_tx(intf))
88 field = &mcam->tx_key_fields[type];
89
90 if (offset + nr_bits <= 64) {
91 /* one KW only */
92 if (start_kwi > max_kwi)
93 return;
94 field->kw_mask[start_kwi] |= GENMASK_ULL(nr_bits - 1, 0)
95 << offset;
96 field->nr_kws = 1;
97 } else if (offset + nr_bits > 64 &&
98 offset + nr_bits <= 128) {
99 /* two KWs */
100 if (start_kwi + 1 > max_kwi)
101 return;
102 /* first KW mask */
103 bits_in_kw = 64 - offset;
104 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0)
105 << offset;
106 /* second KW mask i.e. mask for rest of bits */
107 bits_in_kw = nr_bits + offset - 64;
108 field->kw_mask[start_kwi + 1] |= GENMASK_ULL(bits_in_kw - 1, 0);
109 field->nr_kws = 2;
110 } else {
111 /* three KWs */
112 if (start_kwi + 2 > max_kwi)
113 return;
114 /* first KW mask */
115 bits_in_kw = 64 - offset;
116 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0)
117 << offset;
118 /* second KW mask */
119 field->kw_mask[start_kwi + 1] = ~0ULL;
120 /* third KW mask i.e. mask for rest of bits */
121 bits_in_kw = nr_bits + offset - 128;
122 field->kw_mask[start_kwi + 2] |= GENMASK_ULL(bits_in_kw - 1, 0);
123 field->nr_kws = 3;
124 }
125 }
126
127 /* Helper function to figure out whether field exists in the key */
npc_is_field_present(struct rvu * rvu,enum key_fields type,u8 intf)128 static bool npc_is_field_present(struct rvu *rvu, enum key_fields type, u8 intf)
129 {
130 struct npc_mcam *mcam = &rvu->hw->mcam;
131 struct npc_key_field *input;
132
133 input = &mcam->rx_key_fields[type];
134 if (is_npc_intf_tx(intf))
135 input = &mcam->tx_key_fields[type];
136
137 return input->nr_kws > 0;
138 }
139
npc_is_same(struct npc_key_field * input,struct npc_key_field * field)140 static bool npc_is_same(struct npc_key_field *input,
141 struct npc_key_field *field)
142 {
143 return memcmp(&input->layer_mdata, &field->layer_mdata,
144 sizeof(struct npc_layer_mdata)) == 0;
145 }
146
npc_set_layer_mdata(struct npc_mcam * mcam,enum key_fields type,u64 cfg,u8 lid,u8 lt,u8 intf)147 static void npc_set_layer_mdata(struct npc_mcam *mcam, enum key_fields type,
148 u64 cfg, u8 lid, u8 lt, u8 intf)
149 {
150 struct npc_key_field *input = &mcam->rx_key_fields[type];
151
152 if (is_npc_intf_tx(intf))
153 input = &mcam->tx_key_fields[type];
154
155 input->layer_mdata.hdr = FIELD_GET(NPC_HDR_OFFSET, cfg);
156 input->layer_mdata.key = FIELD_GET(NPC_KEY_OFFSET, cfg);
157 input->layer_mdata.len = FIELD_GET(NPC_BYTESM, cfg) + 1;
158 input->layer_mdata.ltype = lt;
159 input->layer_mdata.lid = lid;
160 }
161
npc_check_overlap_fields(struct npc_key_field * input1,struct npc_key_field * input2)162 static bool npc_check_overlap_fields(struct npc_key_field *input1,
163 struct npc_key_field *input2)
164 {
165 int kwi;
166
167 /* Fields with same layer id and different ltypes are mutually
168 * exclusive hence they can be overlapped
169 */
170 if (input1->layer_mdata.lid == input2->layer_mdata.lid &&
171 input1->layer_mdata.ltype != input2->layer_mdata.ltype)
172 return false;
173
174 for (kwi = 0; kwi < NPC_MAX_KWS_IN_KEY; kwi++) {
175 if (input1->kw_mask[kwi] & input2->kw_mask[kwi])
176 return true;
177 }
178
179 return false;
180 }
181
182 /* Helper function to check whether given field overlaps with any other fields
183 * in the key. Due to limitations on key size and the key extraction profile in
184 * use higher layers can overwrite lower layer's header fields. Hence overlap
185 * needs to be checked.
186 */
npc_check_overlap(struct rvu * rvu,int blkaddr,enum key_fields type,u8 start_lid,u8 intf)187 static bool npc_check_overlap(struct rvu *rvu, int blkaddr,
188 enum key_fields type, u8 start_lid, u8 intf)
189 {
190 struct npc_mcam *mcam = &rvu->hw->mcam;
191 struct npc_key_field *dummy, *input;
192 int start_kwi, offset;
193 u8 nr_bits, lid, lt, ld;
194 u64 cfg;
195
196 dummy = &mcam->rx_key_fields[NPC_UNKNOWN];
197 input = &mcam->rx_key_fields[type];
198
199 if (is_npc_intf_tx(intf)) {
200 dummy = &mcam->tx_key_fields[NPC_UNKNOWN];
201 input = &mcam->tx_key_fields[type];
202 }
203
204 for (lid = start_lid; lid < NPC_MAX_LID; lid++) {
205 for (lt = 0; lt < NPC_MAX_LT; lt++) {
206 for (ld = 0; ld < NPC_MAX_LD; ld++) {
207 cfg = rvu_read64(rvu, blkaddr,
208 NPC_AF_INTFX_LIDX_LTX_LDX_CFG
209 (intf, lid, lt, ld));
210 if (!FIELD_GET(NPC_LDATA_EN, cfg))
211 continue;
212 memset(dummy, 0, sizeof(struct npc_key_field));
213 npc_set_layer_mdata(mcam, NPC_UNKNOWN, cfg,
214 lid, lt, intf);
215 /* exclude input */
216 if (npc_is_same(input, dummy))
217 continue;
218 start_kwi = dummy->layer_mdata.key / 8;
219 offset = (dummy->layer_mdata.key * 8) % 64;
220 nr_bits = dummy->layer_mdata.len * 8;
221 /* form KW masks */
222 npc_set_kw_masks(mcam, NPC_UNKNOWN, nr_bits,
223 start_kwi, offset, intf);
224 /* check any input field bits falls in any
225 * other field bits.
226 */
227 if (npc_check_overlap_fields(dummy, input))
228 return true;
229 }
230 }
231 }
232
233 return false;
234 }
235
npc_check_field(struct rvu * rvu,int blkaddr,enum key_fields type,u8 intf)236 static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type,
237 u8 intf)
238 {
239 if (!npc_is_field_present(rvu, type, intf) ||
240 npc_check_overlap(rvu, blkaddr, type, 0, intf))
241 return false;
242 return true;
243 }
244
npc_scan_exact_result(struct npc_mcam * mcam,u8 bit_number,u8 key_nibble,u8 intf)245 static void npc_scan_exact_result(struct npc_mcam *mcam, u8 bit_number,
246 u8 key_nibble, u8 intf)
247 {
248 u8 offset = (key_nibble * 4) % 64; /* offset within key word */
249 u8 kwi = (key_nibble * 4) / 64; /* which word in key */
250 u8 nr_bits = 4; /* bits in a nibble */
251 u8 type;
252
253 switch (bit_number) {
254 case 40 ... 43:
255 type = NPC_EXACT_RESULT;
256 break;
257
258 default:
259 return;
260 }
261 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf);
262 }
263
npc_scan_parse_result(struct npc_mcam * mcam,u8 bit_number,u8 key_nibble,u8 intf)264 static void npc_scan_parse_result(struct npc_mcam *mcam, u8 bit_number,
265 u8 key_nibble, u8 intf)
266 {
267 u8 offset = (key_nibble * 4) % 64; /* offset within key word */
268 u8 kwi = (key_nibble * 4) / 64; /* which word in key */
269 u8 nr_bits = 4; /* bits in a nibble */
270 u8 type;
271
272 switch (bit_number) {
273 case 0 ... 2:
274 type = NPC_CHAN;
275 break;
276 case 3:
277 type = NPC_ERRLEV;
278 break;
279 case 4 ... 5:
280 type = NPC_ERRCODE;
281 break;
282 case 6:
283 type = NPC_LXMB;
284 break;
285 /* check for LTYPE only as of now */
286 case 9:
287 type = NPC_LA;
288 break;
289 case 12:
290 type = NPC_LB;
291 break;
292 case 15:
293 type = NPC_LC;
294 break;
295 case 18:
296 type = NPC_LD;
297 break;
298 case 21:
299 type = NPC_LE;
300 break;
301 case 24:
302 type = NPC_LF;
303 break;
304 case 27:
305 type = NPC_LG;
306 break;
307 case 30:
308 type = NPC_LH;
309 break;
310 default:
311 return;
312 }
313
314 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf);
315 }
316
npc_handle_multi_layer_fields(struct rvu * rvu,int blkaddr,u8 intf)317 static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf)
318 {
319 struct npc_mcam *mcam = &rvu->hw->mcam;
320 struct npc_key_field *key_fields;
321 /* Ether type can come from three layers
322 * (ethernet, single tagged, double tagged)
323 */
324 struct npc_key_field *etype_ether;
325 struct npc_key_field *etype_tag1;
326 struct npc_key_field *etype_tag2;
327 /* Outer VLAN TCI can come from two layers
328 * (single tagged, double tagged)
329 */
330 struct npc_key_field *vlan_tag1;
331 struct npc_key_field *vlan_tag2;
332 /* Inner VLAN TCI for double tagged frames */
333 struct npc_key_field *vlan_tag3;
334 u64 *features;
335 u8 start_lid;
336 int i;
337
338 key_fields = mcam->rx_key_fields;
339 features = &mcam->rx_features;
340
341 if (is_npc_intf_tx(intf)) {
342 key_fields = mcam->tx_key_fields;
343 features = &mcam->tx_features;
344 }
345
346 /* Handle header fields which can come from multiple layers like
347 * etype, outer vlan tci. These fields should have same position in
348 * the key otherwise to install a mcam rule more than one entry is
349 * needed which complicates mcam space management.
350 */
351 etype_ether = &key_fields[NPC_ETYPE_ETHER];
352 etype_tag1 = &key_fields[NPC_ETYPE_TAG1];
353 etype_tag2 = &key_fields[NPC_ETYPE_TAG2];
354 vlan_tag1 = &key_fields[NPC_VLAN_TAG1];
355 vlan_tag2 = &key_fields[NPC_VLAN_TAG2];
356 vlan_tag3 = &key_fields[NPC_VLAN_TAG3];
357
358 /* if key profile programmed does not extract Ethertype at all */
359 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) {
360 dev_err(rvu->dev, "mkex: Ethertype is not extracted.\n");
361 goto vlan_tci;
362 }
363
364 /* if key profile programmed extracts Ethertype from one layer */
365 if (etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws)
366 key_fields[NPC_ETYPE] = *etype_ether;
367 if (!etype_ether->nr_kws && etype_tag1->nr_kws && !etype_tag2->nr_kws)
368 key_fields[NPC_ETYPE] = *etype_tag1;
369 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && etype_tag2->nr_kws)
370 key_fields[NPC_ETYPE] = *etype_tag2;
371
372 /* if key profile programmed extracts Ethertype from multiple layers */
373 if (etype_ether->nr_kws && etype_tag1->nr_kws) {
374 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
375 if (etype_ether->kw_mask[i] != etype_tag1->kw_mask[i]) {
376 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and tagged pkts.\n");
377 goto vlan_tci;
378 }
379 }
380 key_fields[NPC_ETYPE] = *etype_tag1;
381 }
382 if (etype_ether->nr_kws && etype_tag2->nr_kws) {
383 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
384 if (etype_ether->kw_mask[i] != etype_tag2->kw_mask[i]) {
385 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and double tagged pkts.\n");
386 goto vlan_tci;
387 }
388 }
389 key_fields[NPC_ETYPE] = *etype_tag2;
390 }
391 if (etype_tag1->nr_kws && etype_tag2->nr_kws) {
392 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
393 if (etype_tag1->kw_mask[i] != etype_tag2->kw_mask[i]) {
394 dev_err(rvu->dev, "mkex: Etype pos is different for tagged and double tagged pkts.\n");
395 goto vlan_tci;
396 }
397 }
398 key_fields[NPC_ETYPE] = *etype_tag2;
399 }
400
401 /* check none of higher layers overwrite Ethertype */
402 start_lid = key_fields[NPC_ETYPE].layer_mdata.lid + 1;
403 if (npc_check_overlap(rvu, blkaddr, NPC_ETYPE, start_lid, intf)) {
404 dev_err(rvu->dev, "mkex: Ethertype is overwritten by higher layers.\n");
405 goto vlan_tci;
406 }
407 *features |= BIT_ULL(NPC_ETYPE);
408 vlan_tci:
409 /* if key profile does not extract outer vlan tci at all */
410 if (!vlan_tag1->nr_kws && !vlan_tag2->nr_kws) {
411 dev_err(rvu->dev, "mkex: Outer vlan tci is not extracted.\n");
412 goto done;
413 }
414
415 /* if key profile extracts outer vlan tci from one layer */
416 if (vlan_tag1->nr_kws && !vlan_tag2->nr_kws)
417 key_fields[NPC_OUTER_VID] = *vlan_tag1;
418 if (!vlan_tag1->nr_kws && vlan_tag2->nr_kws)
419 key_fields[NPC_OUTER_VID] = *vlan_tag2;
420
421 /* if key profile extracts outer vlan tci from multiple layers */
422 if (vlan_tag1->nr_kws && vlan_tag2->nr_kws) {
423 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
424 if (vlan_tag1->kw_mask[i] != vlan_tag2->kw_mask[i]) {
425 dev_err(rvu->dev, "mkex: Out vlan tci pos is different for tagged and double tagged pkts.\n");
426 goto done;
427 }
428 }
429 key_fields[NPC_OUTER_VID] = *vlan_tag2;
430 }
431 /* check none of higher layers overwrite outer vlan tci */
432 start_lid = key_fields[NPC_OUTER_VID].layer_mdata.lid + 1;
433 if (npc_check_overlap(rvu, blkaddr, NPC_OUTER_VID, start_lid, intf)) {
434 dev_err(rvu->dev, "mkex: Outer vlan tci is overwritten by higher layers.\n");
435 goto done;
436 }
437 *features |= BIT_ULL(NPC_OUTER_VID);
438
439 /* If key profile extracts inner vlan tci */
440 if (vlan_tag3->nr_kws) {
441 key_fields[NPC_INNER_VID] = *vlan_tag3;
442 *features |= BIT_ULL(NPC_INNER_VID);
443 }
444 done:
445 return;
446 }
447
npc_scan_ldata(struct rvu * rvu,int blkaddr,u8 lid,u8 lt,u64 cfg,u8 intf)448 static void npc_scan_ldata(struct rvu *rvu, int blkaddr, u8 lid,
449 u8 lt, u64 cfg, u8 intf)
450 {
451 struct npc_mcam_kex_hash *mkex_hash = rvu->kpu.mkex_hash;
452 struct npc_mcam *mcam = &rvu->hw->mcam;
453 u8 hdr, key, nr_bytes, bit_offset;
454 u8 la_ltype, la_start;
455 /* starting KW index and starting bit position */
456 int start_kwi, offset;
457
458 nr_bytes = FIELD_GET(NPC_BYTESM, cfg) + 1;
459 hdr = FIELD_GET(NPC_HDR_OFFSET, cfg);
460 key = FIELD_GET(NPC_KEY_OFFSET, cfg);
461
462 /* For Tx, Layer A has NIX_INST_HDR_S(64 bytes) preceding
463 * ethernet header.
464 */
465 if (is_npc_intf_tx(intf)) {
466 la_ltype = NPC_LT_LA_IH_NIX_ETHER;
467 la_start = 8;
468 } else {
469 la_ltype = NPC_LT_LA_ETHER;
470 la_start = 0;
471 }
472
473 #define NPC_SCAN_HDR(name, hlid, hlt, hstart, hlen) \
474 do { \
475 start_kwi = key / 8; \
476 offset = (key * 8) % 64; \
477 if (lid == (hlid) && lt == (hlt)) { \
478 if ((hstart) >= hdr && \
479 ((hstart) + (hlen)) <= (hdr + nr_bytes)) { \
480 bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \
481 npc_set_layer_mdata(mcam, (name), cfg, lid, lt, intf); \
482 offset += bit_offset; \
483 start_kwi += offset / 64; \
484 offset %= 64; \
485 npc_set_kw_masks(mcam, (name), (hlen) * 8, \
486 start_kwi, offset, intf); \
487 } \
488 } \
489 } while (0)
490
491 /* List LID, LTYPE, start offset from layer and length(in bytes) of
492 * packet header fields below.
493 * Example: Source IP is 4 bytes and starts at 12th byte of IP header
494 */
495 NPC_SCAN_HDR(NPC_TOS, NPC_LID_LC, NPC_LT_LC_IP, 1, 1);
496 NPC_SCAN_HDR(NPC_IPFRAG_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 6, 1);
497 NPC_SCAN_HDR(NPC_SIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 12, 4);
498 NPC_SCAN_HDR(NPC_DIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 16, 4);
499 NPC_SCAN_HDR(NPC_IPFRAG_IPV6, NPC_LID_LC, NPC_LT_LC_IP6_EXT, 6, 1);
500 if (rvu->hw->cap.npc_hash_extract) {
501 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][0])
502 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 4);
503 else
504 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16);
505
506 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][1])
507 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 4);
508 else
509 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16);
510 } else {
511 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16);
512 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16);
513 }
514
515 NPC_SCAN_HDR(NPC_SPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 0, 2);
516 NPC_SCAN_HDR(NPC_DPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 2, 2);
517 NPC_SCAN_HDR(NPC_SPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 0, 2);
518 NPC_SCAN_HDR(NPC_DPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 2, 2);
519 NPC_SCAN_HDR(NPC_SPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 0, 2);
520 NPC_SCAN_HDR(NPC_DPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 2, 2);
521 NPC_SCAN_HDR(NPC_ETYPE_ETHER, NPC_LID_LA, NPC_LT_LA_ETHER, 12, 2);
522 NPC_SCAN_HDR(NPC_ETYPE_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 4, 2);
523 NPC_SCAN_HDR(NPC_ETYPE_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 8, 2);
524 NPC_SCAN_HDR(NPC_VLAN_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 2, 2);
525 NPC_SCAN_HDR(NPC_VLAN_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 2, 2);
526 NPC_SCAN_HDR(NPC_VLAN_TAG3, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 6, 2);
527 NPC_SCAN_HDR(NPC_DMAC, NPC_LID_LA, la_ltype, la_start, 6);
528
529 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LD, NPC_LT_LD_AH, 4, 4);
530 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LE, NPC_LT_LE_ESP, 0, 4);
531
532 /* SMAC follows the DMAC(which is 6 bytes) */
533 NPC_SCAN_HDR(NPC_SMAC, NPC_LID_LA, la_ltype, la_start + 6, 6);
534 /* PF_FUNC is 2 bytes at 0th byte of NPC_LT_LA_IH_NIX_ETHER */
535 NPC_SCAN_HDR(NPC_PF_FUNC, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 0, 2);
536 }
537
npc_set_features(struct rvu * rvu,int blkaddr,u8 intf)538 static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf)
539 {
540 struct npc_mcam *mcam = &rvu->hw->mcam;
541 u64 *features = &mcam->rx_features;
542 u64 tcp_udp_sctp;
543 int hdr;
544
545 if (is_npc_intf_tx(intf))
546 features = &mcam->tx_features;
547
548 for (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) {
549 if (npc_check_field(rvu, blkaddr, hdr, intf))
550 *features |= BIT_ULL(hdr);
551 }
552
553 tcp_udp_sctp = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) |
554 BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) |
555 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP);
556
557 /* for tcp/udp/sctp corresponding layer type should be in the key */
558 if (*features & tcp_udp_sctp) {
559 if (!npc_check_field(rvu, blkaddr, NPC_LD, intf))
560 *features &= ~tcp_udp_sctp;
561 else
562 *features |= BIT_ULL(NPC_IPPROTO_TCP) |
563 BIT_ULL(NPC_IPPROTO_UDP) |
564 BIT_ULL(NPC_IPPROTO_SCTP);
565 }
566
567 /* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */
568 if (npc_check_field(rvu, blkaddr, NPC_LD, intf)) {
569 *features |= BIT_ULL(NPC_IPPROTO_AH);
570 *features |= BIT_ULL(NPC_IPPROTO_ICMP);
571 *features |= BIT_ULL(NPC_IPPROTO_ICMP6);
572 }
573
574 /* for ESP, check if corresponding layer type is present in the key */
575 if (npc_check_field(rvu, blkaddr, NPC_LE, intf))
576 *features |= BIT_ULL(NPC_IPPROTO_ESP);
577
578 /* for vlan corresponding layer type should be in the key */
579 if (*features & BIT_ULL(NPC_OUTER_VID))
580 if (!npc_check_field(rvu, blkaddr, NPC_LB, intf))
581 *features &= ~BIT_ULL(NPC_OUTER_VID);
582
583 /* Set SPI flag only if AH/ESP and IPSEC_SPI are in the key */
584 if (npc_check_field(rvu, blkaddr, NPC_IPSEC_SPI, intf) &&
585 (*features & (BIT_ULL(NPC_IPPROTO_ESP) | BIT_ULL(NPC_IPPROTO_AH))))
586 *features |= BIT_ULL(NPC_IPSEC_SPI);
587
588 /* for vlan ethertypes corresponding layer type should be in the key */
589 if (npc_check_field(rvu, blkaddr, NPC_LB, intf))
590 *features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) |
591 BIT_ULL(NPC_VLAN_ETYPE_STAG);
592
593 /* for L2M/L2B/L3M/L3B, check if the type is present in the key */
594 if (npc_check_field(rvu, blkaddr, NPC_LXMB, intf))
595 *features |= BIT_ULL(NPC_LXMB);
596 }
597
598 /* Scan key extraction profile and record how fields of our interest
599 * fill the key structure. Also verify Channel and DMAC exists in
600 * key and not overwritten by other header fields.
601 */
npc_scan_kex(struct rvu * rvu,int blkaddr,u8 intf)602 static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf)
603 {
604 struct npc_mcam *mcam = &rvu->hw->mcam;
605 u8 lid, lt, ld, bitnr;
606 u64 cfg, masked_cfg;
607 u8 key_nibble = 0;
608
609 /* Scan and note how parse result is going to be in key.
610 * A bit set in PARSE_NIBBLE_ENA corresponds to a nibble from
611 * parse result in the key. The enabled nibbles from parse result
612 * will be concatenated in key.
613 */
614 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf));
615 masked_cfg = cfg & NPC_PARSE_NIBBLE;
616 for_each_set_bit(bitnr, (unsigned long *)&masked_cfg, 31) {
617 npc_scan_parse_result(mcam, bitnr, key_nibble, intf);
618 key_nibble++;
619 }
620
621 /* Ignore exact match bits for mcam entries except the first rule
622 * which is drop on hit. This first rule is configured explitcitly by
623 * exact match code.
624 */
625 masked_cfg = cfg & NPC_EXACT_NIBBLE;
626 bitnr = NPC_EXACT_NIBBLE_START;
627 for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, NPC_EXACT_NIBBLE_END + 1) {
628 npc_scan_exact_result(mcam, bitnr, key_nibble, intf);
629 key_nibble++;
630 }
631
632 /* Scan and note how layer data is going to be in key */
633 for (lid = 0; lid < NPC_MAX_LID; lid++) {
634 for (lt = 0; lt < NPC_MAX_LT; lt++) {
635 for (ld = 0; ld < NPC_MAX_LD; ld++) {
636 cfg = rvu_read64(rvu, blkaddr,
637 NPC_AF_INTFX_LIDX_LTX_LDX_CFG
638 (intf, lid, lt, ld));
639 if (!FIELD_GET(NPC_LDATA_EN, cfg))
640 continue;
641 npc_scan_ldata(rvu, blkaddr, lid, lt, cfg,
642 intf);
643 }
644 }
645 }
646
647 return 0;
648 }
649
npc_scan_verify_kex(struct rvu * rvu,int blkaddr)650 static int npc_scan_verify_kex(struct rvu *rvu, int blkaddr)
651 {
652 int err;
653
654 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_RX);
655 if (err)
656 return err;
657
658 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_TX);
659 if (err)
660 return err;
661
662 /* Channel is mandatory */
663 if (!npc_is_field_present(rvu, NPC_CHAN, NIX_INTF_RX)) {
664 dev_err(rvu->dev, "Channel not present in Key\n");
665 return -EINVAL;
666 }
667 /* check that none of the fields overwrite channel */
668 if (npc_check_overlap(rvu, blkaddr, NPC_CHAN, 0, NIX_INTF_RX)) {
669 dev_err(rvu->dev, "Channel cannot be overwritten\n");
670 return -EINVAL;
671 }
672
673 npc_set_features(rvu, blkaddr, NIX_INTF_TX);
674 npc_set_features(rvu, blkaddr, NIX_INTF_RX);
675 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_TX);
676 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_RX);
677
678 return 0;
679 }
680
npc_flow_steering_init(struct rvu * rvu,int blkaddr)681 int npc_flow_steering_init(struct rvu *rvu, int blkaddr)
682 {
683 struct npc_mcam *mcam = &rvu->hw->mcam;
684
685 INIT_LIST_HEAD(&mcam->mcam_rules);
686
687 return npc_scan_verify_kex(rvu, blkaddr);
688 }
689
npc_check_unsupported_flows(struct rvu * rvu,u64 features,u8 intf)690 static int npc_check_unsupported_flows(struct rvu *rvu, u64 features, u8 intf)
691 {
692 struct npc_mcam *mcam = &rvu->hw->mcam;
693 u64 *mcam_features = &mcam->rx_features;
694 u64 unsupported;
695 u8 bit;
696
697 if (is_npc_intf_tx(intf))
698 mcam_features = &mcam->tx_features;
699
700 unsupported = (*mcam_features ^ features) & ~(*mcam_features);
701 if (unsupported) {
702 dev_warn(rvu->dev, "Unsupported flow(s):\n");
703 for_each_set_bit(bit, (unsigned long *)&unsupported, 64)
704 dev_warn(rvu->dev, "%s ", npc_get_field_name(bit));
705 return -EOPNOTSUPP;
706 }
707
708 return 0;
709 }
710
711 /* npc_update_entry - Based on the masks generated during
712 * the key scanning, updates the given entry with value and
713 * masks for the field of interest. Maximum 16 bytes of a packet
714 * header can be extracted by HW hence lo and hi are sufficient.
715 * When field bytes are less than or equal to 8 then hi should be
716 * 0 for value and mask.
717 *
718 * If exact match of value is required then mask should be all 1's.
719 * If any bits in mask are 0 then corresponding bits in value are
720 * dont care.
721 */
npc_update_entry(struct rvu * rvu,enum key_fields type,struct mcam_entry * entry,u64 val_lo,u64 val_hi,u64 mask_lo,u64 mask_hi,u8 intf)722 void npc_update_entry(struct rvu *rvu, enum key_fields type,
723 struct mcam_entry *entry, u64 val_lo,
724 u64 val_hi, u64 mask_lo, u64 mask_hi, u8 intf)
725 {
726 struct npc_mcam *mcam = &rvu->hw->mcam;
727 struct mcam_entry dummy = { {0} };
728 struct npc_key_field *field;
729 u64 kw1, kw2, kw3;
730 u8 shift;
731 int i;
732
733 field = &mcam->rx_key_fields[type];
734 if (is_npc_intf_tx(intf))
735 field = &mcam->tx_key_fields[type];
736
737 if (!field->nr_kws)
738 return;
739
740 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
741 if (!field->kw_mask[i])
742 continue;
743 /* place key value in kw[x] */
744 shift = __ffs64(field->kw_mask[i]);
745 /* update entry value */
746 kw1 = (val_lo << shift) & field->kw_mask[i];
747 dummy.kw[i] = kw1;
748 /* update entry mask */
749 kw1 = (mask_lo << shift) & field->kw_mask[i];
750 dummy.kw_mask[i] = kw1;
751
752 if (field->nr_kws == 1)
753 break;
754 /* place remaining bits of key value in kw[x + 1] */
755 if (field->nr_kws == 2) {
756 /* update entry value */
757 kw2 = shift ? val_lo >> (64 - shift) : 0;
758 kw2 |= (val_hi << shift);
759 kw2 &= field->kw_mask[i + 1];
760 dummy.kw[i + 1] = kw2;
761 /* update entry mask */
762 kw2 = shift ? mask_lo >> (64 - shift) : 0;
763 kw2 |= (mask_hi << shift);
764 kw2 &= field->kw_mask[i + 1];
765 dummy.kw_mask[i + 1] = kw2;
766 break;
767 }
768 /* place remaining bits of key value in kw[x + 1], kw[x + 2] */
769 if (field->nr_kws == 3) {
770 /* update entry value */
771 kw2 = shift ? val_lo >> (64 - shift) : 0;
772 kw2 |= (val_hi << shift);
773 kw2 &= field->kw_mask[i + 1];
774 kw3 = shift ? val_hi >> (64 - shift) : 0;
775 kw3 &= field->kw_mask[i + 2];
776 dummy.kw[i + 1] = kw2;
777 dummy.kw[i + 2] = kw3;
778 /* update entry mask */
779 kw2 = shift ? mask_lo >> (64 - shift) : 0;
780 kw2 |= (mask_hi << shift);
781 kw2 &= field->kw_mask[i + 1];
782 kw3 = shift ? mask_hi >> (64 - shift) : 0;
783 kw3 &= field->kw_mask[i + 2];
784 dummy.kw_mask[i + 1] = kw2;
785 dummy.kw_mask[i + 2] = kw3;
786 break;
787 }
788 }
789 /* dummy is ready with values and masks for given key
790 * field now clear and update input entry with those
791 */
792 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) {
793 if (!field->kw_mask[i])
794 continue;
795 entry->kw[i] &= ~field->kw_mask[i];
796 entry->kw_mask[i] &= ~field->kw_mask[i];
797
798 entry->kw[i] |= dummy.kw[i];
799 entry->kw_mask[i] |= dummy.kw_mask[i];
800 }
801 }
802
npc_update_ipv6_flow(struct rvu * rvu,struct mcam_entry * entry,u64 features,struct flow_msg * pkt,struct flow_msg * mask,struct rvu_npc_mcam_rule * output,u8 intf)803 static void npc_update_ipv6_flow(struct rvu *rvu, struct mcam_entry *entry,
804 u64 features, struct flow_msg *pkt,
805 struct flow_msg *mask,
806 struct rvu_npc_mcam_rule *output, u8 intf)
807 {
808 u32 src_ip[IPV6_WORDS], src_ip_mask[IPV6_WORDS];
809 u32 dst_ip[IPV6_WORDS], dst_ip_mask[IPV6_WORDS];
810 struct flow_msg *opkt = &output->packet;
811 struct flow_msg *omask = &output->mask;
812 u64 mask_lo, mask_hi;
813 u64 val_lo, val_hi;
814
815 /* For an ipv6 address fe80::2c68:63ff:fe5e:2d0a the packet
816 * values to be programmed in MCAM should as below:
817 * val_high: 0xfe80000000000000
818 * val_low: 0x2c6863fffe5e2d0a
819 */
820 if (features & BIT_ULL(NPC_SIP_IPV6)) {
821 be32_to_cpu_array(src_ip_mask, mask->ip6src, IPV6_WORDS);
822 be32_to_cpu_array(src_ip, pkt->ip6src, IPV6_WORDS);
823
824 mask_hi = (u64)src_ip_mask[0] << 32 | src_ip_mask[1];
825 mask_lo = (u64)src_ip_mask[2] << 32 | src_ip_mask[3];
826 val_hi = (u64)src_ip[0] << 32 | src_ip[1];
827 val_lo = (u64)src_ip[2] << 32 | src_ip[3];
828
829 npc_update_entry(rvu, NPC_SIP_IPV6, entry, val_lo, val_hi,
830 mask_lo, mask_hi, intf);
831 memcpy(opkt->ip6src, pkt->ip6src, sizeof(opkt->ip6src));
832 memcpy(omask->ip6src, mask->ip6src, sizeof(omask->ip6src));
833 }
834 if (features & BIT_ULL(NPC_DIP_IPV6)) {
835 be32_to_cpu_array(dst_ip_mask, mask->ip6dst, IPV6_WORDS);
836 be32_to_cpu_array(dst_ip, pkt->ip6dst, IPV6_WORDS);
837
838 mask_hi = (u64)dst_ip_mask[0] << 32 | dst_ip_mask[1];
839 mask_lo = (u64)dst_ip_mask[2] << 32 | dst_ip_mask[3];
840 val_hi = (u64)dst_ip[0] << 32 | dst_ip[1];
841 val_lo = (u64)dst_ip[2] << 32 | dst_ip[3];
842
843 npc_update_entry(rvu, NPC_DIP_IPV6, entry, val_lo, val_hi,
844 mask_lo, mask_hi, intf);
845 memcpy(opkt->ip6dst, pkt->ip6dst, sizeof(opkt->ip6dst));
846 memcpy(omask->ip6dst, mask->ip6dst, sizeof(omask->ip6dst));
847 }
848 }
849
npc_update_vlan_features(struct rvu * rvu,struct mcam_entry * entry,u64 features,u8 intf)850 static void npc_update_vlan_features(struct rvu *rvu, struct mcam_entry *entry,
851 u64 features, u8 intf)
852 {
853 bool ctag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_CTAG));
854 bool stag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_STAG));
855 bool vid = !!(features & BIT_ULL(NPC_OUTER_VID));
856
857 /* If only VLAN id is given then always match outer VLAN id */
858 if (vid && !ctag && !stag) {
859 npc_update_entry(rvu, NPC_LB, entry,
860 NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG, 0,
861 NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG, 0, intf);
862 return;
863 }
864 if (ctag)
865 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_CTAG, 0,
866 ~0ULL, 0, intf);
867 if (stag)
868 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_STAG_QINQ, 0,
869 ~0ULL, 0, intf);
870 }
871
npc_update_flow(struct rvu * rvu,struct mcam_entry * entry,u64 features,struct flow_msg * pkt,struct flow_msg * mask,struct rvu_npc_mcam_rule * output,u8 intf,int blkaddr)872 static void npc_update_flow(struct rvu *rvu, struct mcam_entry *entry,
873 u64 features, struct flow_msg *pkt,
874 struct flow_msg *mask,
875 struct rvu_npc_mcam_rule *output, u8 intf,
876 int blkaddr)
877 {
878 u64 dmac_mask = ether_addr_to_u64(mask->dmac);
879 u64 smac_mask = ether_addr_to_u64(mask->smac);
880 u64 dmac_val = ether_addr_to_u64(pkt->dmac);
881 u64 smac_val = ether_addr_to_u64(pkt->smac);
882 struct flow_msg *opkt = &output->packet;
883 struct flow_msg *omask = &output->mask;
884
885 if (!features)
886 return;
887
888 /* For tcp/udp/sctp LTYPE should be present in entry */
889 if (features & BIT_ULL(NPC_IPPROTO_TCP))
890 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_TCP,
891 0, ~0ULL, 0, intf);
892 if (features & BIT_ULL(NPC_IPPROTO_UDP))
893 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_UDP,
894 0, ~0ULL, 0, intf);
895 if (features & BIT_ULL(NPC_IPPROTO_SCTP))
896 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_SCTP,
897 0, ~0ULL, 0, intf);
898 if (features & BIT_ULL(NPC_IPPROTO_ICMP))
899 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP,
900 0, ~0ULL, 0, intf);
901 if (features & BIT_ULL(NPC_IPPROTO_ICMP6))
902 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP6,
903 0, ~0ULL, 0, intf);
904
905 /* For AH, LTYPE should be present in entry */
906 if (features & BIT_ULL(NPC_IPPROTO_AH))
907 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_AH,
908 0, ~0ULL, 0, intf);
909 /* For ESP, LTYPE should be present in entry */
910 if (features & BIT_ULL(NPC_IPPROTO_ESP))
911 npc_update_entry(rvu, NPC_LE, entry, NPC_LT_LE_ESP,
912 0, ~0ULL, 0, intf);
913
914 if (features & BIT_ULL(NPC_LXMB)) {
915 output->lxmb = is_broadcast_ether_addr(pkt->dmac) ? 2 : 1;
916 npc_update_entry(rvu, NPC_LXMB, entry, output->lxmb, 0,
917 output->lxmb, 0, intf);
918 }
919 #define NPC_WRITE_FLOW(field, member, val_lo, val_hi, mask_lo, mask_hi) \
920 do { \
921 if (features & BIT_ULL((field))) { \
922 npc_update_entry(rvu, (field), entry, (val_lo), (val_hi), \
923 (mask_lo), (mask_hi), intf); \
924 memcpy(&opkt->member, &pkt->member, sizeof(pkt->member)); \
925 memcpy(&omask->member, &mask->member, sizeof(mask->member)); \
926 } \
927 } while (0)
928
929 NPC_WRITE_FLOW(NPC_DMAC, dmac, dmac_val, 0, dmac_mask, 0);
930
931 NPC_WRITE_FLOW(NPC_SMAC, smac, smac_val, 0, smac_mask, 0);
932 NPC_WRITE_FLOW(NPC_ETYPE, etype, ntohs(pkt->etype), 0,
933 ntohs(mask->etype), 0);
934 NPC_WRITE_FLOW(NPC_TOS, tos, pkt->tos, 0, mask->tos, 0);
935 NPC_WRITE_FLOW(NPC_IPFRAG_IPV4, ip_flag, pkt->ip_flag, 0,
936 mask->ip_flag, 0);
937 NPC_WRITE_FLOW(NPC_SIP_IPV4, ip4src, ntohl(pkt->ip4src), 0,
938 ntohl(mask->ip4src), 0);
939 NPC_WRITE_FLOW(NPC_DIP_IPV4, ip4dst, ntohl(pkt->ip4dst), 0,
940 ntohl(mask->ip4dst), 0);
941 NPC_WRITE_FLOW(NPC_SPORT_TCP, sport, ntohs(pkt->sport), 0,
942 ntohs(mask->sport), 0);
943 NPC_WRITE_FLOW(NPC_SPORT_UDP, sport, ntohs(pkt->sport), 0,
944 ntohs(mask->sport), 0);
945 NPC_WRITE_FLOW(NPC_DPORT_TCP, dport, ntohs(pkt->dport), 0,
946 ntohs(mask->dport), 0);
947 NPC_WRITE_FLOW(NPC_DPORT_UDP, dport, ntohs(pkt->dport), 0,
948 ntohs(mask->dport), 0);
949 NPC_WRITE_FLOW(NPC_SPORT_SCTP, sport, ntohs(pkt->sport), 0,
950 ntohs(mask->sport), 0);
951 NPC_WRITE_FLOW(NPC_DPORT_SCTP, dport, ntohs(pkt->dport), 0,
952 ntohs(mask->dport), 0);
953
954 NPC_WRITE_FLOW(NPC_IPSEC_SPI, spi, ntohl(pkt->spi), 0,
955 ntohl(mask->spi), 0);
956
957 NPC_WRITE_FLOW(NPC_OUTER_VID, vlan_tci, ntohs(pkt->vlan_tci), 0,
958 ntohs(mask->vlan_tci), 0);
959 NPC_WRITE_FLOW(NPC_INNER_VID, vlan_itci, ntohs(pkt->vlan_itci), 0,
960 ntohs(mask->vlan_itci), 0);
961
962 NPC_WRITE_FLOW(NPC_IPFRAG_IPV6, next_header, pkt->next_header, 0,
963 mask->next_header, 0);
964 npc_update_ipv6_flow(rvu, entry, features, pkt, mask, output, intf);
965 npc_update_vlan_features(rvu, entry, features, intf);
966
967 npc_update_field_hash(rvu, intf, entry, blkaddr, features,
968 pkt, mask, opkt, omask);
969 }
970
rvu_mcam_find_rule(struct npc_mcam * mcam,u16 entry)971 static struct rvu_npc_mcam_rule *rvu_mcam_find_rule(struct npc_mcam *mcam, u16 entry)
972 {
973 struct rvu_npc_mcam_rule *iter;
974
975 mutex_lock(&mcam->lock);
976 list_for_each_entry(iter, &mcam->mcam_rules, list) {
977 if (iter->entry == entry) {
978 mutex_unlock(&mcam->lock);
979 return iter;
980 }
981 }
982 mutex_unlock(&mcam->lock);
983
984 return NULL;
985 }
986
rvu_mcam_add_rule(struct npc_mcam * mcam,struct rvu_npc_mcam_rule * rule)987 static void rvu_mcam_add_rule(struct npc_mcam *mcam,
988 struct rvu_npc_mcam_rule *rule)
989 {
990 struct list_head *head = &mcam->mcam_rules;
991 struct rvu_npc_mcam_rule *iter;
992
993 mutex_lock(&mcam->lock);
994 list_for_each_entry(iter, &mcam->mcam_rules, list) {
995 if (iter->entry > rule->entry)
996 break;
997 head = &iter->list;
998 }
999
1000 list_add(&rule->list, head);
1001 mutex_unlock(&mcam->lock);
1002 }
1003
rvu_mcam_remove_counter_from_rule(struct rvu * rvu,u16 pcifunc,struct rvu_npc_mcam_rule * rule)1004 static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc,
1005 struct rvu_npc_mcam_rule *rule)
1006 {
1007 struct npc_mcam_oper_counter_req free_req = { 0 };
1008 struct msg_rsp free_rsp;
1009
1010 if (!rule->has_cntr)
1011 return;
1012
1013 free_req.hdr.pcifunc = pcifunc;
1014 free_req.cntr = rule->cntr;
1015
1016 rvu_mbox_handler_npc_mcam_free_counter(rvu, &free_req, &free_rsp);
1017 rule->has_cntr = false;
1018 }
1019
rvu_mcam_add_counter_to_rule(struct rvu * rvu,u16 pcifunc,struct rvu_npc_mcam_rule * rule,struct npc_install_flow_rsp * rsp)1020 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc,
1021 struct rvu_npc_mcam_rule *rule,
1022 struct npc_install_flow_rsp *rsp)
1023 {
1024 struct npc_mcam_alloc_counter_req cntr_req = { 0 };
1025 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 };
1026 int err;
1027
1028 cntr_req.hdr.pcifunc = pcifunc;
1029 cntr_req.contig = true;
1030 cntr_req.count = 1;
1031
1032 /* we try to allocate a counter to track the stats of this
1033 * rule. If counter could not be allocated then proceed
1034 * without counter because counters are limited than entries.
1035 */
1036 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req,
1037 &cntr_rsp);
1038 if (!err && cntr_rsp.count) {
1039 rule->cntr = cntr_rsp.cntr;
1040 rule->has_cntr = true;
1041 rsp->counter = rule->cntr;
1042 } else {
1043 rsp->counter = err;
1044 }
1045 }
1046
npc_update_rx_entry(struct rvu * rvu,struct rvu_pfvf * pfvf,struct mcam_entry * entry,struct npc_install_flow_req * req,u16 target,bool pf_set_vfs_mac)1047 static void npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,
1048 struct mcam_entry *entry,
1049 struct npc_install_flow_req *req,
1050 u16 target, bool pf_set_vfs_mac)
1051 {
1052 struct rvu_switch *rswitch = &rvu->rswitch;
1053 struct nix_rx_action action;
1054
1055 if (rswitch->mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && pf_set_vfs_mac)
1056 req->chan_mask = 0x0; /* Do not care channel */
1057
1058 npc_update_entry(rvu, NPC_CHAN, entry, req->channel, 0, req->chan_mask,
1059 0, NIX_INTF_RX);
1060
1061 *(u64 *)&action = 0x00;
1062 action.pf_func = target;
1063 action.op = req->op;
1064 action.index = req->index;
1065 action.match_id = req->match_id;
1066 action.flow_key_alg = req->flow_key_alg;
1067
1068 if (req->op == NIX_RX_ACTION_DEFAULT) {
1069 if (pfvf->def_ucast_rule) {
1070 action = pfvf->def_ucast_rule->rx_action;
1071 } else {
1072 /* For profiles which do not extract DMAC, the default
1073 * unicast entry is unused. Hence modify action for the
1074 * requests which use same action as default unicast
1075 * entry
1076 */
1077 *(u64 *)&action = 0;
1078 action.pf_func = target;
1079 action.op = NIX_RX_ACTIONOP_UCAST;
1080 }
1081 }
1082
1083 entry->action = *(u64 *)&action;
1084
1085 /* VTAG0 starts at 0th byte of LID_B.
1086 * VTAG1 starts at 4th byte of LID_B.
1087 */
1088 entry->vtag_action = FIELD_PREP(RX_VTAG0_VALID_BIT, req->vtag0_valid) |
1089 FIELD_PREP(RX_VTAG0_TYPE_MASK, req->vtag0_type) |
1090 FIELD_PREP(RX_VTAG0_LID_MASK, NPC_LID_LB) |
1091 FIELD_PREP(RX_VTAG0_RELPTR_MASK, 0) |
1092 FIELD_PREP(RX_VTAG1_VALID_BIT, req->vtag1_valid) |
1093 FIELD_PREP(RX_VTAG1_TYPE_MASK, req->vtag1_type) |
1094 FIELD_PREP(RX_VTAG1_LID_MASK, NPC_LID_LB) |
1095 FIELD_PREP(RX_VTAG1_RELPTR_MASK, 4);
1096 }
1097
npc_update_tx_entry(struct rvu * rvu,struct rvu_pfvf * pfvf,struct mcam_entry * entry,struct npc_install_flow_req * req,u16 target)1098 static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,
1099 struct mcam_entry *entry,
1100 struct npc_install_flow_req *req, u16 target)
1101 {
1102 struct nix_tx_action action;
1103 u64 mask = ~0ULL;
1104
1105 /* If AF is installing then do not care about
1106 * PF_FUNC in Send Descriptor
1107 */
1108 if (is_pffunc_af(req->hdr.pcifunc))
1109 mask = 0;
1110
1111 npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target),
1112 0, mask, 0, NIX_INTF_TX);
1113
1114 *(u64 *)&action = 0x00;
1115 action.op = req->op;
1116 action.index = req->index;
1117 action.match_id = req->match_id;
1118
1119 entry->action = *(u64 *)&action;
1120
1121 /* VTAG0 starts at 0th byte of LID_B.
1122 * VTAG1 starts at 4th byte of LID_B.
1123 */
1124 entry->vtag_action = FIELD_PREP(TX_VTAG0_DEF_MASK, req->vtag0_def) |
1125 FIELD_PREP(TX_VTAG0_OP_MASK, req->vtag0_op) |
1126 FIELD_PREP(TX_VTAG0_LID_MASK, NPC_LID_LA) |
1127 FIELD_PREP(TX_VTAG0_RELPTR_MASK, 20) |
1128 FIELD_PREP(TX_VTAG1_DEF_MASK, req->vtag1_def) |
1129 FIELD_PREP(TX_VTAG1_OP_MASK, req->vtag1_op) |
1130 FIELD_PREP(TX_VTAG1_LID_MASK, NPC_LID_LA) |
1131 FIELD_PREP(TX_VTAG1_RELPTR_MASK, 24);
1132 }
1133
npc_install_flow(struct rvu * rvu,int blkaddr,u16 target,int nixlf,struct rvu_pfvf * pfvf,struct npc_install_flow_req * req,struct npc_install_flow_rsp * rsp,bool enable,bool pf_set_vfs_mac)1134 static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target,
1135 int nixlf, struct rvu_pfvf *pfvf,
1136 struct npc_install_flow_req *req,
1137 struct npc_install_flow_rsp *rsp, bool enable,
1138 bool pf_set_vfs_mac)
1139 {
1140 struct rvu_npc_mcam_rule *def_ucast_rule = pfvf->def_ucast_rule;
1141 u64 features, installed_features, missing_features = 0;
1142 struct npc_mcam_write_entry_req write_req = { 0 };
1143 struct npc_mcam *mcam = &rvu->hw->mcam;
1144 struct rvu_npc_mcam_rule dummy = { 0 };
1145 struct rvu_npc_mcam_rule *rule;
1146 u16 owner = req->hdr.pcifunc;
1147 struct msg_rsp write_rsp;
1148 struct mcam_entry *entry;
1149 bool new = false;
1150 u16 entry_index;
1151 int err;
1152
1153 installed_features = req->features;
1154 features = req->features;
1155 entry = &write_req.entry_data;
1156 entry_index = req->entry;
1157
1158 npc_update_flow(rvu, entry, features, &req->packet, &req->mask, &dummy,
1159 req->intf, blkaddr);
1160
1161 if (is_npc_intf_rx(req->intf))
1162 npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac);
1163 else
1164 npc_update_tx_entry(rvu, pfvf, entry, req, target);
1165
1166 /* Default unicast rules do not exist for TX */
1167 if (is_npc_intf_tx(req->intf))
1168 goto find_rule;
1169
1170 if (req->default_rule) {
1171 entry_index = npc_get_nixlf_mcam_index(mcam, target, nixlf,
1172 NIXLF_UCAST_ENTRY);
1173 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, entry_index);
1174 }
1175
1176 /* update mcam entry with default unicast rule attributes */
1177 if (def_ucast_rule && (req->default_rule && req->append)) {
1178 missing_features = (def_ucast_rule->features ^ features) &
1179 def_ucast_rule->features;
1180 if (missing_features)
1181 npc_update_flow(rvu, entry, missing_features,
1182 &def_ucast_rule->packet,
1183 &def_ucast_rule->mask,
1184 &dummy, req->intf,
1185 blkaddr);
1186 installed_features = req->features | missing_features;
1187 }
1188
1189 find_rule:
1190 rule = rvu_mcam_find_rule(mcam, entry_index);
1191 if (!rule) {
1192 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
1193 if (!rule)
1194 return -ENOMEM;
1195 new = true;
1196 }
1197
1198 /* allocate new counter if rule has no counter */
1199 if (!req->default_rule && req->set_cntr && !rule->has_cntr)
1200 rvu_mcam_add_counter_to_rule(rvu, owner, rule, rsp);
1201
1202 /* if user wants to delete an existing counter for a rule then
1203 * free the counter
1204 */
1205 if (!req->set_cntr && rule->has_cntr)
1206 rvu_mcam_remove_counter_from_rule(rvu, owner, rule);
1207
1208 write_req.hdr.pcifunc = owner;
1209
1210 /* AF owns the default rules so change the owner just to relax
1211 * the checks in rvu_mbox_handler_npc_mcam_write_entry
1212 */
1213 if (req->default_rule)
1214 write_req.hdr.pcifunc = 0;
1215
1216 write_req.entry = entry_index;
1217 write_req.intf = req->intf;
1218 write_req.enable_entry = (u8)enable;
1219 /* if counter is available then clear and use it */
1220 if (req->set_cntr && rule->has_cntr) {
1221 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(rule->cntr), req->cntr_val);
1222 write_req.set_cntr = 1;
1223 write_req.cntr = rule->cntr;
1224 }
1225
1226 /* update rule */
1227 memcpy(&rule->packet, &dummy.packet, sizeof(rule->packet));
1228 memcpy(&rule->mask, &dummy.mask, sizeof(rule->mask));
1229 rule->entry = entry_index;
1230 memcpy(&rule->rx_action, &entry->action, sizeof(struct nix_rx_action));
1231 if (is_npc_intf_tx(req->intf))
1232 memcpy(&rule->tx_action, &entry->action,
1233 sizeof(struct nix_tx_action));
1234 rule->vtag_action = entry->vtag_action;
1235 rule->features = installed_features;
1236 rule->default_rule = req->default_rule;
1237 rule->owner = owner;
1238 rule->enable = enable;
1239 rule->chan_mask = write_req.entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK;
1240 rule->chan = write_req.entry_data.kw[0] & NPC_KEX_CHAN_MASK;
1241 rule->chan &= rule->chan_mask;
1242 rule->lxmb = dummy.lxmb;
1243 if (is_npc_intf_tx(req->intf))
1244 rule->intf = pfvf->nix_tx_intf;
1245 else
1246 rule->intf = pfvf->nix_rx_intf;
1247
1248 if (new)
1249 rvu_mcam_add_rule(mcam, rule);
1250 if (req->default_rule)
1251 pfvf->def_ucast_rule = rule;
1252
1253 /* write to mcam entry registers */
1254 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req,
1255 &write_rsp);
1256 if (err) {
1257 rvu_mcam_remove_counter_from_rule(rvu, owner, rule);
1258 if (new) {
1259 list_del(&rule->list);
1260 kfree(rule);
1261 }
1262 return err;
1263 }
1264
1265 /* VF's MAC address is being changed via PF */
1266 if (pf_set_vfs_mac) {
1267 ether_addr_copy(pfvf->default_mac, req->packet.dmac);
1268 ether_addr_copy(pfvf->mac_addr, req->packet.dmac);
1269 set_bit(PF_SET_VF_MAC, &pfvf->flags);
1270 }
1271
1272 if (test_bit(PF_SET_VF_CFG, &pfvf->flags) &&
1273 req->vtag0_type == NIX_AF_LFX_RX_VTAG_TYPE7)
1274 rule->vfvlan_cfg = true;
1275
1276 if (is_npc_intf_rx(req->intf) && req->match_id &&
1277 (req->op == NIX_RX_ACTIONOP_UCAST || req->op == NIX_RX_ACTIONOP_RSS))
1278 return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc,
1279 req->index, req->match_id);
1280
1281 return 0;
1282 }
1283
rvu_mbox_handler_npc_install_flow(struct rvu * rvu,struct npc_install_flow_req * req,struct npc_install_flow_rsp * rsp)1284 int rvu_mbox_handler_npc_install_flow(struct rvu *rvu,
1285 struct npc_install_flow_req *req,
1286 struct npc_install_flow_rsp *rsp)
1287 {
1288 bool from_vf = !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK);
1289 struct rvu_switch *rswitch = &rvu->rswitch;
1290 int blkaddr, nixlf, err;
1291 struct rvu_pfvf *pfvf;
1292 bool pf_set_vfs_mac = false;
1293 bool enable = true;
1294 u16 target;
1295
1296 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1297 if (blkaddr < 0) {
1298 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
1299 return NPC_MCAM_INVALID_REQ;
1300 }
1301
1302 if (!is_npc_interface_valid(rvu, req->intf))
1303 return NPC_FLOW_INTF_INVALID;
1304
1305 /* If DMAC is not extracted in MKEX, rules installed by AF
1306 * can rely on L2MB bit set by hardware protocol checker for
1307 * broadcast and multicast addresses.
1308 */
1309 if (npc_check_field(rvu, blkaddr, NPC_DMAC, req->intf))
1310 goto process_flow;
1311
1312 if (is_pffunc_af(req->hdr.pcifunc) &&
1313 req->features & BIT_ULL(NPC_DMAC)) {
1314 if (is_unicast_ether_addr(req->packet.dmac)) {
1315 dev_warn(rvu->dev,
1316 "%s: mkex profile does not support ucast flow\n",
1317 __func__);
1318 return NPC_FLOW_NOT_SUPPORTED;
1319 }
1320
1321 if (!npc_is_field_present(rvu, NPC_LXMB, req->intf)) {
1322 dev_warn(rvu->dev,
1323 "%s: mkex profile does not support bcast/mcast flow",
1324 __func__);
1325 return NPC_FLOW_NOT_SUPPORTED;
1326 }
1327
1328 /* Modify feature to use LXMB instead of DMAC */
1329 req->features &= ~BIT_ULL(NPC_DMAC);
1330 req->features |= BIT_ULL(NPC_LXMB);
1331 }
1332
1333 process_flow:
1334 if (from_vf && req->default_rule)
1335 return NPC_FLOW_VF_PERM_DENIED;
1336
1337 /* Each PF/VF info is maintained in struct rvu_pfvf.
1338 * rvu_pfvf for the target PF/VF needs to be retrieved
1339 * hence modify pcifunc accordingly.
1340 */
1341
1342 /* AF installing for a PF/VF */
1343 if (!req->hdr.pcifunc)
1344 target = req->vf;
1345 /* PF installing for its VF */
1346 else if (!from_vf && req->vf) {
1347 target = (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf;
1348 pf_set_vfs_mac = req->default_rule &&
1349 (req->features & BIT_ULL(NPC_DMAC));
1350 }
1351 /* msg received from PF/VF */
1352 else
1353 target = req->hdr.pcifunc;
1354
1355 /* ignore chan_mask in case pf func is not AF, revisit later */
1356 if (!is_pffunc_af(req->hdr.pcifunc))
1357 req->chan_mask = 0xFFF;
1358
1359 err = npc_check_unsupported_flows(rvu, req->features, req->intf);
1360 if (err)
1361 return NPC_FLOW_NOT_SUPPORTED;
1362
1363 pfvf = rvu_get_pfvf(rvu, target);
1364
1365 /* PF installing for its VF */
1366 if (req->hdr.pcifunc && !from_vf && req->vf)
1367 set_bit(PF_SET_VF_CFG, &pfvf->flags);
1368
1369 /* update req destination mac addr */
1370 if ((req->features & BIT_ULL(NPC_DMAC)) && is_npc_intf_rx(req->intf) &&
1371 is_zero_ether_addr(req->packet.dmac)) {
1372 ether_addr_copy(req->packet.dmac, pfvf->mac_addr);
1373 eth_broadcast_addr((u8 *)&req->mask.dmac);
1374 }
1375
1376 /* Proceed if NIXLF is attached or not for TX rules */
1377 err = nix_get_nixlf(rvu, target, &nixlf, NULL);
1378 if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac)
1379 return NPC_FLOW_NO_NIXLF;
1380
1381 /* don't enable rule when nixlf not attached or initialized */
1382 if (!(is_nixlf_attached(rvu, target) &&
1383 test_bit(NIXLF_INITIALIZED, &pfvf->flags)))
1384 enable = false;
1385
1386 /* Packets reaching NPC in Tx path implies that a
1387 * NIXLF is properly setup and transmitting.
1388 * Hence rules can be enabled for Tx.
1389 */
1390 if (is_npc_intf_tx(req->intf))
1391 enable = true;
1392
1393 /* Do not allow requests from uninitialized VFs */
1394 if (from_vf && !enable)
1395 return NPC_FLOW_VF_NOT_INIT;
1396
1397 /* PF sets VF mac & VF NIXLF is not attached, update the mac addr */
1398 if (pf_set_vfs_mac && !enable) {
1399 ether_addr_copy(pfvf->default_mac, req->packet.dmac);
1400 ether_addr_copy(pfvf->mac_addr, req->packet.dmac);
1401 set_bit(PF_SET_VF_MAC, &pfvf->flags);
1402 return 0;
1403 }
1404
1405 mutex_lock(&rswitch->switch_lock);
1406 err = npc_install_flow(rvu, blkaddr, target, nixlf, pfvf,
1407 req, rsp, enable, pf_set_vfs_mac);
1408 mutex_unlock(&rswitch->switch_lock);
1409
1410 return err;
1411 }
1412
npc_delete_flow(struct rvu * rvu,struct rvu_npc_mcam_rule * rule,u16 pcifunc)1413 static int npc_delete_flow(struct rvu *rvu, struct rvu_npc_mcam_rule *rule,
1414 u16 pcifunc)
1415 {
1416 struct npc_mcam_ena_dis_entry_req dis_req = { 0 };
1417 struct msg_rsp dis_rsp;
1418
1419 if (rule->default_rule)
1420 return 0;
1421
1422 if (rule->has_cntr)
1423 rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule);
1424
1425 dis_req.hdr.pcifunc = pcifunc;
1426 dis_req.entry = rule->entry;
1427
1428 list_del(&rule->list);
1429 kfree(rule);
1430
1431 return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp);
1432 }
1433
rvu_mbox_handler_npc_delete_flow(struct rvu * rvu,struct npc_delete_flow_req * req,struct npc_delete_flow_rsp * rsp)1434 int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu,
1435 struct npc_delete_flow_req *req,
1436 struct npc_delete_flow_rsp *rsp)
1437 {
1438 struct npc_mcam *mcam = &rvu->hw->mcam;
1439 struct rvu_npc_mcam_rule *iter, *tmp;
1440 u16 pcifunc = req->hdr.pcifunc;
1441 struct list_head del_list;
1442 int blkaddr;
1443
1444 INIT_LIST_HEAD(&del_list);
1445
1446 mutex_lock(&mcam->lock);
1447 list_for_each_entry_safe(iter, tmp, &mcam->mcam_rules, list) {
1448 if (iter->owner == pcifunc) {
1449 /* All rules */
1450 if (req->all) {
1451 list_move_tail(&iter->list, &del_list);
1452 /* Range of rules */
1453 } else if (req->end && iter->entry >= req->start &&
1454 iter->entry <= req->end) {
1455 list_move_tail(&iter->list, &del_list);
1456 /* single rule */
1457 } else if (req->entry == iter->entry) {
1458 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1459 if (blkaddr)
1460 rsp->cntr_val = rvu_read64(rvu, blkaddr,
1461 NPC_AF_MATCH_STATX(iter->cntr));
1462 list_move_tail(&iter->list, &del_list);
1463 break;
1464 }
1465 }
1466 }
1467 mutex_unlock(&mcam->lock);
1468
1469 list_for_each_entry_safe(iter, tmp, &del_list, list) {
1470 u16 entry = iter->entry;
1471
1472 /* clear the mcam entry target pcifunc */
1473 mcam->entry2target_pffunc[entry] = 0x0;
1474 if (npc_delete_flow(rvu, iter, pcifunc))
1475 dev_err(rvu->dev, "rule deletion failed for entry:%u",
1476 entry);
1477 }
1478
1479 return 0;
1480 }
1481
npc_update_dmac_value(struct rvu * rvu,int npcblkaddr,struct rvu_npc_mcam_rule * rule,struct rvu_pfvf * pfvf)1482 static int npc_update_dmac_value(struct rvu *rvu, int npcblkaddr,
1483 struct rvu_npc_mcam_rule *rule,
1484 struct rvu_pfvf *pfvf)
1485 {
1486 struct npc_mcam_write_entry_req write_req = { 0 };
1487 struct mcam_entry *entry = &write_req.entry_data;
1488 struct npc_mcam *mcam = &rvu->hw->mcam;
1489 struct msg_rsp rsp;
1490 u8 intf, enable;
1491 int err;
1492
1493 ether_addr_copy(rule->packet.dmac, pfvf->mac_addr);
1494
1495 npc_read_mcam_entry(rvu, mcam, npcblkaddr, rule->entry,
1496 entry, &intf, &enable);
1497
1498 npc_update_entry(rvu, NPC_DMAC, entry,
1499 ether_addr_to_u64(pfvf->mac_addr), 0,
1500 0xffffffffffffull, 0, intf);
1501
1502 write_req.hdr.pcifunc = rule->owner;
1503 write_req.entry = rule->entry;
1504 write_req.intf = pfvf->nix_rx_intf;
1505
1506 mutex_unlock(&mcam->lock);
1507 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, &rsp);
1508 mutex_lock(&mcam->lock);
1509
1510 return err;
1511 }
1512
npc_mcam_enable_flows(struct rvu * rvu,u16 target)1513 void npc_mcam_enable_flows(struct rvu *rvu, u16 target)
1514 {
1515 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, target);
1516 struct rvu_npc_mcam_rule *def_ucast_rule;
1517 struct npc_mcam *mcam = &rvu->hw->mcam;
1518 struct rvu_npc_mcam_rule *rule;
1519 int blkaddr, bank, index;
1520 u64 def_action;
1521
1522 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1523 if (blkaddr < 0)
1524 return;
1525
1526 def_ucast_rule = pfvf->def_ucast_rule;
1527
1528 mutex_lock(&mcam->lock);
1529 list_for_each_entry(rule, &mcam->mcam_rules, list) {
1530 if (is_npc_intf_rx(rule->intf) &&
1531 rule->rx_action.pf_func == target && !rule->enable) {
1532 if (rule->default_rule) {
1533 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1534 rule->entry, true);
1535 rule->enable = true;
1536 continue;
1537 }
1538
1539 if (rule->vfvlan_cfg)
1540 npc_update_dmac_value(rvu, blkaddr, rule, pfvf);
1541
1542 if (rule->rx_action.op == NIX_RX_ACTION_DEFAULT) {
1543 if (!def_ucast_rule)
1544 continue;
1545 /* Use default unicast entry action */
1546 rule->rx_action = def_ucast_rule->rx_action;
1547 def_action = *(u64 *)&def_ucast_rule->rx_action;
1548 bank = npc_get_bank(mcam, rule->entry);
1549 rvu_write64(rvu, blkaddr,
1550 NPC_AF_MCAMEX_BANKX_ACTION
1551 (rule->entry, bank), def_action);
1552 }
1553
1554 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1555 rule->entry, true);
1556 rule->enable = true;
1557 }
1558 }
1559
1560 /* Enable MCAM entries installed by PF with target as VF pcifunc */
1561 for (index = 0; index < mcam->bmap_entries; index++) {
1562 if (mcam->entry2target_pffunc[index] == target)
1563 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1564 index, true);
1565 }
1566 mutex_unlock(&mcam->lock);
1567 }
1568
npc_mcam_disable_flows(struct rvu * rvu,u16 target)1569 void npc_mcam_disable_flows(struct rvu *rvu, u16 target)
1570 {
1571 struct npc_mcam *mcam = &rvu->hw->mcam;
1572 int blkaddr, index;
1573
1574 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1575 if (blkaddr < 0)
1576 return;
1577
1578 mutex_lock(&mcam->lock);
1579 /* Disable MCAM entries installed by PF with target as VF pcifunc */
1580 for (index = 0; index < mcam->bmap_entries; index++) {
1581 if (mcam->entry2target_pffunc[index] == target)
1582 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1583 index, false);
1584 }
1585 mutex_unlock(&mcam->lock);
1586 }
1587
1588 /* single drop on non hit rule starting from 0th index. This an extension
1589 * to RPM mac filter to support more rules.
1590 */
npc_install_mcam_drop_rule(struct rvu * rvu,int mcam_idx,u16 * counter_idx,u64 chan_val,u64 chan_mask,u64 exact_val,u64 exact_mask,u64 bcast_mcast_val,u64 bcast_mcast_mask)1591 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
1592 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
1593 u64 bcast_mcast_val, u64 bcast_mcast_mask)
1594 {
1595 struct npc_mcam_alloc_counter_req cntr_req = { 0 };
1596 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 };
1597 struct npc_mcam_write_entry_req req = { 0 };
1598 struct npc_mcam *mcam = &rvu->hw->mcam;
1599 struct rvu_npc_mcam_rule *rule;
1600 struct msg_rsp rsp;
1601 bool enabled;
1602 int blkaddr;
1603 int err;
1604
1605 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1606 if (blkaddr < 0) {
1607 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
1608 return -ENODEV;
1609 }
1610
1611 /* Bail out if no exact match support */
1612 if (!rvu_npc_exact_has_match_table(rvu)) {
1613 dev_info(rvu->dev, "%s: No support for exact match feature\n", __func__);
1614 return -EINVAL;
1615 }
1616
1617 /* If 0th entry is already used, return err */
1618 enabled = is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_idx);
1619 if (enabled) {
1620 dev_err(rvu->dev, "%s: failed to add single drop on non hit rule at %d th index\n",
1621 __func__, mcam_idx);
1622 return -EINVAL;
1623 }
1624
1625 /* Add this entry to mcam rules list */
1626 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
1627 if (!rule)
1628 return -ENOMEM;
1629
1630 /* Disable rule by default. Enable rule when first dmac filter is
1631 * installed
1632 */
1633 rule->enable = false;
1634 rule->chan = chan_val;
1635 rule->chan_mask = chan_mask;
1636 rule->entry = mcam_idx;
1637 rvu_mcam_add_rule(mcam, rule);
1638
1639 /* Reserve slot 0 */
1640 npc_mcam_rsrcs_reserve(rvu, blkaddr, mcam_idx);
1641
1642 /* Allocate counter for this single drop on non hit rule */
1643 cntr_req.hdr.pcifunc = 0; /* AF request */
1644 cntr_req.contig = true;
1645 cntr_req.count = 1;
1646 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
1647 if (err) {
1648 dev_err(rvu->dev, "%s: Err to allocate cntr for drop rule (err=%d)\n",
1649 __func__, err);
1650 return -EFAULT;
1651 }
1652 *counter_idx = cntr_rsp.cntr;
1653
1654 /* Fill in fields for this mcam entry */
1655 npc_update_entry(rvu, NPC_EXACT_RESULT, &req.entry_data, exact_val, 0,
1656 exact_mask, 0, NIX_INTF_RX);
1657 npc_update_entry(rvu, NPC_CHAN, &req.entry_data, chan_val, 0,
1658 chan_mask, 0, NIX_INTF_RX);
1659 npc_update_entry(rvu, NPC_LXMB, &req.entry_data, bcast_mcast_val, 0,
1660 bcast_mcast_mask, 0, NIX_INTF_RX);
1661
1662 req.intf = NIX_INTF_RX;
1663 req.set_cntr = true;
1664 req.cntr = cntr_rsp.cntr;
1665 req.entry = mcam_idx;
1666
1667 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &req, &rsp);
1668 if (err) {
1669 dev_err(rvu->dev, "%s: Installation of single drop on non hit rule at %d failed\n",
1670 __func__, mcam_idx);
1671 return err;
1672 }
1673
1674 dev_err(rvu->dev, "%s: Installed single drop on non hit rule at %d, cntr=%d\n",
1675 __func__, mcam_idx, req.cntr);
1676
1677 /* disable entry at Bank 0, index 0 */
1678 npc_enable_mcam_entry(rvu, mcam, blkaddr, mcam_idx, false);
1679
1680 return 0;
1681 }
1682
rvu_mbox_handler_npc_get_field_status(struct rvu * rvu,struct npc_get_field_status_req * req,struct npc_get_field_status_rsp * rsp)1683 int rvu_mbox_handler_npc_get_field_status(struct rvu *rvu,
1684 struct npc_get_field_status_req *req,
1685 struct npc_get_field_status_rsp *rsp)
1686 {
1687 int blkaddr;
1688
1689 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1690 if (blkaddr < 0)
1691 return NPC_MCAM_INVALID_REQ;
1692
1693 if (!is_npc_interface_valid(rvu, req->intf))
1694 return NPC_FLOW_INTF_INVALID;
1695
1696 if (npc_check_field(rvu, blkaddr, req->field, req->intf))
1697 rsp->enable = 1;
1698
1699 return 0;
1700 }
1701