xref: /openbmc/linux/drivers/gpu/drm/virtio/virtgpu_plane.c (revision 360823a09426347ea8f232b0b0b5156d0aed0302)
1 /*
2  * Copyright (C) 2015 Red Hat, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_damage_helper.h>
28 #include <drm/drm_fourcc.h>
29 
30 #include "virtgpu_drv.h"
31 
32 static const uint32_t virtio_gpu_formats[] = {
33 	DRM_FORMAT_HOST_XRGB8888,
34 };
35 
36 static const uint32_t virtio_gpu_cursor_formats[] = {
37 	DRM_FORMAT_HOST_ARGB8888,
38 };
39 
virtio_gpu_translate_format(uint32_t drm_fourcc)40 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
41 {
42 	uint32_t format;
43 
44 	switch (drm_fourcc) {
45 	case DRM_FORMAT_XRGB8888:
46 		format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
47 		break;
48 	case DRM_FORMAT_ARGB8888:
49 		format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
50 		break;
51 	case DRM_FORMAT_BGRX8888:
52 		format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
53 		break;
54 	case DRM_FORMAT_BGRA8888:
55 		format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
56 		break;
57 	default:
58 		/*
59 		 * This should not happen, we handle everything listed
60 		 * in virtio_gpu_formats[].
61 		 */
62 		format = 0;
63 		break;
64 	}
65 	WARN_ON(format == 0);
66 	return format;
67 }
68 
69 static struct
virtio_gpu_plane_duplicate_state(struct drm_plane * plane)70 drm_plane_state *virtio_gpu_plane_duplicate_state(struct drm_plane *plane)
71 {
72 	struct virtio_gpu_plane_state *new;
73 
74 	if (WARN_ON(!plane->state))
75 		return NULL;
76 
77 	new = kzalloc(sizeof(*new), GFP_KERNEL);
78 	if (!new)
79 		return NULL;
80 
81 	__drm_atomic_helper_plane_duplicate_state(plane, &new->base);
82 
83 	return &new->base;
84 }
85 
86 static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
87 	.update_plane		= drm_atomic_helper_update_plane,
88 	.disable_plane		= drm_atomic_helper_disable_plane,
89 	.reset			= drm_atomic_helper_plane_reset,
90 	.atomic_duplicate_state = virtio_gpu_plane_duplicate_state,
91 	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
92 };
93 
virtio_gpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)94 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
95 					 struct drm_atomic_state *state)
96 {
97 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
98 										 plane);
99 	struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
100 										 plane);
101 	bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
102 	struct drm_crtc_state *crtc_state;
103 	int ret;
104 
105 	if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
106 		return 0;
107 
108 	/*
109 	 * Ignore damage clips if the framebuffer attached to the plane's state
110 	 * has changed since the last plane update (page-flip). In this case, a
111 	 * full plane update should happen because uploads are done per-buffer.
112 	 */
113 	if (old_plane_state->fb != new_plane_state->fb)
114 		new_plane_state->ignore_damage_clips = true;
115 
116 	crtc_state = drm_atomic_get_crtc_state(state,
117 					       new_plane_state->crtc);
118 	if (IS_ERR(crtc_state))
119                 return PTR_ERR(crtc_state);
120 
121 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
122 						  DRM_PLANE_NO_SCALING,
123 						  DRM_PLANE_NO_SCALING,
124 						  is_cursor, true);
125 	return ret;
126 }
127 
virtio_gpu_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)128 static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
129 				      struct drm_plane_state *state,
130 				      struct drm_rect *rect)
131 {
132 	struct virtio_gpu_object *bo =
133 		gem_to_virtio_gpu_obj(state->fb->obj[0]);
134 	struct virtio_gpu_object_array *objs;
135 	uint32_t w = rect->x2 - rect->x1;
136 	uint32_t h = rect->y2 - rect->y1;
137 	uint32_t x = rect->x1;
138 	uint32_t y = rect->y1;
139 	uint32_t off = x * state->fb->format->cpp[0] +
140 		y * state->fb->pitches[0];
141 
142 	objs = virtio_gpu_array_alloc(1);
143 	if (!objs)
144 		return;
145 	virtio_gpu_array_add_obj(objs, &bo->base.base);
146 
147 	virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
148 					   objs, NULL);
149 }
150 
virtio_gpu_resource_flush(struct drm_plane * plane,uint32_t x,uint32_t y,uint32_t width,uint32_t height)151 static void virtio_gpu_resource_flush(struct drm_plane *plane,
152 				      uint32_t x, uint32_t y,
153 				      uint32_t width, uint32_t height)
154 {
155 	struct drm_device *dev = plane->dev;
156 	struct virtio_gpu_device *vgdev = dev->dev_private;
157 	struct virtio_gpu_framebuffer *vgfb;
158 	struct virtio_gpu_plane_state *vgplane_st;
159 	struct virtio_gpu_object *bo;
160 
161 	vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
162 	vgplane_st = to_virtio_gpu_plane_state(plane->state);
163 	bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
164 	if (vgplane_st->fence) {
165 		struct virtio_gpu_object_array *objs;
166 
167 		objs = virtio_gpu_array_alloc(1);
168 		if (!objs)
169 			return;
170 		virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
171 		virtio_gpu_array_lock_resv(objs);
172 		virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
173 					      width, height, objs,
174 					      vgplane_st->fence);
175 		virtio_gpu_notify(vgdev);
176 		dma_fence_wait_timeout(&vgplane_st->fence->f, true,
177 				       msecs_to_jiffies(50));
178 	} else {
179 		virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
180 					      width, height, NULL, NULL);
181 		virtio_gpu_notify(vgdev);
182 	}
183 }
184 
virtio_gpu_primary_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)185 static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
186 					    struct drm_atomic_state *state)
187 {
188 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
189 									   plane);
190 	struct drm_device *dev = plane->dev;
191 	struct virtio_gpu_device *vgdev = dev->dev_private;
192 	struct virtio_gpu_output *output = NULL;
193 	struct virtio_gpu_object *bo;
194 	struct drm_rect rect;
195 
196 	if (plane->state->crtc)
197 		output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
198 	if (old_state->crtc)
199 		output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
200 	if (WARN_ON(!output))
201 		return;
202 
203 	if (!plane->state->fb || !output->crtc.state->active) {
204 		DRM_DEBUG("nofb\n");
205 		virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
206 					   plane->state->src_w >> 16,
207 					   plane->state->src_h >> 16,
208 					   0, 0);
209 		virtio_gpu_notify(vgdev);
210 		return;
211 	}
212 
213 	if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
214 		return;
215 
216 	bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
217 	if (bo->dumb)
218 		virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
219 
220 	if (plane->state->fb != old_state->fb ||
221 	    plane->state->src_w != old_state->src_w ||
222 	    plane->state->src_h != old_state->src_h ||
223 	    plane->state->src_x != old_state->src_x ||
224 	    plane->state->src_y != old_state->src_y ||
225 	    output->needs_modeset) {
226 		output->needs_modeset = false;
227 		DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
228 			  bo->hw_res_handle,
229 			  plane->state->crtc_w, plane->state->crtc_h,
230 			  plane->state->crtc_x, plane->state->crtc_y,
231 			  plane->state->src_w >> 16,
232 			  plane->state->src_h >> 16,
233 			  plane->state->src_x >> 16,
234 			  plane->state->src_y >> 16);
235 
236 		if (bo->host3d_blob || bo->guest_blob) {
237 			virtio_gpu_cmd_set_scanout_blob
238 						(vgdev, output->index, bo,
239 						 plane->state->fb,
240 						 plane->state->src_w >> 16,
241 						 plane->state->src_h >> 16,
242 						 plane->state->src_x >> 16,
243 						 plane->state->src_y >> 16);
244 		} else {
245 			virtio_gpu_cmd_set_scanout(vgdev, output->index,
246 						   bo->hw_res_handle,
247 						   plane->state->src_w >> 16,
248 						   plane->state->src_h >> 16,
249 						   plane->state->src_x >> 16,
250 						   plane->state->src_y >> 16);
251 		}
252 	}
253 
254 	virtio_gpu_resource_flush(plane,
255 				  rect.x1,
256 				  rect.y1,
257 				  rect.x2 - rect.x1,
258 				  rect.y2 - rect.y1);
259 }
260 
virtio_gpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)261 static int virtio_gpu_plane_prepare_fb(struct drm_plane *plane,
262 				       struct drm_plane_state *new_state)
263 {
264 	struct drm_device *dev = plane->dev;
265 	struct virtio_gpu_device *vgdev = dev->dev_private;
266 	struct virtio_gpu_framebuffer *vgfb;
267 	struct virtio_gpu_plane_state *vgplane_st;
268 	struct virtio_gpu_object *bo;
269 
270 	if (!new_state->fb)
271 		return 0;
272 
273 	vgfb = to_virtio_gpu_framebuffer(new_state->fb);
274 	vgplane_st = to_virtio_gpu_plane_state(new_state);
275 	bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
276 	if (!bo || (plane->type == DRM_PLANE_TYPE_PRIMARY && !bo->guest_blob))
277 		return 0;
278 
279 	if (bo->dumb) {
280 		vgplane_st->fence = virtio_gpu_fence_alloc(vgdev,
281 						     vgdev->fence_drv.context,
282 						     0);
283 		if (!vgplane_st->fence)
284 			return -ENOMEM;
285 	}
286 
287 	return 0;
288 }
289 
virtio_gpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)290 static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane,
291 					struct drm_plane_state *state)
292 {
293 	struct virtio_gpu_plane_state *vgplane_st;
294 
295 	if (!state->fb)
296 		return;
297 
298 	vgplane_st = to_virtio_gpu_plane_state(state);
299 	if (vgplane_st->fence) {
300 		dma_fence_put(&vgplane_st->fence->f);
301 		vgplane_st->fence = NULL;
302 	}
303 }
304 
virtio_gpu_cursor_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)305 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
306 					   struct drm_atomic_state *state)
307 {
308 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
309 									   plane);
310 	struct drm_device *dev = plane->dev;
311 	struct virtio_gpu_device *vgdev = dev->dev_private;
312 	struct virtio_gpu_output *output = NULL;
313 	struct virtio_gpu_framebuffer *vgfb;
314 	struct virtio_gpu_plane_state *vgplane_st;
315 	struct virtio_gpu_object *bo = NULL;
316 	uint32_t handle;
317 
318 	if (plane->state->crtc)
319 		output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
320 	if (old_state->crtc)
321 		output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
322 	if (WARN_ON(!output))
323 		return;
324 
325 	if (plane->state->fb) {
326 		vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
327 		vgplane_st = to_virtio_gpu_plane_state(plane->state);
328 		bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
329 		handle = bo->hw_res_handle;
330 	} else {
331 		handle = 0;
332 	}
333 
334 	if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
335 		/* new cursor -- update & wait */
336 		struct virtio_gpu_object_array *objs;
337 
338 		objs = virtio_gpu_array_alloc(1);
339 		if (!objs)
340 			return;
341 		virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
342 		virtio_gpu_array_lock_resv(objs);
343 		virtio_gpu_cmd_transfer_to_host_2d
344 			(vgdev, 0,
345 			 plane->state->crtc_w,
346 			 plane->state->crtc_h,
347 			 0, 0, objs, vgplane_st->fence);
348 		virtio_gpu_notify(vgdev);
349 		dma_fence_wait(&vgplane_st->fence->f, true);
350 	}
351 
352 	if (plane->state->fb != old_state->fb) {
353 		DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
354 			  plane->state->crtc_x,
355 			  plane->state->crtc_y,
356 			  plane->state->fb ? plane->state->fb->hot_x : 0,
357 			  plane->state->fb ? plane->state->fb->hot_y : 0);
358 		output->cursor.hdr.type =
359 			cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
360 		output->cursor.resource_id = cpu_to_le32(handle);
361 		if (plane->state->fb) {
362 			output->cursor.hot_x =
363 				cpu_to_le32(plane->state->fb->hot_x);
364 			output->cursor.hot_y =
365 				cpu_to_le32(plane->state->fb->hot_y);
366 		} else {
367 			output->cursor.hot_x = cpu_to_le32(0);
368 			output->cursor.hot_y = cpu_to_le32(0);
369 		}
370 	} else {
371 		DRM_DEBUG("move +%d+%d\n",
372 			  plane->state->crtc_x,
373 			  plane->state->crtc_y);
374 		output->cursor.hdr.type =
375 			cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
376 	}
377 	output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
378 	output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
379 	virtio_gpu_cursor_ping(vgdev, output);
380 }
381 
382 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
383 	.prepare_fb		= virtio_gpu_plane_prepare_fb,
384 	.cleanup_fb		= virtio_gpu_plane_cleanup_fb,
385 	.atomic_check		= virtio_gpu_plane_atomic_check,
386 	.atomic_update		= virtio_gpu_primary_plane_update,
387 };
388 
389 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
390 	.prepare_fb		= virtio_gpu_plane_prepare_fb,
391 	.cleanup_fb		= virtio_gpu_plane_cleanup_fb,
392 	.atomic_check		= virtio_gpu_plane_atomic_check,
393 	.atomic_update		= virtio_gpu_cursor_plane_update,
394 };
395 
virtio_gpu_plane_init(struct virtio_gpu_device * vgdev,enum drm_plane_type type,int index)396 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
397 					enum drm_plane_type type,
398 					int index)
399 {
400 	struct drm_device *dev = vgdev->ddev;
401 	const struct drm_plane_helper_funcs *funcs;
402 	struct drm_plane *plane;
403 	const uint32_t *formats;
404 	int nformats;
405 
406 	if (type == DRM_PLANE_TYPE_CURSOR) {
407 		formats = virtio_gpu_cursor_formats;
408 		nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
409 		funcs = &virtio_gpu_cursor_helper_funcs;
410 	} else {
411 		formats = virtio_gpu_formats;
412 		nformats = ARRAY_SIZE(virtio_gpu_formats);
413 		funcs = &virtio_gpu_primary_helper_funcs;
414 	}
415 
416 	plane = drmm_universal_plane_alloc(dev, struct drm_plane, dev,
417 					   1 << index, &virtio_gpu_plane_funcs,
418 					   formats, nformats, NULL, type, NULL);
419 	if (IS_ERR(plane))
420 		return plane;
421 
422 	drm_plane_helper_add(plane, funcs);
423 
424 	if (type == DRM_PLANE_TYPE_PRIMARY)
425 		drm_plane_enable_fb_damage_clips(plane);
426 
427 	return plane;
428 }
429