1 /*
2  * MPC8xx Internal Memory Map
3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4  *
5  * The I/O on the MPC860 is comprised of blocks of special registers
6  * and the dual port ram for the Communication Processor Module.
7  * Within this space are functional units such as the SIU, memory
8  * controller, system timers, and other control functions.  It is
9  * a combination that I found difficult to separate into logical
10  * functional files.....but anyone else is welcome to try.  -- Dan
11  */
12 #ifdef __KERNEL__
13 #ifndef __IMMAP_8XX__
14 #define __IMMAP_8XX__
15 
16 /* System configuration registers.
17 */
18 typedef	struct sys_conf {
19 	uint	sc_siumcr;
20 	uint	sc_sypcr;
21 	uint	sc_swt;
22 	char	res1[2];
23 	ushort	sc_swsr;
24 	uint	sc_sipend;
25 	uint	sc_simask;
26 	uint	sc_siel;
27 	uint	sc_sivec;
28 	uint	sc_tesr;
29 	char	res2[0xc];
30 	uint	sc_sdcr;
31 	char	res3[0x4c];
32 } sysconf8xx_t;
33 
34 /* PCMCIA configuration registers.
35 */
36 typedef struct pcmcia_conf {
37 	uint	pcmc_pbr0;
38 	uint	pcmc_por0;
39 	uint	pcmc_pbr1;
40 	uint	pcmc_por1;
41 	uint	pcmc_pbr2;
42 	uint	pcmc_por2;
43 	uint	pcmc_pbr3;
44 	uint	pcmc_por3;
45 	uint	pcmc_pbr4;
46 	uint	pcmc_por4;
47 	uint	pcmc_pbr5;
48 	uint	pcmc_por5;
49 	uint	pcmc_pbr6;
50 	uint	pcmc_por6;
51 	uint	pcmc_pbr7;
52 	uint	pcmc_por7;
53 	char	res1[0x20];
54 	uint	pcmc_pgcra;
55 	uint	pcmc_pgcrb;
56 	uint	pcmc_pscr;
57 	char	res2[4];
58 	uint	pcmc_pipr;
59 	char	res3[4];
60 	uint	pcmc_per;
61 	char	res4[4];
62 } pcmconf8xx_t;
63 
64 /* Memory controller registers.
65 */
66 typedef struct	mem_ctlr {
67 	uint	memc_br0;
68 	uint	memc_or0;
69 	uint	memc_br1;
70 	uint	memc_or1;
71 	uint	memc_br2;
72 	uint	memc_or2;
73 	uint	memc_br3;
74 	uint	memc_or3;
75 	uint	memc_br4;
76 	uint	memc_or4;
77 	uint	memc_br5;
78 	uint	memc_or5;
79 	uint	memc_br6;
80 	uint	memc_or6;
81 	uint	memc_br7;
82 	uint	memc_or7;
83 	char	res1[0x24];
84 	uint	memc_mar;
85 	uint	memc_mcr;
86 	char	res2[4];
87 	uint	memc_mamr;
88 	uint	memc_mbmr;
89 	ushort	memc_mstat;
90 	ushort	memc_mptpr;
91 	uint	memc_mdr;
92 	char	res3[0x80];
93 } memctl8xx_t;
94 
95 /*-----------------------------------------------------------------------
96  * BR - Memory Controller: Base Register					16-9
97  */
98 #define BR_BA_MSK	0xffff8000	/* Base Address Mask			*/
99 #define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
100 #define BR_PS_MSK	0x00000c00	/* Port Size Mask			*/
101 #define BR_PS_32	0x00000000	/* 32 bit port size			*/
102 #define BR_PS_16	0x00000800	/* 16 bit port size			*/
103 #define BR_PS_8		0x00000400	/*  8 bit port size			*/
104 #define BR_PARE		0x00000200	/* Parity Enable			*/
105 #define BR_WP		0x00000100	/* Write Protect			*/
106 #define BR_MS_MSK	0x000000c0	/* Machine Select Mask			*/
107 #define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
108 #define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
109 #define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select		*/
110 #define BR_V		0x00000001	/* Bank Valid				*/
111 
112 /*-----------------------------------------------------------------------
113  * OR - Memory Controller: Option Register				16-11
114  */
115 #define OR_AM_MSK	0xffff8000	/* Address Mask Mask			*/
116 #define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
117 #define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
118 					/* Address Multiplex			*/
119 #define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
120 #define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
121 #define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
122 #define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
123 #define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
124 #define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
125 #define OR_BI		0x00000100	/* Burst inhibit			*/
126 #define OR_SCY_MSK	0x000000f0	/* Cycle Length in Clocks		*/
127 #define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
128 #define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
129 #define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
130 #define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
131 #define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
132 #define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
133 #define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
134 #define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
135 #define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
136 #define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
137 #define OR_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states		*/
138 #define OR_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states		*/
139 #define OR_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states		*/
140 #define OR_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states		*/
141 #define OR_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states		*/
142 #define OR_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states		*/
143 #define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
144 #define OR_TRLX		0x00000004	/* Timing Relaxed			*/
145 #define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
146 
147 /* System Integration Timers.
148 */
149 typedef struct	sys_int_timers {
150 	ushort	sit_tbscr;
151 	char	res0[0x02];
152 	uint	sit_tbreff0;
153 	uint	sit_tbreff1;
154 	char	res1[0x14];
155 	ushort	sit_rtcsc;
156 	char	res2[0x02];
157 	uint	sit_rtc;
158 	uint	sit_rtsec;
159 	uint	sit_rtcal;
160 	char	res3[0x10];
161 	ushort	sit_piscr;
162 	char	res4[2];
163 	uint	sit_pitc;
164 	uint	sit_pitr;
165 	char	res5[0x34];
166 } sit8xx_t;
167 
168 #define TBSCR_TBIRQ_MASK	((ushort)0xff00)
169 #define TBSCR_REFA		((ushort)0x0080)
170 #define TBSCR_REFB		((ushort)0x0040)
171 #define TBSCR_REFAE		((ushort)0x0008)
172 #define TBSCR_REFBE		((ushort)0x0004)
173 #define TBSCR_TBF		((ushort)0x0002)
174 #define TBSCR_TBE		((ushort)0x0001)
175 
176 #define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
177 #define RTCSC_SEC		((ushort)0x0080)
178 #define RTCSC_ALR		((ushort)0x0040)
179 #define RTCSC_38K		((ushort)0x0010)
180 #define RTCSC_SIE		((ushort)0x0008)
181 #define RTCSC_ALE		((ushort)0x0004)
182 #define RTCSC_RTF		((ushort)0x0002)
183 #define RTCSC_RTE		((ushort)0x0001)
184 
185 #define PISCR_PIRQ_MASK		((ushort)0xff00)
186 #define PISCR_PS		((ushort)0x0080)
187 #define PISCR_PIE		((ushort)0x0004)
188 #define PISCR_PTF		((ushort)0x0002)
189 #define PISCR_PTE		((ushort)0x0001)
190 
191 /* Clocks and Reset.
192 */
193 typedef struct clk_and_reset {
194 	uint	car_sccr;
195 	uint	car_plprcr;
196 	uint	car_rsr;
197 	char	res[0x74];        /* Reserved area                  */
198 } car8xx_t;
199 
200 /* System Integration Timers keys.
201 */
202 typedef struct sitk {
203 	uint	sitk_tbscrk;
204 	uint	sitk_tbreff0k;
205 	uint	sitk_tbreff1k;
206 	uint	sitk_tbk;
207 	char	res1[0x10];
208 	uint	sitk_rtcsck;
209 	uint	sitk_rtck;
210 	uint	sitk_rtseck;
211 	uint	sitk_rtcalk;
212 	char	res2[0x10];
213 	uint	sitk_piscrk;
214 	uint	sitk_pitck;
215 	char	res3[0x38];
216 } sitk8xx_t;
217 
218 /* Clocks and reset keys.
219 */
220 typedef struct cark {
221 	uint	cark_sccrk;
222 	uint	cark_plprcrk;
223 	uint	cark_rsrk;
224 	char	res[0x474];
225 } cark8xx_t;
226 
227 /* The key to unlock registers maintained by keep-alive power.
228 */
229 #define KAPWR_KEY	((unsigned int)0x55ccaa33)
230 
231 /* Video interface.  MPC823 Only.
232 */
233 typedef struct vid823 {
234 	ushort	vid_vccr;
235 	ushort	res1;
236 	u_char	vid_vsr;
237 	u_char	res2;
238 	u_char	vid_vcmr;
239 	u_char	res3;
240 	uint	vid_vbcb;
241 	uint	res4;
242 	uint	vid_vfcr0;
243 	uint	vid_vfaa0;
244 	uint	vid_vfba0;
245 	uint	vid_vfcr1;
246 	uint	vid_vfaa1;
247 	uint	vid_vfba1;
248 	u_char	res5[0x18];
249 } vid823_t;
250 
251 /* LCD interface.  823 Only.
252 */
253 typedef struct lcd {
254 	uint	lcd_lccr;
255 	uint	lcd_lchcr;
256 	uint	lcd_lcvcr;
257 	char	res1[4];
258 	uint	lcd_lcfaa;
259 	uint	lcd_lcfba;
260 	char	lcd_lcsr;
261 	char	res2[0x7];
262 } lcd823_t;
263 
264 /* I2C
265 */
266 typedef struct i2c {
267 	u_char	i2c_i2mod;
268 	char	res1[3];
269 	u_char	i2c_i2add;
270 	char	res2[3];
271 	u_char	i2c_i2brg;
272 	char	res3[3];
273 	u_char	i2c_i2com;
274 	char	res4[3];
275 	u_char	i2c_i2cer;
276 	char	res5[3];
277 	u_char	i2c_i2cmr;
278 	char	res6[0x8b];
279 } i2c8xx_t;
280 
281 /* DMA control/status registers.
282 */
283 typedef struct sdma_csr {
284 	char	res1[4];
285 	uint	sdma_sdar;
286 	u_char	sdma_sdsr;
287 	char	res3[3];
288 	u_char	sdma_sdmr;
289 	char	res4[3];
290 	u_char	sdma_idsr1;
291 	char	res5[3];
292 	u_char	sdma_idmr1;
293 	char	res6[3];
294 	u_char	sdma_idsr2;
295 	char	res7[3];
296 	u_char	sdma_idmr2;
297 	char	res8[0x13];
298 } sdma8xx_t;
299 
300 /* Communication Processor Module Interrupt Controller.
301 */
302 typedef struct cpm_ic {
303 	ushort	cpic_civr;
304 	char	res[0xe];
305 	uint	cpic_cicr;
306 	uint	cpic_cipr;
307 	uint	cpic_cimr;
308 	uint	cpic_cisr;
309 } cpic8xx_t;
310 
311 /* Input/Output Port control/status registers.
312 */
313 typedef struct io_port {
314 	ushort	iop_padir;
315 	ushort	iop_papar;
316 	ushort	iop_paodr;
317 	ushort	iop_padat;
318 	char	res1[8];
319 	ushort	iop_pcdir;
320 	ushort	iop_pcpar;
321 	ushort	iop_pcso;
322 	ushort	iop_pcdat;
323 	ushort	iop_pcint;
324 	char	res2[6];
325 	ushort	iop_pddir;
326 	ushort	iop_pdpar;
327 	char	res3[2];
328 	ushort	iop_pddat;
329 	uint	utmode;
330 	char	res4[4];
331 } iop8xx_t;
332 
333 /* Communication Processor Module Timers
334 */
335 typedef struct cpm_timers {
336 	ushort	cpmt_tgcr;
337 	char	res1[0xe];
338 	ushort	cpmt_tmr1;
339 	ushort	cpmt_tmr2;
340 	ushort	cpmt_trr1;
341 	ushort	cpmt_trr2;
342 	ushort	cpmt_tcr1;
343 	ushort	cpmt_tcr2;
344 	ushort	cpmt_tcn1;
345 	ushort	cpmt_tcn2;
346 	ushort	cpmt_tmr3;
347 	ushort	cpmt_tmr4;
348 	ushort	cpmt_trr3;
349 	ushort	cpmt_trr4;
350 	ushort	cpmt_tcr3;
351 	ushort	cpmt_tcr4;
352 	ushort	cpmt_tcn3;
353 	ushort	cpmt_tcn4;
354 	ushort	cpmt_ter1;
355 	ushort	cpmt_ter2;
356 	ushort	cpmt_ter3;
357 	ushort	cpmt_ter4;
358 	char	res2[8];
359 } cpmtimer8xx_t;
360 
361 /* Finally, the Communication Processor stuff.....
362 */
363 typedef struct scc {		/* Serial communication channels */
364 	uint	scc_gsmrl;
365 	uint	scc_gsmrh;
366 	ushort	scc_psmr;
367 	char	res1[2];
368 	ushort	scc_todr;
369 	ushort	scc_dsr;
370 	ushort	scc_scce;
371 	char	res2[2];
372 	ushort	scc_sccm;
373 	char	res3;
374 	u_char	scc_sccs;
375 	char	res4[8];
376 } scc_t;
377 
378 typedef struct smc {		/* Serial management channels */
379 	char	res1[2];
380 	ushort	smc_smcmr;
381 	char	res2[2];
382 	u_char	smc_smce;
383 	char	res3[3];
384 	u_char	smc_smcm;
385 	char	res4[5];
386 } smc_t;
387 
388 /* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
389  * it fits within the address space.
390  */
391 
392 typedef struct fec {
393 	uint	fec_addr_low;		/* lower 32 bits of station address	*/
394 	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
395 	ushort	res1;			/* reserved				*/
396 	uint	fec_grp_hash_table_high;	/* upper 32-bits of hash table		*/
397 	uint	fec_grp_hash_table_low;	/* lower 32-bits of hash table		*/
398 	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
399 	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
400 	uint	fec_r_buff_size;	/* Rx buffer size			*/
401 	uint	res2[9];		/* reserved				*/
402 	uint	fec_ecntrl;		/* ethernet control register		*/
403 	uint	fec_ievent;		/* interrupt event register		*/
404 	uint	fec_imask;		/* interrupt mask register		*/
405 	uint	fec_ivec;		/* interrupt level and vector status	*/
406 	uint	fec_r_des_active;	/* Rx ring updated flag			*/
407 	uint	fec_x_des_active;	/* Tx ring updated flag			*/
408 	uint	res3[10];		/* reserved				*/
409 	uint	fec_mii_data;		/* MII data register			*/
410 	uint	fec_mii_speed;		/* MII speed control register		*/
411 	uint	res4[17];		/* reserved				*/
412 	uint	fec_r_bound;		/* end of RAM (read-only)		*/
413 	uint	fec_r_fstart;		/* Rx FIFO start address		*/
414 	uint	res5[6];		/* reserved				*/
415 	uint	fec_x_fstart;		/* Tx FIFO start address		*/
416 	uint	res6[17];		/* reserved				*/
417 	uint	fec_fun_code;		/* fec SDMA function code		*/
418 	uint	res7[3];		/* reserved				*/
419 	uint	fec_r_cntrl;		/* Rx control register			*/
420 	uint	fec_r_hash;		/* Rx hash register			*/
421 	uint	res8[14];		/* reserved				*/
422 	uint	fec_x_cntrl;		/* Tx control register			*/
423 	uint	res9[0x1e];		/* reserved				*/
424 } fec_t;
425 
426 /* The FEC and LCD color map share the same address space....
427  * I guess we will never see an 823T :-).
428  */
429 union fec_lcd {
430 	fec_t	fl_un_fec;
431 	u_char	fl_un_cmap[0x200];
432 };
433 
434 typedef struct comm_proc {
435 	/* General control and status registers.
436 	*/
437 	ushort	cp_cpcr;
438 	u_char	res1[2];
439 	ushort	cp_rccr;
440 	u_char	res2;
441 	u_char	cp_rmds;
442 	u_char	res3[4];
443 	ushort	cp_cpmcr1;
444 	ushort	cp_cpmcr2;
445 	ushort	cp_cpmcr3;
446 	ushort	cp_cpmcr4;
447 	u_char	res4[2];
448 	ushort	cp_rter;
449 	u_char	res5[2];
450 	ushort	cp_rtmr;
451 	u_char	res6[0x14];
452 
453 	/* Baud rate generators.
454 	*/
455 	uint	cp_brgc1;
456 	uint	cp_brgc2;
457 	uint	cp_brgc3;
458 	uint	cp_brgc4;
459 
460 	/* Serial Communication Channels.
461 	*/
462 	scc_t	cp_scc[4];
463 
464 	/* Serial Management Channels.
465 	*/
466 	smc_t	cp_smc[2];
467 
468 	/* Serial Peripheral Interface.
469 	*/
470 	ushort	cp_spmode;
471 	u_char	res7[4];
472 	u_char	cp_spie;
473 	u_char	res8[3];
474 	u_char	cp_spim;
475 	u_char	res9[2];
476 	u_char	cp_spcom;
477 	u_char	res10[2];
478 
479 	/* Parallel Interface Port.
480 	*/
481 	u_char	res11[2];
482 	ushort	cp_pipc;
483 	u_char	res12[2];
484 	ushort	cp_ptpr;
485 	uint	cp_pbdir;
486 	uint	cp_pbpar;
487 	u_char	res13[2];
488 	ushort	cp_pbodr;
489 	uint	cp_pbdat;
490 
491 	/* Port E - MPC87x/88x only.
492 	 */
493 	uint	cp_pedir;
494 	uint	cp_pepar;
495 	uint	cp_peso;
496 	uint	cp_peodr;
497 	uint	cp_pedat;
498 
499 	/* Communications Processor Timing Register -
500 	   Contains RMII Timing for the FECs on MPC87x/88x only.
501 	*/
502 	uint	cp_cptr;
503 
504 	/* Serial Interface and Time Slot Assignment.
505 	*/
506 	uint	cp_simode;
507 	u_char	cp_sigmr;
508 	u_char	res15;
509 	u_char	cp_sistr;
510 	u_char	cp_sicmr;
511 	u_char	res16[4];
512 	uint	cp_sicr;
513 	uint	cp_sirp;
514 	u_char	res17[0xc];
515 
516 	/* 256 bytes of MPC823 video controller RAM array.
517 	*/
518 	u_char	cp_vcram[0x100];
519 	u_char	cp_siram[0x200];
520 
521 	/* The fast ethernet controller is not really part of the CPM,
522 	 * but it resides in the address space.
523 	 * The LCD color map is also here.
524 	 */
525 	union	fec_lcd	fl_un;
526 #define cp_fec		fl_un.fl_un_fec
527 #define lcd_cmap	fl_un.fl_un_cmap
528 	char	res18[0xE00];
529 
530 	/* The DUET family has a second FEC here */
531 	fec_t	cp_fec2;
532 #define cp_fec1	cp_fec	/* consistency macro */
533 
534 	/* Dual Ported RAM follows.
535 	 * There are many different formats for this memory area
536 	 * depending upon the devices used and options chosen.
537 	 * Some processors don't have all of it populated.
538 	 */
539 	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
540 	u_char	cp_dparam[0x400];	/* Parameter RAM */
541 } cpm8xx_t;
542 
543 /* Internal memory map.
544 */
545 typedef struct immap {
546 	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
547 	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
548 	memctl8xx_t	im_memctl;	/* Memory Controller */
549 	sit8xx_t	im_sit;		/* System integration timers */
550 	car8xx_t	im_clkrst;	/* Clocks and reset */
551 	sitk8xx_t	im_sitk;	/* Sys int timer keys */
552 	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
553 	vid823_t	im_vid;		/* Video (823 only) */
554 	lcd823_t	im_lcd;		/* LCD (823 only) */
555 	i2c8xx_t	im_i2c;		/* I2C control/status */
556 	sdma8xx_t	im_sdma;	/* SDMA control/status */
557 	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
558 	iop8xx_t	im_ioport;	/* IO Port control/status */
559 	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
560 	cpm8xx_t	im_cpm;		/* Communication processor */
561 } immap_t;
562 
563 extern immap_t __iomem *mpc8xx_immr;
564 
565 #endif /* __IMMAP_8XX__ */
566 #endif /* __KERNEL__ */
567