1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28 
29 // For dce12_get_dp_ref_freq_khz
30 #include "dce100/dce_clk_mgr.h"
31 
32 // For dcn20_update_clocks_update_dpp_dto
33 #include "dcn20/dcn20_clk_mgr.h"
34 
35 // For DML FPU code
36 #include "dml/dcn20/dcn20_fpu.h"
37 
38 #include "vg_clk_mgr.h"
39 #include "dcn301_smu.h"
40 #include "reg_helper.h"
41 #include "core_types.h"
42 #include "dm_helpers.h"
43 
44 #include "atomfirmware.h"
45 #include "vangogh_ip_offset.h"
46 #include "clk/clk_11_5_0_offset.h"
47 #include "clk/clk_11_5_0_sh_mask.h"
48 
49 /* Constants */
50 
51 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
52 
53 /* Macros */
54 
55 #define TO_CLK_MGR_VGH(clk_mgr)\
56 	container_of(clk_mgr, struct clk_mgr_vgh, base)
57 
58 #define REG(reg_name) \
59 	(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
60 
61 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
vg_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)62 static int vg_get_active_display_cnt_wa(
63 		struct dc *dc,
64 		struct dc_state *context)
65 {
66 	int i, display_count;
67 	bool tmds_present = false;
68 
69 	display_count = 0;
70 	for (i = 0; i < context->stream_count; i++) {
71 		const struct dc_stream_state *stream = context->streams[i];
72 
73 		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
74 				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
75 				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
76 			tmds_present = true;
77 	}
78 
79 	for (i = 0; i < dc->link_count; i++) {
80 		const struct dc_link *link = dc->links[i];
81 
82 		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
83 		if (link->link_enc->funcs->is_dig_enabled &&
84 				link->link_enc->funcs->is_dig_enabled(link->link_enc))
85 			display_count++;
86 	}
87 
88 	/* WA for hang on HDMI after display off back back on*/
89 	if (display_count == 0 && tmds_present)
90 		display_count = 1;
91 
92 	return display_count;
93 }
94 
vg_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)95 static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
96 			     struct dc_state *context,
97 			     bool safe_to_lower)
98 {
99 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
100 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
101 	struct dc *dc = clk_mgr_base->ctx->dc;
102 	int display_count;
103 	bool update_dppclk = false;
104 	bool update_dispclk = false;
105 	bool dpp_clock_lowered = false;
106 
107 	if (dc->work_arounds.skip_clock_update)
108 		return;
109 
110 	/*
111 	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
112 	 * also if safe to lower is false, we just go in the higher state
113 	 */
114 	if (safe_to_lower) {
115 		/* check that we're not already in lower */
116 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
117 
118 			display_count = vg_get_active_display_cnt_wa(dc, context);
119 			/* if we can go lower, go lower */
120 			if (display_count == 0) {
121 				union display_idle_optimization_u idle_info = { 0 };
122 
123 				idle_info.idle_info.df_request_disabled = 1;
124 				idle_info.idle_info.phy_ref_clk_off = 1;
125 
126 				dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
127 				/* update power state */
128 				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
129 			}
130 		}
131 	} else {
132 		/* check that we're not already in D0 */
133 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
134 			union display_idle_optimization_u idle_info = { 0 };
135 
136 			dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
137 			/* update power state */
138 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
139 		}
140 	}
141 
142 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {
143 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
144 		dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
145 	}
146 
147 	if (should_set_clock(safe_to_lower,
148 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {
149 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
150 		dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
151 	}
152 
153 	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
154 	if (new_clocks->dppclk_khz < 100000)
155 		new_clocks->dppclk_khz = 100000;
156 
157 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
158 		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
159 			dpp_clock_lowered = true;
160 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
161 		update_dppclk = true;
162 	}
163 
164 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
165 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
166 		dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
167 
168 		update_dispclk = true;
169 	}
170 
171 	if (dpp_clock_lowered) {
172 		// increase per DPP DTO before lowering global dppclk
173 		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
174 		dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
175 	} else {
176 		// increase global DPPCLK before lowering per DPP DTO
177 		if (update_dppclk || update_dispclk)
178 			dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
179 		// always update dtos unless clock is lowered and not safe to lower
180 		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
181 	}
182 }
183 
184 
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)185 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
186 {
187 	/* get FbMult value */
188 	struct fixed31_32 pll_req;
189 	unsigned int fbmult_frac_val = 0;
190 	unsigned int fbmult_int_val = 0;
191 
192 
193 	/*
194 	 * Register value of fbmult is in 8.16 format, we are converting to 31.32
195 	 * to leverage the fix point operations available in driver
196 	 */
197 
198 	REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
199 	REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
200 
201 	pll_req = dc_fixpt_from_int(fbmult_int_val);
202 
203 	/*
204 	 * since fractional part is only 16 bit in register definition but is 32 bit
205 	 * in our fix point definiton, need to shift left by 16 to obtain correct value
206 	 */
207 	pll_req.value |= fbmult_frac_val << 16;
208 
209 	/* multiply by REFCLK period */
210 	pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
211 
212 	/* integer part is now VCO frequency in kHz */
213 	return dc_fixpt_floor(pll_req);
214 }
215 
vg_dump_clk_registers_internal(struct dcn301_clk_internal * internal,struct clk_mgr * clk_mgr_base)216 static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
217 {
218 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
219 
220 	internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
221 	internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
222 
223 	internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL);	//dcf deep sleep divider
224 	internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
225 
226 	internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
227 	internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
228 
229 	internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
230 	internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
231 
232 	internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
233 	internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
234 }
235 
236 /* This function collect raw clk register values */
vg_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)237 static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
238 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
239 {
240 	struct dcn301_clk_internal internal = {0};
241 	char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
242 	unsigned int chars_printed = 0;
243 	unsigned int remaining_buffer = log_info->bufSize;
244 
245 	vg_dump_clk_registers_internal(&internal, clk_mgr_base);
246 
247 	regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
248 	regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
249 	regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
250 	regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
251 	regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
252 	regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
253 
254 	regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
255 	if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
256 		regs_and_bypass->dppclk_bypass = 0;
257 	regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
258 	if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
259 		regs_and_bypass->dcfclk_bypass = 0;
260 	regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
261 	if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
262 		regs_and_bypass->dispclk_bypass = 0;
263 	regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
264 	if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
265 		regs_and_bypass->dprefclk_bypass = 0;
266 
267 	if (log_info->enabled) {
268 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
269 		remaining_buffer -= chars_printed;
270 		*log_info->sum_chars_printed += chars_printed;
271 		log_info->pBuf += chars_printed;
272 
273 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
274 			regs_and_bypass->dcfclk,
275 			regs_and_bypass->dcf_deep_sleep_divider,
276 			regs_and_bypass->dcf_deep_sleep_allow,
277 			bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
278 		remaining_buffer -= chars_printed;
279 		*log_info->sum_chars_printed += chars_printed;
280 		log_info->pBuf += chars_printed;
281 
282 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
283 			regs_and_bypass->dprefclk,
284 			bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
285 		remaining_buffer -= chars_printed;
286 		*log_info->sum_chars_printed += chars_printed;
287 		log_info->pBuf += chars_printed;
288 
289 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
290 			regs_and_bypass->dispclk,
291 			bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
292 		remaining_buffer -= chars_printed;
293 		*log_info->sum_chars_printed += chars_printed;
294 		log_info->pBuf += chars_printed;
295 
296 		//split
297 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
298 		remaining_buffer -= chars_printed;
299 		*log_info->sum_chars_printed += chars_printed;
300 		log_info->pBuf += chars_printed;
301 
302 		// REGISTER VALUES
303 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
304 		remaining_buffer -= chars_printed;
305 		*log_info->sum_chars_printed += chars_printed;
306 		log_info->pBuf += chars_printed;
307 
308 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
309 				internal.CLK1_CLK3_CURRENT_CNT);
310 		remaining_buffer -= chars_printed;
311 		*log_info->sum_chars_printed += chars_printed;
312 		log_info->pBuf += chars_printed;
313 
314 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
315 					internal.CLK1_CLK3_DS_CNTL);
316 		remaining_buffer -= chars_printed;
317 		*log_info->sum_chars_printed += chars_printed;
318 		log_info->pBuf += chars_printed;
319 
320 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
321 					internal.CLK1_CLK3_ALLOW_DS);
322 		remaining_buffer -= chars_printed;
323 		*log_info->sum_chars_printed += chars_printed;
324 		log_info->pBuf += chars_printed;
325 
326 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
327 					internal.CLK1_CLK2_CURRENT_CNT);
328 		remaining_buffer -= chars_printed;
329 		*log_info->sum_chars_printed += chars_printed;
330 		log_info->pBuf += chars_printed;
331 
332 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
333 					internal.CLK1_CLK0_CURRENT_CNT);
334 		remaining_buffer -= chars_printed;
335 		*log_info->sum_chars_printed += chars_printed;
336 		log_info->pBuf += chars_printed;
337 
338 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
339 					internal.CLK1_CLK1_CURRENT_CNT);
340 		remaining_buffer -= chars_printed;
341 		*log_info->sum_chars_printed += chars_printed;
342 		log_info->pBuf += chars_printed;
343 
344 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
345 					internal.CLK1_CLK3_BYPASS_CNTL);
346 		remaining_buffer -= chars_printed;
347 		*log_info->sum_chars_printed += chars_printed;
348 		log_info->pBuf += chars_printed;
349 
350 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
351 					internal.CLK1_CLK2_BYPASS_CNTL);
352 		remaining_buffer -= chars_printed;
353 		*log_info->sum_chars_printed += chars_printed;
354 		log_info->pBuf += chars_printed;
355 
356 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
357 					internal.CLK1_CLK0_BYPASS_CNTL);
358 		remaining_buffer -= chars_printed;
359 		*log_info->sum_chars_printed += chars_printed;
360 		log_info->pBuf += chars_printed;
361 
362 		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
363 					internal.CLK1_CLK1_BYPASS_CNTL);
364 		remaining_buffer -= chars_printed;
365 		*log_info->sum_chars_printed += chars_printed;
366 		log_info->pBuf += chars_printed;
367 	}
368 }
369 
vg_enable_pme_wa(struct clk_mgr * clk_mgr_base)370 static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
371 {
372 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
373 
374 	dcn301_smu_enable_pme_wa(clk_mgr);
375 }
376 
vg_init_clocks(struct clk_mgr * clk_mgr)377 static void vg_init_clocks(struct clk_mgr *clk_mgr)
378 {
379 	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
380 	// Assumption is that boot state always supports pstate
381 	clk_mgr->clks.p_state_change_support = true;
382 	clk_mgr->clks.prev_p_state_change_support = true;
383 	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
384 }
385 
vg_build_watermark_ranges(struct clk_bw_params * bw_params,struct watermarks * table)386 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
387 {
388 	int i, num_valid_sets;
389 
390 	num_valid_sets = 0;
391 
392 	for (i = 0; i < WM_SET_COUNT; i++) {
393 		/* skip empty entries, the smu array has no holes*/
394 		if (!bw_params->wm_table.entries[i].valid)
395 			continue;
396 
397 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
398 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
399 		/* We will not select WM based on fclk, so leave it as unconstrained */
400 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
401 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
402 
403 		if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
404 			if (i == 0)
405 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
406 			else {
407 				/* add 1 to make it non-overlapping with next lvl */
408 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
409 						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
410 			}
411 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
412 					bw_params->clk_table.entries[i].dcfclk_mhz;
413 
414 		} else {
415 			/* unconstrained for memory retraining */
416 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
417 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
418 
419 			/* Modify previous watermark range to cover up to max */
420 			table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
421 		}
422 		num_valid_sets++;
423 	}
424 
425 	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
426 
427 	/* modify the min and max to make sure we cover the whole range*/
428 	table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
429 	table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
430 	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
431 	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
432 
433 	/* This is for writeback only, does not matter currently as no writeback support*/
434 	table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
435 	table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
436 	table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
437 	table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
438 	table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
439 }
440 
441 
vg_notify_wm_ranges(struct clk_mgr * clk_mgr_base)442 static void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
443 {
444 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
445 	struct clk_mgr_vgh *clk_mgr_vgh = TO_CLK_MGR_VGH(clk_mgr);
446 	struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set;
447 
448 	if (!clk_mgr->smu_ver)
449 		return;
450 
451 	if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0)
452 		return;
453 
454 	memset(table, 0, sizeof(*table));
455 
456 	vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
457 
458 	dcn301_smu_set_dram_addr_high(clk_mgr,
459 			clk_mgr_vgh->smu_wm_set.mc_address.high_part);
460 	dcn301_smu_set_dram_addr_low(clk_mgr,
461 			clk_mgr_vgh->smu_wm_set.mc_address.low_part);
462 	dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
463 }
464 
vg_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)465 static bool vg_are_clock_states_equal(struct dc_clocks *a,
466 		struct dc_clocks *b)
467 {
468 	if (a->dispclk_khz != b->dispclk_khz)
469 		return false;
470 	else if (a->dppclk_khz != b->dppclk_khz)
471 		return false;
472 	else if (a->dcfclk_khz != b->dcfclk_khz)
473 		return false;
474 	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
475 		return false;
476 
477 	return true;
478 }
479 
480 
481 static struct clk_mgr_funcs vg_funcs = {
482 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
483 	.update_clocks = vg_update_clocks,
484 	.init_clocks = vg_init_clocks,
485 	.enable_pme_wa = vg_enable_pme_wa,
486 	.are_clock_states_equal = vg_are_clock_states_equal,
487 	.notify_wm_ranges = vg_notify_wm_ranges
488 };
489 
490 static struct clk_bw_params vg_bw_params = {
491 	.vram_type = Ddr4MemType,
492 	.num_channels = 1,
493 	.clk_table = {
494 		.entries = {
495 			{
496 				.voltage = 0,
497 				.dcfclk_mhz = 400,
498 				.fclk_mhz = 400,
499 				.memclk_mhz = 800,
500 				.socclk_mhz = 0,
501 			},
502 			{
503 				.voltage = 0,
504 				.dcfclk_mhz = 483,
505 				.fclk_mhz = 800,
506 				.memclk_mhz = 1600,
507 				.socclk_mhz = 0,
508 			},
509 			{
510 				.voltage = 0,
511 				.dcfclk_mhz = 602,
512 				.fclk_mhz = 1067,
513 				.memclk_mhz = 1067,
514 				.socclk_mhz = 0,
515 			},
516 			{
517 				.voltage = 0,
518 				.dcfclk_mhz = 738,
519 				.fclk_mhz = 1333,
520 				.memclk_mhz = 1600,
521 				.socclk_mhz = 0,
522 			},
523 		},
524 
525 		.num_entries = 4,
526 	},
527 
528 };
529 
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)530 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
531 {
532 	uint32_t max = 0;
533 	int i;
534 
535 	for (i = 0; i < num_clocks; ++i) {
536 		if (clocks[i] > max)
537 			max = clocks[i];
538 	}
539 
540 	return max;
541 }
542 
find_dcfclk_for_voltage(const struct vg_dpm_clocks * clock_table,unsigned int voltage)543 static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
544 		unsigned int voltage)
545 {
546 	int i;
547 
548 	for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
549 		if (clock_table->SocVoltage[i] == voltage)
550 			return clock_table->DcfClocks[i];
551 	}
552 
553 	ASSERT(0);
554 	return 0;
555 }
556 
vg_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const struct vg_dpm_clocks * clock_table)557 static void vg_clk_mgr_helper_populate_bw_params(
558 		struct clk_mgr_internal *clk_mgr,
559 		struct integrated_info *bios_info,
560 		const struct vg_dpm_clocks *clock_table)
561 {
562 	int i, j;
563 	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
564 
565 	j = -1;
566 
567 	ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
568 
569 	/* Find lowest DPM, FCLK is filled in reverse order*/
570 
571 	for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
572 		if (clock_table->DfPstateTable[i].fclk != 0) {
573 			j = i;
574 			break;
575 		}
576 	}
577 
578 	if (j == -1) {
579 		/* clock table is all 0s, just use our own hardcode */
580 		ASSERT(0);
581 		return;
582 	}
583 
584 	bw_params->clk_table.num_entries = j + 1;
585 
586 	for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) {
587 		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
588 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
589 		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
590 		bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
591 	}
592 	bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
593 	bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
594 	bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
595 	bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCFCLK_DPM_LEVELS);
596 
597 	bw_params->vram_type = bios_info->memory_type;
598 	bw_params->num_channels = bios_info->ma_channel_number;
599 
600 	for (i = 0; i < WM_SET_COUNT; i++) {
601 		bw_params->wm_table.entries[i].wm_inst = i;
602 
603 		if (i >= bw_params->clk_table.num_entries) {
604 			bw_params->wm_table.entries[i].valid = false;
605 			continue;
606 		}
607 
608 		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
609 		bw_params->wm_table.entries[i].valid = true;
610 	}
611 
612 	if (bw_params->vram_type == LpDdr4MemType) {
613 		/*
614 		 * WM set D will be re-purposed for memory retraining
615 		 */
616 		DC_FP_START();
617 		dcn21_clk_mgr_set_bw_params_wm_table(bw_params);
618 		DC_FP_END();
619 	}
620 
621 }
622 
623 /* Temporary Place holder until we can get them from fuse */
624 static struct vg_dpm_clocks dummy_clocks = {
625 		.DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
626 		.SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
627 		.SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
628 		.DfPstateTable = {
629 				{ .fclk = 400,  .memclk = 400, .voltage = 2800 },
630 				{ .fclk = 400,  .memclk = 400, .voltage = 2800 },
631 				{ .fclk = 400,  .memclk = 400, .voltage = 2800 },
632 				{ .fclk = 400,  .memclk = 400, .voltage = 2800 }
633 		}
634 };
635 
636 static struct watermarks dummy_wms = { 0 };
637 
vg_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct smu_dpm_clks * smu_dpm_clks)638 static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
639 		struct smu_dpm_clks *smu_dpm_clks)
640 {
641 	struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
642 
643 	if (!clk_mgr->smu_ver)
644 		return;
645 
646 	if (!table || smu_dpm_clks->mc_address.quad_part == 0)
647 		return;
648 
649 	memset(table, 0, sizeof(*table));
650 
651 	dcn301_smu_set_dram_addr_high(clk_mgr,
652 			smu_dpm_clks->mc_address.high_part);
653 	dcn301_smu_set_dram_addr_low(clk_mgr,
654 			smu_dpm_clks->mc_address.low_part);
655 	dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
656 }
657 
vg_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_vgh * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)658 void vg_clk_mgr_construct(
659 		struct dc_context *ctx,
660 		struct clk_mgr_vgh *clk_mgr,
661 		struct pp_smu_funcs *pp_smu,
662 		struct dccg *dccg)
663 {
664 	struct smu_dpm_clks smu_dpm_clks = { 0 };
665 	struct clk_log_info log_info = {0};
666 
667 	clk_mgr->base.base.ctx = ctx;
668 	clk_mgr->base.base.funcs = &vg_funcs;
669 
670 	clk_mgr->base.pp_smu = pp_smu;
671 
672 	clk_mgr->base.dccg = dccg;
673 	clk_mgr->base.dfs_bypass_disp_clk = 0;
674 
675 	clk_mgr->base.dprefclk_ss_percentage = 0;
676 	clk_mgr->base.dprefclk_ss_divider = 1000;
677 	clk_mgr->base.ss_on_dprefclk = false;
678 	clk_mgr->base.dfs_ref_freq_khz = 48000;
679 
680 	clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
681 				clk_mgr->base.base.ctx,
682 				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
683 				sizeof(struct watermarks),
684 				&clk_mgr->smu_wm_set.mc_address.quad_part);
685 
686 	if (!clk_mgr->smu_wm_set.wm_set) {
687 		clk_mgr->smu_wm_set.wm_set = &dummy_wms;
688 		clk_mgr->smu_wm_set.mc_address.quad_part = 0;
689 	}
690 	ASSERT(clk_mgr->smu_wm_set.wm_set);
691 
692 	smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
693 				clk_mgr->base.base.ctx,
694 				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
695 				sizeof(struct vg_dpm_clocks),
696 				&smu_dpm_clks.mc_address.quad_part);
697 
698 	if (smu_dpm_clks.dpm_clks == NULL) {
699 		smu_dpm_clks.dpm_clks = &dummy_clocks;
700 		smu_dpm_clks.mc_address.quad_part = 0;
701 	}
702 
703 	ASSERT(smu_dpm_clks.dpm_clks);
704 
705 	clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base);
706 
707 	if (clk_mgr->base.smu_ver)
708 		clk_mgr->base.smu_present = true;
709 
710 	/* TODO: Check we get what we expect during bringup */
711 	clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
712 
713 	/* in case we don't get a value from the register, use default */
714 	if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
715 		clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
716 
717 	if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
718 		vg_bw_params.wm_table = lpddr5_wm_table;
719 	} else {
720 		vg_bw_params.wm_table = ddr4_wm_table;
721 	}
722 	/* Saved clocks configured at boot for debug purposes */
723 	vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
724 
725 	clk_mgr->base.base.dprefclk_khz = 600000;
726 	dce_clock_read_ss_info(&clk_mgr->base);
727 
728 	clk_mgr->base.base.bw_params = &vg_bw_params;
729 
730 	vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
731 	if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
732 		vg_clk_mgr_helper_populate_bw_params(
733 				&clk_mgr->base,
734 				ctx->dc_bios->integrated_info,
735 				smu_dpm_clks.dpm_clks);
736 	}
737 
738 	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
739 		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
740 				smu_dpm_clks.dpm_clks);
741 }
742 
vg_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)743 void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
744 {
745 	struct clk_mgr_vgh *clk_mgr = TO_CLK_MGR_VGH(clk_mgr_int);
746 
747 	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
748 		dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
749 				clk_mgr->smu_wm_set.wm_set);
750 }
751