1 /* 2 * ARM Versatile Platform/Application Baseboard System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/sysbus.h" 13 #include "migration/vmstate.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/machines-qom.h" 16 #include "hw/net/smc91c111.h" 17 #include "net/net.h" 18 #include "system/system.h" 19 #include "hw/pci/pci.h" 20 #include "hw/i2c/i2c.h" 21 #include "hw/i2c/arm_sbcon_i2c.h" 22 #include "hw/irq.h" 23 #include "hw/boards.h" 24 #include "hw/block/flash.h" 25 #include "qemu/error-report.h" 26 #include "hw/char/pl011.h" 27 #include "hw/sd/sd.h" 28 #include "qom/object.h" 29 #include "qemu/audio.h" 30 #include "target/arm/cpu-qom.h" 31 #include "qemu/log.h" 32 33 #define VERSATILE_FLASH_ADDR 0x34000000 34 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) 35 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) 36 37 /* Primary interrupt controller. */ 38 39 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic" 40 OBJECT_DECLARE_SIMPLE_TYPE(vpb_sic_state, VERSATILE_PB_SIC) 41 42 struct vpb_sic_state { 43 SysBusDevice parent_obj; 44 45 MemoryRegion iomem; 46 uint32_t level; 47 uint32_t mask; 48 uint32_t pic_enable; 49 qemu_irq parent[32]; 50 int irq; 51 }; 52 53 static const VMStateDescription vmstate_vpb_sic = { 54 .name = "versatilepb_sic", 55 .version_id = 1, 56 .minimum_version_id = 1, 57 .fields = (const VMStateField[]) { 58 VMSTATE_UINT32(level, vpb_sic_state), 59 VMSTATE_UINT32(mask, vpb_sic_state), 60 VMSTATE_UINT32(pic_enable, vpb_sic_state), 61 VMSTATE_END_OF_LIST() 62 } 63 }; 64 65 static void vpb_sic_update(vpb_sic_state *s) 66 { 67 uint32_t flags; 68 69 flags = s->level & s->mask; 70 qemu_set_irq(s->parent[s->irq], flags != 0); 71 } 72 73 static void vpb_sic_update_pic(vpb_sic_state *s) 74 { 75 int i; 76 uint32_t mask; 77 78 for (i = 21; i <= 30; i++) { 79 mask = 1u << i; 80 if (!(s->pic_enable & mask)) 81 continue; 82 qemu_set_irq(s->parent[i], (s->level & mask) != 0); 83 } 84 } 85 86 static void vpb_sic_set_irq(void *opaque, int irq, int level) 87 { 88 vpb_sic_state *s = (vpb_sic_state *)opaque; 89 if (level) 90 s->level |= 1u << irq; 91 else 92 s->level &= ~(1u << irq); 93 if (s->pic_enable & (1u << irq)) 94 qemu_set_irq(s->parent[irq], level); 95 vpb_sic_update(s); 96 } 97 98 static uint64_t vpb_sic_read(void *opaque, hwaddr offset, 99 unsigned size) 100 { 101 vpb_sic_state *s = (vpb_sic_state *)opaque; 102 103 switch (offset >> 2) { 104 case 0: /* STATUS */ 105 return s->level & s->mask; 106 case 1: /* RAWSTAT */ 107 return s->level; 108 case 2: /* ENABLE */ 109 return s->mask; 110 case 4: /* SOFTINT */ 111 return s->level & 1; 112 case 8: /* PICENABLE */ 113 return s->pic_enable; 114 default: 115 qemu_log_mask(LOG_GUEST_ERROR, 116 "vpb_sic_read: Bad register offset 0x%x\n", (int)offset); 117 return 0; 118 } 119 } 120 121 static void vpb_sic_write(void *opaque, hwaddr offset, 122 uint64_t value, unsigned size) 123 { 124 vpb_sic_state *s = (vpb_sic_state *)opaque; 125 126 switch (offset >> 2) { 127 case 2: /* ENSET */ 128 s->mask |= value; 129 break; 130 case 3: /* ENCLR */ 131 s->mask &= ~value; 132 break; 133 case 4: /* SOFTINTSET */ 134 if (value) 135 s->mask |= 1; 136 break; 137 case 5: /* SOFTINTCLR */ 138 if (value) 139 s->mask &= ~1u; 140 break; 141 case 8: /* PICENSET */ 142 s->pic_enable |= (value & 0x7fe00000); 143 vpb_sic_update_pic(s); 144 break; 145 case 9: /* PICENCLR */ 146 s->pic_enable &= ~value; 147 vpb_sic_update_pic(s); 148 break; 149 default: 150 qemu_log_mask(LOG_GUEST_ERROR, 151 "vpb_sic_write: Bad register offset 0x%x\n", (int)offset); 152 return; 153 } 154 vpb_sic_update(s); 155 } 156 157 static const MemoryRegionOps vpb_sic_ops = { 158 .read = vpb_sic_read, 159 .write = vpb_sic_write, 160 .endianness = DEVICE_NATIVE_ENDIAN, 161 }; 162 163 static void vpb_sic_init(Object *obj) 164 { 165 DeviceState *dev = DEVICE(obj); 166 vpb_sic_state *s = VERSATILE_PB_SIC(obj); 167 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 168 int i; 169 170 qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); 171 for (i = 0; i < 32; i++) { 172 sysbus_init_irq(sbd, &s->parent[i]); 173 } 174 s->irq = 31; 175 memory_region_init_io(&s->iomem, obj, &vpb_sic_ops, s, 176 "vpb-sic", 0x1000); 177 sysbus_init_mmio(sbd, &s->iomem); 178 } 179 180 /* Board init. */ 181 182 /* The AB and PB boards both use the same core, just with different 183 peripherals and expansion busses. For now we emulate a subset of the 184 PB peripherals and just change the board ID. */ 185 186 static struct arm_boot_info versatile_binfo; 187 188 static void versatile_init(MachineState *machine, int board_id) 189 { 190 Object *cpuobj; 191 ARMCPU *cpu; 192 MemoryRegion *sysmem = get_system_memory(); 193 qemu_irq pic[32]; 194 qemu_irq sic[32]; 195 DeviceState *dev, *sysctl; 196 SysBusDevice *busdev; 197 DeviceState *pl041; 198 PCIBus *pci_bus; 199 I2CBus *i2c; 200 int n; 201 DriveInfo *dinfo; 202 203 if (machine->ram_size > 0x10000000) { 204 /* Device starting at address 0x10000000, 205 * and memory cannot overlap with devices. 206 * Refuse to run rather than behaving very confusingly. 207 */ 208 error_report("versatilepb: memory size must not exceed 256MB"); 209 exit(1); 210 } 211 212 cpuobj = object_new(machine->cpu_type); 213 214 /* By default ARM1176 CPUs have EL3 enabled. This board does not 215 * currently support EL3 so the CPU EL3 property is disabled before 216 * realization. 217 */ 218 if (object_property_find(cpuobj, "has_el3")) { 219 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 220 } 221 222 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 223 224 cpu = ARM_CPU(cpuobj); 225 226 /* ??? RAM should repeat to fill physical memory space. */ 227 /* SDRAM at address zero. */ 228 memory_region_add_subregion(sysmem, 0, machine->ram); 229 230 sysctl = qdev_new("realview_sysctl"); 231 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 232 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 233 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 234 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 235 236 dev = sysbus_create_varargs("pl190", 0x10140000, 237 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 238 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 239 NULL); 240 for (n = 0; n < 32; n++) { 241 pic[n] = qdev_get_gpio_in(dev, n); 242 } 243 dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); 244 for (n = 0; n < 32; n++) { 245 sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); 246 sic[n] = qdev_get_gpio_in(dev, n); 247 } 248 249 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 250 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 251 252 dev = qdev_new("versatile_pci"); 253 busdev = SYS_BUS_DEVICE(dev); 254 sysbus_realize_and_unref(busdev, &error_fatal); 255 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 256 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 257 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ 258 sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ 259 sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ 260 sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ 261 sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ 262 sysbus_connect_irq(busdev, 0, sic[27]); 263 sysbus_connect_irq(busdev, 1, sic[28]); 264 sysbus_connect_irq(busdev, 2, sic[29]); 265 sysbus_connect_irq(busdev, 3, sic[30]); 266 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); 267 268 if (qemu_find_nic_info("smc91c111", true, NULL)) { 269 smc91c111_init(0x10010000, sic[25]); 270 } 271 pci_init_nic_devices(pci_bus, "rtl8139"); 272 273 if (machine_usb(machine)) { 274 pci_create_simple(pci_bus, -1, "pci-ohci"); 275 } 276 n = drive_get_max_bus(IF_SCSI); 277 while (n >= 0) { 278 dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); 279 lsi53c8xx_handle_legacy_cmdline(dev); 280 n--; 281 } 282 283 pl011_create(0x101f1000, pic[12], serial_hd(0)); 284 pl011_create(0x101f2000, pic[13], serial_hd(1)); 285 pl011_create(0x101f3000, pic[14], serial_hd(2)); 286 pl011_create(0x10009000, sic[6], serial_hd(3)); 287 288 dev = qdev_new("pl080"); 289 object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), 290 &error_fatal); 291 busdev = SYS_BUS_DEVICE(dev); 292 sysbus_realize_and_unref(busdev, &error_fatal); 293 sysbus_mmio_map(busdev, 0, 0x10130000); 294 sysbus_connect_irq(busdev, 0, pic[17]); 295 296 sysbus_create_simple("sp804", 0x101e2000, pic[4]); 297 sysbus_create_simple("sp804", 0x101e3000, pic[5]); 298 299 sysbus_create_simple("pl061", 0x101e4000, pic[6]); 300 sysbus_create_simple("pl061", 0x101e5000, pic[7]); 301 sysbus_create_simple("pl061", 0x101e6000, pic[8]); 302 sysbus_create_simple("pl061", 0x101e7000, pic[9]); 303 304 /* The versatile/PB actually has a modified Color LCD controller 305 that includes hardware cursor support from the PL111. */ 306 dev = qdev_new("pl110_versatile"); 307 object_property_set_link(OBJECT(dev), "framebuffer-memory", 308 OBJECT(sysmem), &error_fatal); 309 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 310 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10120000); 311 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[16]); 312 313 /* Wire up the mux control signals from the SYS_CLCD register */ 314 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); 315 316 dev = sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); 317 dinfo = drive_get(IF_SD, 0, 0); 318 if (dinfo) { 319 DeviceState *card; 320 321 card = qdev_new(TYPE_SD_CARD); 322 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 323 &error_fatal); 324 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 325 &error_fatal); 326 } 327 328 dev = sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); 329 dinfo = drive_get(IF_SD, 0, 1); 330 if (dinfo) { 331 DeviceState *card; 332 333 card = qdev_new(TYPE_SD_CARD); 334 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 335 &error_fatal); 336 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 337 &error_fatal); 338 } 339 340 /* Add PL031 Real Time Clock. */ 341 sysbus_create_simple("pl031", 0x101e8000, pic[10]); 342 343 dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL); 344 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 345 i2c_slave_create_simple(i2c, "ds1338", 0x68); 346 347 /* Add PL041 AACI Interface to the LM4549 codec */ 348 pl041 = qdev_new("pl041"); 349 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 350 if (machine->audiodev) { 351 qdev_prop_set_string(pl041, "audiodev", machine->audiodev); 352 } 353 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 354 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 355 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 356 357 /* Memory map for Versatile/PB: */ 358 /* 0x10000000 System registers. */ 359 /* 0x10001000 PCI controller config registers. */ 360 /* 0x10002000 Serial bus interface. */ 361 /* 0x10003000 Secondary interrupt controller. */ 362 /* 0x10004000 AACI (audio). */ 363 /* 0x10005000 MMCI0. */ 364 /* 0x10006000 KMI0 (keyboard). */ 365 /* 0x10007000 KMI1 (mouse). */ 366 /* 0x10008000 Character LCD Interface. */ 367 /* 0x10009000 UART3. */ 368 /* 0x1000a000 Smart card 1. */ 369 /* 0x1000b000 MMCI1. */ 370 /* 0x10010000 Ethernet. */ 371 /* 0x10020000 USB. */ 372 /* 0x10100000 SSMC. */ 373 /* 0x10110000 MPMC. */ 374 /* 0x10120000 CLCD Controller. */ 375 /* 0x10130000 DMA Controller. */ 376 /* 0x10140000 Vectored interrupt controller. */ 377 /* 0x101d0000 AHB Monitor Interface. */ 378 /* 0x101e0000 System Controller. */ 379 /* 0x101e1000 Watchdog Interface. */ 380 /* 0x101e2000 Timer 0/1. */ 381 /* 0x101e3000 Timer 2/3. */ 382 /* 0x101e4000 GPIO port 0. */ 383 /* 0x101e5000 GPIO port 1. */ 384 /* 0x101e6000 GPIO port 2. */ 385 /* 0x101e7000 GPIO port 3. */ 386 /* 0x101e8000 RTC. */ 387 /* 0x101f0000 Smart card 0. */ 388 /* 0x101f1000 UART0. */ 389 /* 0x101f2000 UART1. */ 390 /* 0x101f3000 UART2. */ 391 /* 0x101f4000 SSPI. */ 392 /* 0x34000000 NOR Flash */ 393 394 dinfo = drive_get(IF_PFLASH, 0, 0); 395 pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", 396 VERSATILE_FLASH_SIZE, 397 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 398 VERSATILE_FLASH_SECT_SIZE, 399 4, 0x0089, 0x0018, 0x0000, 0x0, 0); 400 401 versatile_binfo.ram_size = machine->ram_size; 402 versatile_binfo.board_id = board_id; 403 arm_load_kernel(cpu, machine, &versatile_binfo); 404 } 405 406 static void vpb_init(MachineState *machine) 407 { 408 versatile_init(machine, 0x183); 409 } 410 411 static void vab_init(MachineState *machine) 412 { 413 versatile_init(machine, 0x25e); 414 } 415 416 static void versatilepb_class_init(ObjectClass *oc, const void *data) 417 { 418 MachineClass *mc = MACHINE_CLASS(oc); 419 420 mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; 421 mc->init = vpb_init; 422 mc->block_default_type = IF_SCSI; 423 mc->ignore_memory_transaction_failures = true; 424 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 425 mc->default_ram_id = "versatile.ram"; 426 mc->auto_create_sdcard = true; 427 428 machine_add_audiodev_property(mc); 429 } 430 431 static const TypeInfo versatilepb_type = { 432 .name = MACHINE_TYPE_NAME("versatilepb"), 433 .parent = TYPE_MACHINE, 434 .class_init = versatilepb_class_init, 435 .interfaces = arm_machine_interfaces, 436 }; 437 438 static void versatileab_class_init(ObjectClass *oc, const void *data) 439 { 440 MachineClass *mc = MACHINE_CLASS(oc); 441 442 mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; 443 mc->init = vab_init; 444 mc->block_default_type = IF_SCSI; 445 mc->ignore_memory_transaction_failures = true; 446 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 447 mc->default_ram_id = "versatile.ram"; 448 mc->auto_create_sdcard = true; 449 450 machine_add_audiodev_property(mc); 451 } 452 453 static const TypeInfo versatileab_type = { 454 .name = MACHINE_TYPE_NAME("versatileab"), 455 .parent = TYPE_MACHINE, 456 .class_init = versatileab_class_init, 457 .interfaces = arm_machine_interfaces, 458 }; 459 460 static void versatile_machine_init(void) 461 { 462 type_register_static(&versatilepb_type); 463 type_register_static(&versatileab_type); 464 } 465 466 type_init(versatile_machine_init) 467 468 static void vpb_sic_class_init(ObjectClass *klass, const void *data) 469 { 470 DeviceClass *dc = DEVICE_CLASS(klass); 471 472 dc->vmsd = &vmstate_vpb_sic; 473 } 474 475 static const TypeInfo vpb_sic_info = { 476 .name = TYPE_VERSATILE_PB_SIC, 477 .parent = TYPE_SYS_BUS_DEVICE, 478 .instance_size = sizeof(vpb_sic_state), 479 .instance_init = vpb_sic_init, 480 .class_init = vpb_sic_class_init, 481 }; 482 483 static void versatilepb_register_types(void) 484 { 485 type_register_static(&vpb_sic_info); 486 } 487 488 type_init(versatilepb_register_types) 489