1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/pci.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28 #include "soc15.h"
29
30 #include "oss/osssys_4_2_0_offset.h"
31 #include "oss/osssys_4_2_0_sh_mask.h"
32
33 #include "soc15_common.h"
34 #include "vega20_ih.h"
35
36 #define MAX_REARM_RETRY 10
37
38 #define mmIH_CHICKEN_ALDEBARAN 0x18d
39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40
41 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea
42 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0
43 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10
44 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L
45
46 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
47
48 /**
49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
50 *
51 * @adev: amdgpu_device pointer
52 *
53 * Initialize register offset ih rings (VEGA20).
54 */
vega20_ih_init_register_offset(struct amdgpu_device * adev)55 static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
56 {
57 struct amdgpu_ih_regs *ih_regs;
58
59 if (adev->irq.ih.ring_size) {
60 ih_regs = &adev->irq.ih.ih_regs;
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
70 }
71
72 if (adev->irq.ih1.ring_size) {
73 ih_regs = &adev->irq.ih1.ih_regs;
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
81 }
82
83 if (adev->irq.ih2.ring_size) {
84 ih_regs = &adev->irq.ih2.ih_regs;
85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
92 }
93 }
94
95 /**
96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
97 *
98 * @adev: amdgpu_device pointer
99 * @ih: amdgpu_ih_ring pointer
100 * @enable: true - enable the interrupts, false - disable the interrupts
101 *
102 * Toggle the interrupt ring buffer (VEGA20)
103 */
vega20_ih_toggle_ring_interrupts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,bool enable)104 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
105 struct amdgpu_ih_ring *ih,
106 bool enable)
107 {
108 struct amdgpu_ih_regs *ih_regs;
109 uint32_t tmp;
110
111 ih_regs = &ih->ih_regs;
112
113 tmp = RREG32(ih_regs->ih_rb_cntl);
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
116
117 /* enable_intr field is only valid in ring0 */
118 if (ih == &adev->irq.ih)
119 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
120 if (amdgpu_sriov_vf(adev)) {
121 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
122 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
123 return -ETIMEDOUT;
124 }
125 } else {
126 WREG32(ih_regs->ih_rb_cntl, tmp);
127 }
128
129 if (enable) {
130 ih->enabled = true;
131 } else {
132 /* set rptr, wptr to 0 */
133 WREG32(ih_regs->ih_rb_rptr, 0);
134 WREG32(ih_regs->ih_rb_wptr, 0);
135 ih->enabled = false;
136 ih->rptr = 0;
137 }
138
139 return 0;
140 }
141
142 /**
143 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
144 *
145 * @adev: amdgpu_device pointer
146 * @enable: enable or disable interrupt ring buffers
147 *
148 * Toggle all the available interrupt ring buffers (VEGA20).
149 */
vega20_ih_toggle_interrupts(struct amdgpu_device * adev,bool enable)150 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
151 {
152 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
153 int i;
154 int r;
155
156 for (i = 0; i < ARRAY_SIZE(ih); i++) {
157 if (ih[i]->ring_size) {
158 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
159 if (r)
160 return r;
161 }
162 }
163
164 return 0;
165 }
166
vega20_ih_rb_cntl(struct amdgpu_ih_ring * ih,uint32_t ih_rb_cntl)167 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
168 {
169 int rb_bufsz = order_base_2(ih->ring_size / 4);
170
171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
172 MC_SPACE, ih->use_bus_addr ? 1 : 4);
173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
174 WPTR_OVERFLOW_CLEAR, 1);
175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
176 WPTR_OVERFLOW_ENABLE, 1);
177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
178 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
179 * value is written to memory
180 */
181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
182 WPTR_WRITEBACK_ENABLE, 1);
183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
185 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
186
187 return ih_rb_cntl;
188 }
189
vega20_ih_doorbell_rptr(struct amdgpu_ih_ring * ih)190 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
191 {
192 u32 ih_doorbell_rtpr = 0;
193
194 if (ih->use_doorbell) {
195 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
196 IH_DOORBELL_RPTR, OFFSET,
197 ih->doorbell_index);
198 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
199 IH_DOORBELL_RPTR,
200 ENABLE, 1);
201 } else {
202 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
203 IH_DOORBELL_RPTR,
204 ENABLE, 0);
205 }
206 return ih_doorbell_rtpr;
207 }
208
209 /**
210 * vega20_ih_enable_ring - enable an ih ring buffer
211 *
212 * @adev: amdgpu_device pointer
213 * @ih: amdgpu_ih_ring pointer
214 *
215 * Enable an ih ring buffer (VEGA20)
216 */
vega20_ih_enable_ring(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)217 static int vega20_ih_enable_ring(struct amdgpu_device *adev,
218 struct amdgpu_ih_ring *ih)
219 {
220 struct amdgpu_ih_regs *ih_regs;
221 uint32_t tmp;
222
223 ih_regs = &ih->ih_regs;
224
225 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
226 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
227 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
228
229 tmp = RREG32(ih_regs->ih_rb_cntl);
230 tmp = vega20_ih_rb_cntl(ih, tmp);
231 if (ih == &adev->irq.ih)
232 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
233 if (ih == &adev->irq.ih1)
234 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
235 if (amdgpu_sriov_vf(adev)) {
236 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
237 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
238 return -ETIMEDOUT;
239 }
240 } else {
241 WREG32(ih_regs->ih_rb_cntl, tmp);
242 }
243
244 if (ih == &adev->irq.ih) {
245 /* set the ih ring 0 writeback address whether it's enabled or not */
246 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
247 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
248 }
249
250 /* set rptr, wptr to 0 */
251 WREG32(ih_regs->ih_rb_wptr, 0);
252 WREG32(ih_regs->ih_rb_rptr, 0);
253
254 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
255
256 return 0;
257 }
258
vega20_setup_retry_doorbell(u32 doorbell_index)259 static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
260 {
261 u32 val = 0;
262
263 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
264 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
265
266 return val;
267 }
268
269 /**
270 * vega20_ih_irq_init - init and enable the interrupt ring
271 *
272 * @adev: amdgpu_device pointer
273 *
274 * Allocate a ring buffer for the interrupt controller,
275 * enable the RLC, disable interrupts, enable the IH
276 * ring buffer and enable it (VI).
277 * Called at device load and reume.
278 * Returns 0 for success, errors for failure.
279 */
vega20_ih_irq_init(struct amdgpu_device * adev)280 static int vega20_ih_irq_init(struct amdgpu_device *adev)
281 {
282 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
283 u32 ih_chicken;
284 int ret;
285 int i;
286
287 /* disable irqs */
288 ret = vega20_ih_toggle_interrupts(adev, false);
289 if (ret)
290 return ret;
291
292 adev->nbio.funcs->ih_control(adev);
293
294 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) &&
295 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
296 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
297 if (adev->irq.ih.use_bus_addr) {
298 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
299 MC_SPACE_GPA_ENABLE, 1);
300 }
301 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
302 }
303
304 /* psp firmware won't program IH_CHICKEN for aldebaran
305 * driver needs to program it properly according to
306 * MC_SPACE type in IH_RB_CNTL */
307 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) ||
308 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) {
309 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
310 if (adev->irq.ih.use_bus_addr) {
311 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
312 MC_SPACE_GPA_ENABLE, 1);
313 }
314 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
315 }
316
317 for (i = 0; i < ARRAY_SIZE(ih); i++) {
318 if (ih[i]->ring_size) {
319 ret = vega20_ih_enable_ring(adev, ih[i]);
320 if (ret)
321 return ret;
322 }
323 }
324
325 if (!amdgpu_sriov_vf(adev))
326 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
327 adev->irq.ih.doorbell_index);
328
329 pci_set_master(adev->pdev);
330
331 /* Allocate the doorbell for IH Retry CAM */
332 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
333 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
334 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
335
336 /* Enable IH Retry CAM */
337 if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0) ||
338 adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))
339 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
340 ENABLE, 1);
341 else
342 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
343
344 adev->irq.retry_cam_enabled = true;
345
346 /* enable interrupts */
347 ret = vega20_ih_toggle_interrupts(adev, true);
348 if (ret)
349 return ret;
350
351 if (adev->irq.ih_soft.ring_size)
352 adev->irq.ih_soft.enabled = true;
353
354 return 0;
355 }
356
357 /**
358 * vega20_ih_irq_disable - disable interrupts
359 *
360 * @adev: amdgpu_device pointer
361 *
362 * Disable interrupts on the hw (VEGA20).
363 */
vega20_ih_irq_disable(struct amdgpu_device * adev)364 static void vega20_ih_irq_disable(struct amdgpu_device *adev)
365 {
366 vega20_ih_toggle_interrupts(adev, false);
367
368 /* Wait and acknowledge irq */
369 mdelay(1);
370 }
371
372 /**
373 * vega20_ih_get_wptr - get the IH ring buffer wptr
374 *
375 * @adev: amdgpu_device pointer
376 * @ih: amdgpu_ih_ring pointer
377 *
378 * Get the IH ring buffer wptr from either the register
379 * or the writeback memory buffer (VEGA20). Also check for
380 * ring buffer overflow and deal with it.
381 * Returns the value of the wptr.
382 */
vega20_ih_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)383 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
384 struct amdgpu_ih_ring *ih)
385 {
386 u32 wptr, tmp;
387 struct amdgpu_ih_regs *ih_regs;
388
389 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
390 /* Only ring0 supports writeback. On other rings fall back
391 * to register-based code with overflow checking below.
392 * ih_soft ring doesn't have any backing hardware registers,
393 * update wptr and return.
394 */
395 wptr = le32_to_cpu(*ih->wptr_cpu);
396
397 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
398 goto out;
399 }
400
401 ih_regs = &ih->ih_regs;
402
403 /* Double check that the overflow wasn't already cleared. */
404 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
405 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
406 goto out;
407
408 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
409
410 /* When a ring buffer overflow happen start parsing interrupt
411 * from the last not overwritten vector (wptr + 32). Hopefully
412 * this should allow us to catchup.
413 */
414 tmp = (wptr + 32) & ih->ptr_mask;
415 dev_warn(adev->dev, "IH ring buffer overflow "
416 "(0x%08X, 0x%08X, 0x%08X)\n",
417 wptr, ih->rptr, tmp);
418 ih->rptr = tmp;
419
420 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
421 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
422 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
423
424 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
425 * can be detected.
426 */
427 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
428 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
429
430 out:
431 return (wptr & ih->ptr_mask);
432 }
433
434 /**
435 * vega20_ih_irq_rearm - rearm IRQ if lost
436 *
437 * @adev: amdgpu_device pointer
438 * @ih: amdgpu_ih_ring pointer
439 *
440 */
vega20_ih_irq_rearm(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)441 static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
442 struct amdgpu_ih_ring *ih)
443 {
444 uint32_t v = 0;
445 uint32_t i = 0;
446 struct amdgpu_ih_regs *ih_regs;
447
448 ih_regs = &ih->ih_regs;
449
450 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
451 for (i = 0; i < MAX_REARM_RETRY; i++) {
452 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
453 if ((v < ih->ring_size) && (v != ih->rptr))
454 WDOORBELL32(ih->doorbell_index, ih->rptr);
455 else
456 break;
457 }
458 }
459
460 /**
461 * vega20_ih_set_rptr - set the IH ring buffer rptr
462 *
463 * @adev: amdgpu_device pointer
464 * @ih: amdgpu_ih_ring pointer
465 *
466 * Set the IH ring buffer rptr.
467 */
vega20_ih_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)468 static void vega20_ih_set_rptr(struct amdgpu_device *adev,
469 struct amdgpu_ih_ring *ih)
470 {
471 struct amdgpu_ih_regs *ih_regs;
472
473 if (ih == &adev->irq.ih_soft)
474 return;
475
476 if (ih->use_doorbell) {
477 /* XXX check if swapping is necessary on BE */
478 *ih->rptr_cpu = ih->rptr;
479 WDOORBELL32(ih->doorbell_index, ih->rptr);
480
481 if (amdgpu_sriov_vf(adev))
482 vega20_ih_irq_rearm(adev, ih);
483 } else {
484 ih_regs = &ih->ih_regs;
485 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
486 }
487 }
488
489 /**
490 * vega20_ih_self_irq - dispatch work for ring 1 and 2
491 *
492 * @adev: amdgpu_device pointer
493 * @source: irq source
494 * @entry: IV with WPTR update
495 *
496 * Update the WPTR from the IV and schedule work to handle the entries.
497 */
vega20_ih_self_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)498 static int vega20_ih_self_irq(struct amdgpu_device *adev,
499 struct amdgpu_irq_src *source,
500 struct amdgpu_iv_entry *entry)
501 {
502 switch (entry->ring_id) {
503 case 1:
504 schedule_work(&adev->irq.ih1_work);
505 break;
506 case 2:
507 schedule_work(&adev->irq.ih2_work);
508 break;
509 default:
510 break;
511 }
512 return 0;
513 }
514
515 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
516 .process = vega20_ih_self_irq,
517 };
518
vega20_ih_set_self_irq_funcs(struct amdgpu_device * adev)519 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
520 {
521 adev->irq.self_irq.num_types = 0;
522 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
523 }
524
vega20_ih_early_init(void * handle)525 static int vega20_ih_early_init(void *handle)
526 {
527 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
528
529 vega20_ih_set_interrupt_funcs(adev);
530 vega20_ih_set_self_irq_funcs(adev);
531 return 0;
532 }
533
vega20_ih_sw_init(void * handle)534 static int vega20_ih_sw_init(void *handle)
535 {
536 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
537 bool use_bus_addr = true;
538 int r;
539
540 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
541 &adev->irq.self_irq);
542 if (r)
543 return r;
544
545 if ((adev->flags & AMD_IS_APU) &&
546 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2)))
547 use_bus_addr = false;
548
549 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
550 if (r)
551 return r;
552
553 adev->irq.ih.use_doorbell = true;
554 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
555
556 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
557 if (r)
558 return r;
559
560 adev->irq.ih1.use_doorbell = true;
561 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
562
563 if (adev->ip_versions[OSSSYS_HWIP][0] != IP_VERSION(4, 4, 2)) {
564 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
565 if (r)
566 return r;
567
568 adev->irq.ih2.use_doorbell = true;
569 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
570 }
571
572 /* initialize ih control registers offset */
573 vega20_ih_init_register_offset(adev);
574
575 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
576 if (r)
577 return r;
578
579 r = amdgpu_irq_init(adev);
580
581 return r;
582 }
583
vega20_ih_sw_fini(void * handle)584 static int vega20_ih_sw_fini(void *handle)
585 {
586 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
587
588 amdgpu_irq_fini_sw(adev);
589
590 return 0;
591 }
592
vega20_ih_hw_init(void * handle)593 static int vega20_ih_hw_init(void *handle)
594 {
595 int r;
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 r = vega20_ih_irq_init(adev);
599 if (r)
600 return r;
601
602 return 0;
603 }
604
vega20_ih_hw_fini(void * handle)605 static int vega20_ih_hw_fini(void *handle)
606 {
607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608
609 vega20_ih_irq_disable(adev);
610
611 return 0;
612 }
613
vega20_ih_suspend(void * handle)614 static int vega20_ih_suspend(void *handle)
615 {
616 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
617
618 return vega20_ih_hw_fini(adev);
619 }
620
vega20_ih_resume(void * handle)621 static int vega20_ih_resume(void *handle)
622 {
623 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
624
625 return vega20_ih_hw_init(adev);
626 }
627
vega20_ih_is_idle(void * handle)628 static bool vega20_ih_is_idle(void *handle)
629 {
630 /* todo */
631 return true;
632 }
633
vega20_ih_wait_for_idle(void * handle)634 static int vega20_ih_wait_for_idle(void *handle)
635 {
636 /* todo */
637 return -ETIMEDOUT;
638 }
639
vega20_ih_soft_reset(void * handle)640 static int vega20_ih_soft_reset(void *handle)
641 {
642 /* todo */
643
644 return 0;
645 }
646
vega20_ih_update_clockgating_state(struct amdgpu_device * adev,bool enable)647 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
648 bool enable)
649 {
650 uint32_t data, def, field_val;
651
652 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
653 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
654 field_val = enable ? 0 : 1;
655 data = REG_SET_FIELD(data, IH_CLK_CTRL,
656 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
657 data = REG_SET_FIELD(data, IH_CLK_CTRL,
658 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
659 data = REG_SET_FIELD(data, IH_CLK_CTRL,
660 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
661 data = REG_SET_FIELD(data, IH_CLK_CTRL,
662 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
663 data = REG_SET_FIELD(data, IH_CLK_CTRL,
664 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
665 data = REG_SET_FIELD(data, IH_CLK_CTRL,
666 DYN_CLK_SOFT_OVERRIDE, field_val);
667 data = REG_SET_FIELD(data, IH_CLK_CTRL,
668 REG_CLK_SOFT_OVERRIDE, field_val);
669 if (def != data)
670 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
671 }
672 }
673
vega20_ih_set_clockgating_state(void * handle,enum amd_clockgating_state state)674 static int vega20_ih_set_clockgating_state(void *handle,
675 enum amd_clockgating_state state)
676 {
677 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
678
679 vega20_ih_update_clockgating_state(adev,
680 state == AMD_CG_STATE_GATE);
681 return 0;
682
683 }
684
vega20_ih_set_powergating_state(void * handle,enum amd_powergating_state state)685 static int vega20_ih_set_powergating_state(void *handle,
686 enum amd_powergating_state state)
687 {
688 return 0;
689 }
690
691 const struct amd_ip_funcs vega20_ih_ip_funcs = {
692 .name = "vega20_ih",
693 .early_init = vega20_ih_early_init,
694 .late_init = NULL,
695 .sw_init = vega20_ih_sw_init,
696 .sw_fini = vega20_ih_sw_fini,
697 .hw_init = vega20_ih_hw_init,
698 .hw_fini = vega20_ih_hw_fini,
699 .suspend = vega20_ih_suspend,
700 .resume = vega20_ih_resume,
701 .is_idle = vega20_ih_is_idle,
702 .wait_for_idle = vega20_ih_wait_for_idle,
703 .soft_reset = vega20_ih_soft_reset,
704 .set_clockgating_state = vega20_ih_set_clockgating_state,
705 .set_powergating_state = vega20_ih_set_powergating_state,
706 };
707
708 static const struct amdgpu_ih_funcs vega20_ih_funcs = {
709 .get_wptr = vega20_ih_get_wptr,
710 .decode_iv = amdgpu_ih_decode_iv_helper,
711 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
712 .set_rptr = vega20_ih_set_rptr
713 };
714
vega20_ih_set_interrupt_funcs(struct amdgpu_device * adev)715 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
716 {
717 adev->irq.ih_funcs = &vega20_ih_funcs;
718 }
719
720 const struct amdgpu_ip_block_version vega20_ih_ip_block = {
721 .type = AMD_IP_BLOCK_TYPE_IH,
722 .major = 4,
723 .minor = 2,
724 .rev = 0,
725 .funcs = &vega20_ih_ip_funcs,
726 };
727