1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/slab.h>
27 
28 #include "hwmgr.h"
29 #include "amd_powerplay.h"
30 #include "vega12_smumgr.h"
31 #include "hardwaremanager.h"
32 #include "ppatomfwctrl.h"
33 #include "atomfirmware.h"
34 #include "cgs_common.h"
35 #include "vega12_inc.h"
36 #include "pppcielanes.h"
37 #include "vega12_hwmgr.h"
38 #include "vega12_processpptables.h"
39 #include "vega12_pptable.h"
40 #include "vega12_thermal.h"
41 #include "vega12_ppsmc.h"
42 #include "pp_debug.h"
43 #include "amd_pcie_helpers.h"
44 #include "ppinterrupt.h"
45 #include "pp_overdriver.h"
46 #include "pp_thermal.h"
47 #include "vega12_baco.h"
48 
49 #define smnPCIE_LC_SPEED_CNTL			0x11140290
50 #define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
51 
52 #define LINK_WIDTH_MAX				6
53 #define LINK_SPEED_MAX				3
54 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
55 static const int link_speed[] = {25, 50, 80, 160};
56 
57 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
58 		enum pp_clock_type type, uint32_t mask);
59 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
60 		uint32_t *clock,
61 		PPCLK_e clock_select,
62 		bool max);
63 
vega12_set_default_registry_data(struct pp_hwmgr * hwmgr)64 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
65 {
66 	struct vega12_hwmgr *data =
67 			(struct vega12_hwmgr *)(hwmgr->backend);
68 
69 	data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
70 	data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
71 	data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
72 	data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
73 	data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
74 
75 	data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
76 	data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
77 	data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
78 	data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
79 	data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
80 	data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
81 	data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
82 	data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
83 	data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
84 	data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
85 	data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
86 	data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
87 	data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
88 
89 	data->registry_data.disallowed_features = 0x0;
90 	data->registry_data.od_state_in_dc_support = 0;
91 	data->registry_data.thermal_support = 1;
92 	data->registry_data.skip_baco_hardware = 0;
93 
94 	data->registry_data.log_avfs_param = 0;
95 	data->registry_data.sclk_throttle_low_notification = 1;
96 	data->registry_data.force_dpm_high = 0;
97 	data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
98 
99 	data->registry_data.didt_support = 0;
100 	if (data->registry_data.didt_support) {
101 		data->registry_data.didt_mode = 6;
102 		data->registry_data.sq_ramping_support = 1;
103 		data->registry_data.db_ramping_support = 0;
104 		data->registry_data.td_ramping_support = 0;
105 		data->registry_data.tcp_ramping_support = 0;
106 		data->registry_data.dbr_ramping_support = 0;
107 		data->registry_data.edc_didt_support = 1;
108 		data->registry_data.gc_didt_support = 0;
109 		data->registry_data.psm_didt_support = 0;
110 	}
111 
112 	data->registry_data.pcie_lane_override = 0xff;
113 	data->registry_data.pcie_speed_override = 0xff;
114 	data->registry_data.pcie_clock_override = 0xffffffff;
115 	data->registry_data.regulator_hot_gpio_support = 1;
116 	data->registry_data.ac_dc_switch_gpio_support = 0;
117 	data->registry_data.quick_transition_support = 0;
118 	data->registry_data.zrpm_start_temp = 0xffff;
119 	data->registry_data.zrpm_stop_temp = 0xffff;
120 	data->registry_data.odn_feature_enable = 1;
121 	data->registry_data.disable_water_mark = 0;
122 	data->registry_data.disable_pp_tuning = 0;
123 	data->registry_data.disable_xlpp_tuning = 0;
124 	data->registry_data.disable_workload_policy = 0;
125 	data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
126 	data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
127 	data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
128 	data->registry_data.force_workload_policy_mask = 0;
129 	data->registry_data.disable_3d_fs_detection = 0;
130 	data->registry_data.fps_support = 1;
131 	data->registry_data.disable_auto_wattman = 1;
132 	data->registry_data.auto_wattman_debug = 0;
133 	data->registry_data.auto_wattman_sample_period = 100;
134 	data->registry_data.auto_wattman_threshold = 50;
135 	data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
136 }
137 
vega12_set_features_platform_caps(struct pp_hwmgr * hwmgr)138 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
139 {
140 	struct vega12_hwmgr *data =
141 			(struct vega12_hwmgr *)(hwmgr->backend);
142 	struct amdgpu_device *adev = hwmgr->adev;
143 
144 	if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
145 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
146 				PHM_PlatformCaps_ControlVDDCI);
147 
148 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
149 			PHM_PlatformCaps_TablelessHardwareInterface);
150 
151 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
152 			PHM_PlatformCaps_EnableSMU7ThermalManagement);
153 
154 	if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
155 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
156 				PHM_PlatformCaps_UVDPowerGating);
157 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 				PHM_PlatformCaps_UVDDynamicPowerGating);
159 	}
160 
161 	if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
162 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
163 				PHM_PlatformCaps_VCEPowerGating);
164 
165 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
166 			PHM_PlatformCaps_UnTabledHardwareInterface);
167 
168 	if (data->registry_data.odn_feature_enable)
169 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
170 				PHM_PlatformCaps_ODNinACSupport);
171 	else {
172 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 				PHM_PlatformCaps_OD6inACSupport);
174 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
175 				PHM_PlatformCaps_OD6PlusinACSupport);
176 	}
177 
178 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
179 			PHM_PlatformCaps_ActivityReporting);
180 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
181 			PHM_PlatformCaps_FanSpeedInTableIsRPM);
182 
183 	if (data->registry_data.od_state_in_dc_support) {
184 		if (data->registry_data.odn_feature_enable)
185 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
186 					PHM_PlatformCaps_ODNinDCSupport);
187 		else {
188 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
189 					PHM_PlatformCaps_OD6inDCSupport);
190 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
191 					PHM_PlatformCaps_OD6PlusinDCSupport);
192 		}
193 	}
194 
195 	if (data->registry_data.thermal_support
196 			&& data->registry_data.fuzzy_fan_control_support
197 			&& hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
198 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
199 				PHM_PlatformCaps_ODFuzzyFanControlSupport);
200 
201 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
202 				PHM_PlatformCaps_DynamicPowerManagement);
203 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 			PHM_PlatformCaps_SMC);
205 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
206 			PHM_PlatformCaps_ThermalPolicyDelay);
207 
208 	if (data->registry_data.force_dpm_high)
209 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
210 				PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
211 
212 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
213 			PHM_PlatformCaps_DynamicUVDState);
214 
215 	if (data->registry_data.sclk_throttle_low_notification)
216 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
217 				PHM_PlatformCaps_SclkThrottleLowNotification);
218 
219 	/* power tune caps */
220 	/* assume disabled */
221 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
222 			PHM_PlatformCaps_PowerContainment);
223 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
224 			PHM_PlatformCaps_DiDtSupport);
225 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
226 			PHM_PlatformCaps_SQRamping);
227 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
228 			PHM_PlatformCaps_DBRamping);
229 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
230 			PHM_PlatformCaps_TDRamping);
231 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
232 			PHM_PlatformCaps_TCPRamping);
233 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
234 			PHM_PlatformCaps_DBRRamping);
235 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
236 			PHM_PlatformCaps_DiDtEDCEnable);
237 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
238 			PHM_PlatformCaps_GCEDC);
239 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
240 			PHM_PlatformCaps_PSM);
241 
242 	if (data->registry_data.didt_support) {
243 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
244 		if (data->registry_data.sq_ramping_support)
245 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
246 		if (data->registry_data.db_ramping_support)
247 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
248 		if (data->registry_data.td_ramping_support)
249 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
250 		if (data->registry_data.tcp_ramping_support)
251 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
252 		if (data->registry_data.dbr_ramping_support)
253 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
254 		if (data->registry_data.edc_didt_support)
255 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
256 		if (data->registry_data.gc_didt_support)
257 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
258 		if (data->registry_data.psm_didt_support)
259 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
260 	}
261 
262 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 			PHM_PlatformCaps_RegulatorHot);
264 
265 	if (data->registry_data.ac_dc_switch_gpio_support) {
266 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
267 				PHM_PlatformCaps_AutomaticDCTransition);
268 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
269 				PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
270 	}
271 
272 	if (data->registry_data.quick_transition_support) {
273 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
274 				PHM_PlatformCaps_AutomaticDCTransition);
275 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
276 				PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
277 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
278 				PHM_PlatformCaps_Falcon_QuickTransition);
279 	}
280 
281 	if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
282 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
283 				PHM_PlatformCaps_LowestUclkReservedForUlv);
284 		if (data->lowest_uclk_reserved_for_ulv == 1)
285 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
286 					PHM_PlatformCaps_LowestUclkReservedForUlv);
287 	}
288 
289 	if (data->registry_data.custom_fan_support)
290 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 				PHM_PlatformCaps_CustomFanControlSupport);
292 
293 	return 0;
294 }
295 
vega12_init_dpm_defaults(struct pp_hwmgr * hwmgr)296 static int vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
297 {
298 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
299 	struct amdgpu_device *adev = hwmgr->adev;
300 	uint32_t top32, bottom32;
301 	int i, ret;
302 
303 	data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
304 			FEATURE_DPM_PREFETCHER_BIT;
305 	data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
306 			FEATURE_DPM_GFXCLK_BIT;
307 	data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
308 			FEATURE_DPM_UCLK_BIT;
309 	data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
310 			FEATURE_DPM_SOCCLK_BIT;
311 	data->smu_features[GNLD_DPM_UVD].smu_feature_id =
312 			FEATURE_DPM_UVD_BIT;
313 	data->smu_features[GNLD_DPM_VCE].smu_feature_id =
314 			FEATURE_DPM_VCE_BIT;
315 	data->smu_features[GNLD_ULV].smu_feature_id =
316 			FEATURE_ULV_BIT;
317 	data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
318 			FEATURE_DPM_MP0CLK_BIT;
319 	data->smu_features[GNLD_DPM_LINK].smu_feature_id =
320 			FEATURE_DPM_LINK_BIT;
321 	data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
322 			FEATURE_DPM_DCEFCLK_BIT;
323 	data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
324 			FEATURE_DS_GFXCLK_BIT;
325 	data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
326 			FEATURE_DS_SOCCLK_BIT;
327 	data->smu_features[GNLD_DS_LCLK].smu_feature_id =
328 			FEATURE_DS_LCLK_BIT;
329 	data->smu_features[GNLD_PPT].smu_feature_id =
330 			FEATURE_PPT_BIT;
331 	data->smu_features[GNLD_TDC].smu_feature_id =
332 			FEATURE_TDC_BIT;
333 	data->smu_features[GNLD_THERMAL].smu_feature_id =
334 			FEATURE_THERMAL_BIT;
335 	data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
336 			FEATURE_GFX_PER_CU_CG_BIT;
337 	data->smu_features[GNLD_RM].smu_feature_id =
338 			FEATURE_RM_BIT;
339 	data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
340 			FEATURE_DS_DCEFCLK_BIT;
341 	data->smu_features[GNLD_ACDC].smu_feature_id =
342 			FEATURE_ACDC_BIT;
343 	data->smu_features[GNLD_VR0HOT].smu_feature_id =
344 			FEATURE_VR0HOT_BIT;
345 	data->smu_features[GNLD_VR1HOT].smu_feature_id =
346 			FEATURE_VR1HOT_BIT;
347 	data->smu_features[GNLD_FW_CTF].smu_feature_id =
348 			FEATURE_FW_CTF_BIT;
349 	data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
350 			FEATURE_LED_DISPLAY_BIT;
351 	data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
352 			FEATURE_FAN_CONTROL_BIT;
353 	data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
354 	data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
355 	data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
356 	data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
357 
358 	for (i = 0; i < GNLD_FEATURES_MAX; i++) {
359 		data->smu_features[i].smu_feature_bitmap =
360 			(uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
361 		data->smu_features[i].allowed =
362 			((data->registry_data.disallowed_features >> i) & 1) ?
363 			false : true;
364 	}
365 
366 	/* Get the SN to turn into a Unique ID */
367 	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
368 	if (ret)
369 		return ret;
370 	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
371 	if (ret)
372 		return ret;
373 
374 	adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
375 
376 	return 0;
377 }
378 
vega12_set_private_data_based_on_pptable(struct pp_hwmgr * hwmgr)379 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
380 {
381 	return 0;
382 }
383 
vega12_hwmgr_backend_fini(struct pp_hwmgr * hwmgr)384 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
385 {
386 	kfree(hwmgr->backend);
387 	hwmgr->backend = NULL;
388 
389 	return 0;
390 }
391 
vega12_hwmgr_backend_init(struct pp_hwmgr * hwmgr)392 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
393 {
394 	int result = 0;
395 	struct vega12_hwmgr *data;
396 	struct amdgpu_device *adev = hwmgr->adev;
397 
398 	data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
399 	if (data == NULL)
400 		return -ENOMEM;
401 
402 	hwmgr->backend = data;
403 
404 	vega12_set_default_registry_data(hwmgr);
405 
406 	data->disable_dpm_mask = 0xff;
407 	data->workload_mask = 0xff;
408 
409 	/* need to set voltage control types before EVV patching */
410 	data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
411 	data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
412 	data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
413 
414 	data->water_marks_bitmap = 0;
415 	data->avfs_exist = false;
416 
417 	vega12_set_features_platform_caps(hwmgr);
418 
419 	result = vega12_init_dpm_defaults(hwmgr);
420 	if (result) {
421 		pr_err("%s failed\n", __func__);
422 		return result;
423 	}
424 
425 	/* Parse pptable data read from VBIOS */
426 	vega12_set_private_data_based_on_pptable(hwmgr);
427 
428 	data->is_tlu_enabled = false;
429 
430 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
431 			VEGA12_MAX_HARDWARE_POWERLEVELS;
432 	hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
433 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
434 
435 	hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
436 	/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
437 	hwmgr->platform_descriptor.clockStep.engineClock = 500;
438 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
439 
440 	data->total_active_cus = adev->gfx.cu_info.number;
441 	/* Setup default Overdrive Fan control settings */
442 	data->odn_fan_table.target_fan_speed =
443 			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
444 	data->odn_fan_table.target_temperature =
445 			hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
446 	data->odn_fan_table.min_performance_clock =
447 			hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
448 	data->odn_fan_table.min_fan_limit =
449 			hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
450 			hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
451 
452 	if (hwmgr->feature_mask & PP_GFXOFF_MASK)
453 		data->gfxoff_controlled_by_driver = true;
454 	else
455 		data->gfxoff_controlled_by_driver = false;
456 
457 	return result;
458 }
459 
vega12_init_sclk_threshold(struct pp_hwmgr * hwmgr)460 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
461 {
462 	struct vega12_hwmgr *data =
463 			(struct vega12_hwmgr *)(hwmgr->backend);
464 
465 	data->low_sclk_interrupt_threshold = 0;
466 
467 	return 0;
468 }
469 
vega12_setup_asic_task(struct pp_hwmgr * hwmgr)470 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
471 {
472 	PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
473 			"Failed to init sclk threshold!",
474 			return -EINVAL);
475 
476 	return 0;
477 }
478 
479 /*
480  * @fn vega12_init_dpm_state
481  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
482  *
483  * @param    dpm_state - the address of the DPM Table to initiailize.
484  * @return   None.
485  */
vega12_init_dpm_state(struct vega12_dpm_state * dpm_state)486 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
487 {
488 	dpm_state->soft_min_level = 0x0;
489 	dpm_state->soft_max_level = 0xffff;
490 	dpm_state->hard_min_level = 0x0;
491 	dpm_state->hard_max_level = 0xffff;
492 }
493 
vega12_override_pcie_parameters(struct pp_hwmgr * hwmgr)494 static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr)
495 {
496 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
497 	struct vega12_hwmgr *data =
498 			(struct vega12_hwmgr *)(hwmgr->backend);
499 	uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;
500 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
501 	int i;
502 	int ret;
503 
504 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
505 		pcie_gen = 3;
506 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
507 		pcie_gen = 2;
508 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
509 		pcie_gen = 1;
510 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
511 		pcie_gen = 0;
512 
513 	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
514 		pcie_width = 6;
515 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
516 		pcie_width = 5;
517 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
518 		pcie_width = 4;
519 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
520 		pcie_width = 3;
521 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
522 		pcie_width = 2;
523 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
524 		pcie_width = 1;
525 
526 	/* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
527 	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
528 	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
529 	 */
530 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
531 		pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen :
532 			pp_table->PcieGenSpeed[i];
533 		pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width :
534 			pp_table->PcieLaneCount[i];
535 
536 		if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg !=
537 		    pp_table->PcieLaneCount[i]) {
538 			smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg;
539 			ret = smum_send_msg_to_smc_with_parameter(hwmgr,
540 				PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
541 				NULL);
542 			PP_ASSERT_WITH_CODE(!ret,
543 				"[OverridePcieParameters] Attempt to override pcie params failed!",
544 				return ret);
545 		}
546 
547 		/* update the pptable */
548 		pp_table->PcieGenSpeed[i] = pcie_gen_arg;
549 		pp_table->PcieLaneCount[i] = pcie_width_arg;
550 	}
551 
552 	/* override to the highest if it's disabled from ppfeaturmask */
553 	if (data->registry_data.pcie_dpm_key_disabled) {
554 		for (i = 0; i < NUM_LINK_LEVELS; i++) {
555 			smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;
556 			ret = smum_send_msg_to_smc_with_parameter(hwmgr,
557 				PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
558 				NULL);
559 			PP_ASSERT_WITH_CODE(!ret,
560 				"[OverridePcieParameters] Attempt to override pcie params failed!",
561 				return ret);
562 
563 			pp_table->PcieGenSpeed[i] = pcie_gen;
564 			pp_table->PcieLaneCount[i] = pcie_width;
565 		}
566 		ret = vega12_enable_smc_features(hwmgr,
567 				false,
568 				data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);
569 		PP_ASSERT_WITH_CODE(!ret,
570 				"Attempt to Disable DPM LINK Failed!",
571 				return ret);
572 		data->smu_features[GNLD_DPM_LINK].enabled = false;
573 		data->smu_features[GNLD_DPM_LINK].supported = false;
574 	}
575 	return 0;
576 }
577 
vega12_get_number_of_dpm_level(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t * num_of_levels)578 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
579 		PPCLK_e clk_id, uint32_t *num_of_levels)
580 {
581 	int ret = 0;
582 
583 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
584 			PPSMC_MSG_GetDpmFreqByIndex,
585 			(clk_id << 16 | 0xFF),
586 			num_of_levels);
587 	PP_ASSERT_WITH_CODE(!ret,
588 			"[GetNumOfDpmLevel] failed to get dpm levels!",
589 			return ret);
590 
591 	return ret;
592 }
593 
vega12_get_dpm_frequency_by_index(struct pp_hwmgr * hwmgr,PPCLK_e clkID,uint32_t index,uint32_t * clock)594 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
595 		PPCLK_e clkID, uint32_t index, uint32_t *clock)
596 {
597 	/*
598 	 *SMU expects the Clock ID to be in the top 16 bits.
599 	 *Lower 16 bits specify the level
600 	 */
601 	PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
602 		PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index),
603 		clock) == 0,
604 		"[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
605 		return -EINVAL);
606 
607 	return 0;
608 }
609 
vega12_setup_single_dpm_table(struct pp_hwmgr * hwmgr,struct vega12_single_dpm_table * dpm_table,PPCLK_e clk_id)610 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
611 		struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
612 {
613 	int ret = 0;
614 	uint32_t i, num_of_levels, clk;
615 
616 	ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
617 	PP_ASSERT_WITH_CODE(!ret,
618 			"[SetupSingleDpmTable] failed to get clk levels!",
619 			return ret);
620 
621 	dpm_table->count = num_of_levels;
622 
623 	for (i = 0; i < num_of_levels; i++) {
624 		ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
625 		PP_ASSERT_WITH_CODE(!ret,
626 			"[SetupSingleDpmTable] failed to get clk of specific level!",
627 			return ret);
628 		dpm_table->dpm_levels[i].value = clk;
629 		dpm_table->dpm_levels[i].enabled = true;
630 	}
631 
632 	return ret;
633 }
634 
635 /*
636  * This function is to initialize all DPM state tables
637  * for SMU based on the dependency table.
638  * Dynamic state patching function will then trim these
639  * state tables to the allowed range based
640  * on the power policy or external client requests,
641  * such as UVD request, etc.
642  */
vega12_setup_default_dpm_tables(struct pp_hwmgr * hwmgr)643 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
644 {
645 
646 	struct vega12_hwmgr *data =
647 			(struct vega12_hwmgr *)(hwmgr->backend);
648 	struct vega12_single_dpm_table *dpm_table;
649 	int ret = 0;
650 
651 	memset(&data->dpm_table, 0, sizeof(data->dpm_table));
652 
653 	/* socclk */
654 	dpm_table = &(data->dpm_table.soc_table);
655 	if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
656 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
657 		PP_ASSERT_WITH_CODE(!ret,
658 				"[SetupDefaultDpmTable] failed to get socclk dpm levels!",
659 				return ret);
660 	} else {
661 		dpm_table->count = 1;
662 		dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
663 	}
664 	vega12_init_dpm_state(&(dpm_table->dpm_state));
665 
666 	/* gfxclk */
667 	dpm_table = &(data->dpm_table.gfx_table);
668 	if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
669 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
670 		PP_ASSERT_WITH_CODE(!ret,
671 				"[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
672 				return ret);
673 	} else {
674 		dpm_table->count = 1;
675 		dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
676 	}
677 	vega12_init_dpm_state(&(dpm_table->dpm_state));
678 
679 	/* memclk */
680 	dpm_table = &(data->dpm_table.mem_table);
681 	if (data->smu_features[GNLD_DPM_UCLK].enabled) {
682 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
683 		PP_ASSERT_WITH_CODE(!ret,
684 				"[SetupDefaultDpmTable] failed to get memclk dpm levels!",
685 				return ret);
686 	} else {
687 		dpm_table->count = 1;
688 		dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
689 	}
690 	vega12_init_dpm_state(&(dpm_table->dpm_state));
691 
692 	/* eclk */
693 	dpm_table = &(data->dpm_table.eclk_table);
694 	if (data->smu_features[GNLD_DPM_VCE].enabled) {
695 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
696 		PP_ASSERT_WITH_CODE(!ret,
697 				"[SetupDefaultDpmTable] failed to get eclk dpm levels!",
698 				return ret);
699 	} else {
700 		dpm_table->count = 1;
701 		dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
702 	}
703 	vega12_init_dpm_state(&(dpm_table->dpm_state));
704 
705 	/* vclk */
706 	dpm_table = &(data->dpm_table.vclk_table);
707 	if (data->smu_features[GNLD_DPM_UVD].enabled) {
708 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
709 		PP_ASSERT_WITH_CODE(!ret,
710 				"[SetupDefaultDpmTable] failed to get vclk dpm levels!",
711 				return ret);
712 	} else {
713 		dpm_table->count = 1;
714 		dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
715 	}
716 	vega12_init_dpm_state(&(dpm_table->dpm_state));
717 
718 	/* dclk */
719 	dpm_table = &(data->dpm_table.dclk_table);
720 	if (data->smu_features[GNLD_DPM_UVD].enabled) {
721 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
722 		PP_ASSERT_WITH_CODE(!ret,
723 				"[SetupDefaultDpmTable] failed to get dclk dpm levels!",
724 				return ret);
725 	} else {
726 		dpm_table->count = 1;
727 		dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
728 	}
729 	vega12_init_dpm_state(&(dpm_table->dpm_state));
730 
731 	/* dcefclk */
732 	dpm_table = &(data->dpm_table.dcef_table);
733 	if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
734 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
735 		PP_ASSERT_WITH_CODE(!ret,
736 				"[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
737 				return ret);
738 	} else {
739 		dpm_table->count = 1;
740 		dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
741 	}
742 	vega12_init_dpm_state(&(dpm_table->dpm_state));
743 
744 	/* pixclk */
745 	dpm_table = &(data->dpm_table.pixel_table);
746 	if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
747 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
748 		PP_ASSERT_WITH_CODE(!ret,
749 				"[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
750 				return ret);
751 	} else
752 		dpm_table->count = 0;
753 	vega12_init_dpm_state(&(dpm_table->dpm_state));
754 
755 	/* dispclk */
756 	dpm_table = &(data->dpm_table.display_table);
757 	if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
758 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
759 		PP_ASSERT_WITH_CODE(!ret,
760 				"[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
761 				return ret);
762 	} else
763 		dpm_table->count = 0;
764 	vega12_init_dpm_state(&(dpm_table->dpm_state));
765 
766 	/* phyclk */
767 	dpm_table = &(data->dpm_table.phy_table);
768 	if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
769 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
770 		PP_ASSERT_WITH_CODE(!ret,
771 				"[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
772 				return ret);
773 	} else
774 		dpm_table->count = 0;
775 	vega12_init_dpm_state(&(dpm_table->dpm_state));
776 
777 	/* save a copy of the default DPM table */
778 	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
779 			sizeof(struct vega12_dpm_table));
780 
781 	return 0;
782 }
783 
784 #if 0
785 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
786 {
787 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
788 	struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
789 	uint32_t min_level;
790 
791 	hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
792 	hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
793 
794 	/* Optimize compute power profile: Use only highest
795 	 * 2 power levels (if more than 2 are available)
796 	 */
797 	if (dpm_table->count > 2)
798 		min_level = dpm_table->count - 2;
799 	else if (dpm_table->count == 2)
800 		min_level = 1;
801 	else
802 		min_level = 0;
803 
804 	hwmgr->default_compute_power_profile.min_sclk =
805 			dpm_table->dpm_levels[min_level].value;
806 
807 	hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
808 	hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
809 
810 	return 0;
811 }
812 #endif
813 
814 /**
815  * vega12_init_smc_table - Initializes the SMC table and uploads it
816  *
817  * @hwmgr:  the address of the powerplay hardware manager.
818  * return:  always 0
819  */
vega12_init_smc_table(struct pp_hwmgr * hwmgr)820 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
821 {
822 	int result;
823 	struct vega12_hwmgr *data =
824 			(struct vega12_hwmgr *)(hwmgr->backend);
825 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
826 	struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
827 	struct phm_ppt_v3_information *pptable_information =
828 		(struct phm_ppt_v3_information *)hwmgr->pptable;
829 
830 	result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
831 	if (!result) {
832 		data->vbios_boot_state.vddc     = boot_up_values.usVddc;
833 		data->vbios_boot_state.vddci    = boot_up_values.usVddci;
834 		data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
835 		data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
836 		data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
837 		data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
838 		data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
839 		data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
840 		data->vbios_boot_state.eclock = boot_up_values.ulEClk;
841 		data->vbios_boot_state.dclock = boot_up_values.ulDClk;
842 		data->vbios_boot_state.vclock = boot_up_values.ulVClk;
843 		smum_send_msg_to_smc_with_parameter(hwmgr,
844 				PPSMC_MSG_SetMinDeepSleepDcefclk,
845 			(uint32_t)(data->vbios_boot_state.dcef_clock / 100),
846 				NULL);
847 	}
848 
849 	memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
850 
851 	result = smum_smc_table_manager(hwmgr,
852 					(uint8_t *)pp_table, TABLE_PPTABLE, false);
853 	PP_ASSERT_WITH_CODE(!result,
854 			"Failed to upload PPtable!", return result);
855 
856 	return 0;
857 }
858 
vega12_run_acg_btc(struct pp_hwmgr * hwmgr)859 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
860 {
861 	uint32_t result;
862 
863 	PP_ASSERT_WITH_CODE(
864 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0,
865 		"[Run_ACG_BTC] Attempt to run ACG BTC failed!",
866 		return -EINVAL);
867 
868 	PP_ASSERT_WITH_CODE(result == 1,
869 			"Failed to run ACG BTC!", return -EINVAL);
870 
871 	return 0;
872 }
873 
vega12_set_allowed_featuresmask(struct pp_hwmgr * hwmgr)874 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
875 {
876 	struct vega12_hwmgr *data =
877 			(struct vega12_hwmgr *)(hwmgr->backend);
878 	int i;
879 	uint32_t allowed_features_low = 0, allowed_features_high = 0;
880 
881 	for (i = 0; i < GNLD_FEATURES_MAX; i++)
882 		if (data->smu_features[i].allowed)
883 			data->smu_features[i].smu_feature_id > 31 ?
884 				(allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
885 				(allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
886 
887 	PP_ASSERT_WITH_CODE(
888 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high,
889 			NULL) == 0,
890 		"[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
891 		return -1);
892 
893 	PP_ASSERT_WITH_CODE(
894 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low,
895 			NULL) == 0,
896 		"[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
897 		return -1);
898 
899 	return 0;
900 }
901 
vega12_init_powergate_state(struct pp_hwmgr * hwmgr)902 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
903 {
904 	struct vega12_hwmgr *data =
905 			(struct vega12_hwmgr *)(hwmgr->backend);
906 
907 	data->uvd_power_gated = true;
908 	data->vce_power_gated = true;
909 
910 	if (data->smu_features[GNLD_DPM_UVD].enabled)
911 		data->uvd_power_gated = false;
912 
913 	if (data->smu_features[GNLD_DPM_VCE].enabled)
914 		data->vce_power_gated = false;
915 }
916 
vega12_enable_all_smu_features(struct pp_hwmgr * hwmgr)917 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
918 {
919 	struct vega12_hwmgr *data =
920 			(struct vega12_hwmgr *)(hwmgr->backend);
921 	uint64_t features_enabled;
922 	int i;
923 	bool enabled;
924 
925 	PP_ASSERT_WITH_CODE(
926 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0,
927 		"[EnableAllSMUFeatures] Failed to enable all smu features!",
928 		return -1);
929 
930 	if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
931 		for (i = 0; i < GNLD_FEATURES_MAX; i++) {
932 			enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
933 			data->smu_features[i].enabled = enabled;
934 			data->smu_features[i].supported = enabled;
935 		}
936 	}
937 
938 	vega12_init_powergate_state(hwmgr);
939 
940 	return 0;
941 }
942 
vega12_disable_all_smu_features(struct pp_hwmgr * hwmgr)943 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
944 {
945 	struct vega12_hwmgr *data =
946 			(struct vega12_hwmgr *)(hwmgr->backend);
947 	uint64_t features_enabled;
948 	int i;
949 	bool enabled;
950 
951 	PP_ASSERT_WITH_CODE(
952 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0,
953 		"[DisableAllSMUFeatures] Failed to disable all smu features!",
954 		return -1);
955 
956 	if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
957 		for (i = 0; i < GNLD_FEATURES_MAX; i++) {
958 			enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
959 			data->smu_features[i].enabled = enabled;
960 			data->smu_features[i].supported = enabled;
961 		}
962 	}
963 
964 	return 0;
965 }
966 
vega12_odn_initialize_default_settings(struct pp_hwmgr * hwmgr)967 static int vega12_odn_initialize_default_settings(
968 		struct pp_hwmgr *hwmgr)
969 {
970 	return 0;
971 }
972 
vega12_set_overdrive_target_percentage(struct pp_hwmgr * hwmgr,uint32_t adjust_percent)973 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
974 		uint32_t adjust_percent)
975 {
976 	return smum_send_msg_to_smc_with_parameter(hwmgr,
977 			PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
978 			NULL);
979 }
980 
vega12_power_control_set_level(struct pp_hwmgr * hwmgr)981 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
982 {
983 	int adjust_percent, result = 0;
984 
985 	if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
986 		adjust_percent =
987 				hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
988 				hwmgr->platform_descriptor.TDPAdjustment :
989 				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
990 		result = vega12_set_overdrive_target_percentage(hwmgr,
991 				(uint32_t)adjust_percent);
992 	}
993 	return result;
994 }
995 
vega12_get_all_clock_ranges_helper(struct pp_hwmgr * hwmgr,PPCLK_e clkid,struct vega12_clock_range * clock)996 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
997 		PPCLK_e clkid, struct vega12_clock_range *clock)
998 {
999 	/* AC Max */
1000 	PP_ASSERT_WITH_CODE(
1001 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16),
1002 			&(clock->ACMax)) == 0,
1003 		"[GetClockRanges] Failed to get max ac clock from SMC!",
1004 		return -EINVAL);
1005 
1006 	/* AC Min */
1007 	PP_ASSERT_WITH_CODE(
1008 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16),
1009 			&(clock->ACMin)) == 0,
1010 		"[GetClockRanges] Failed to get min ac clock from SMC!",
1011 		return -EINVAL);
1012 
1013 	/* DC Max */
1014 	PP_ASSERT_WITH_CODE(
1015 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16),
1016 			&(clock->DCMax)) == 0,
1017 		"[GetClockRanges] Failed to get max dc clock from SMC!",
1018 		return -EINVAL);
1019 
1020 	return 0;
1021 }
1022 
vega12_get_all_clock_ranges(struct pp_hwmgr * hwmgr)1023 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
1024 {
1025 	struct vega12_hwmgr *data =
1026 			(struct vega12_hwmgr *)(hwmgr->backend);
1027 	uint32_t i;
1028 
1029 	for (i = 0; i < PPCLK_COUNT; i++)
1030 		PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
1031 					i, &(data->clk_range[i])),
1032 				"Failed to get clk range from SMC!",
1033 				return -EINVAL);
1034 
1035 	return 0;
1036 }
1037 
vega12_populate_umdpstate_clocks(struct pp_hwmgr * hwmgr)1038 static void vega12_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
1039 {
1040 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1041 	struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1042 	struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1043 
1044 	if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1045 	    mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL) {
1046 		hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
1047 		hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
1048 	} else {
1049 		hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[0].value;
1050 		hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[0].value;
1051 	}
1052 
1053 	hwmgr->pstate_sclk_peak = gfx_dpm_table->dpm_levels[gfx_dpm_table->count].value;
1054 	hwmgr->pstate_mclk_peak = mem_dpm_table->dpm_levels[mem_dpm_table->count].value;
1055 }
1056 
vega12_enable_dpm_tasks(struct pp_hwmgr * hwmgr)1057 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1058 {
1059 	int tmp_result, result = 0;
1060 
1061 	smum_send_msg_to_smc_with_parameter(hwmgr,
1062 			PPSMC_MSG_NumOfDisplays, 0, NULL);
1063 
1064 	result = vega12_set_allowed_featuresmask(hwmgr);
1065 	PP_ASSERT_WITH_CODE(result == 0,
1066 			"[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1067 			return result);
1068 
1069 	tmp_result = vega12_init_smc_table(hwmgr);
1070 	PP_ASSERT_WITH_CODE(!tmp_result,
1071 			"Failed to initialize SMC table!",
1072 			result = tmp_result);
1073 
1074 	tmp_result = vega12_run_acg_btc(hwmgr);
1075 	PP_ASSERT_WITH_CODE(!tmp_result,
1076 			"Failed to run ACG BTC!",
1077 			result = tmp_result);
1078 
1079 	result = vega12_enable_all_smu_features(hwmgr);
1080 	PP_ASSERT_WITH_CODE(!result,
1081 			"Failed to enable all smu features!",
1082 			return result);
1083 
1084 	result = vega12_override_pcie_parameters(hwmgr);
1085 	PP_ASSERT_WITH_CODE(!result,
1086 			"[EnableDPMTasks] Failed to override pcie parameters!",
1087 			return result);
1088 
1089 	tmp_result = vega12_power_control_set_level(hwmgr);
1090 	PP_ASSERT_WITH_CODE(!tmp_result,
1091 			"Failed to power control set level!",
1092 			result = tmp_result);
1093 
1094 	result = vega12_get_all_clock_ranges(hwmgr);
1095 	PP_ASSERT_WITH_CODE(!result,
1096 			"Failed to get all clock ranges!",
1097 			return result);
1098 
1099 	result = vega12_odn_initialize_default_settings(hwmgr);
1100 	PP_ASSERT_WITH_CODE(!result,
1101 			"Failed to power control set level!",
1102 			return result);
1103 
1104 	result = vega12_setup_default_dpm_tables(hwmgr);
1105 	PP_ASSERT_WITH_CODE(!result,
1106 			"Failed to setup default DPM tables!",
1107 			return result);
1108 
1109 	vega12_populate_umdpstate_clocks(hwmgr);
1110 
1111 	return result;
1112 }
1113 
vega12_patch_boot_state(struct pp_hwmgr * hwmgr,struct pp_hw_power_state * hw_ps)1114 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
1115 	     struct pp_hw_power_state *hw_ps)
1116 {
1117 	return 0;
1118 }
1119 
vega12_find_lowest_dpm_level(struct vega12_single_dpm_table * table)1120 static uint32_t vega12_find_lowest_dpm_level(
1121 		struct vega12_single_dpm_table *table)
1122 {
1123 	uint32_t i;
1124 
1125 	for (i = 0; i < table->count; i++) {
1126 		if (table->dpm_levels[i].enabled)
1127 			break;
1128 	}
1129 
1130 	if (i >= table->count) {
1131 		i = 0;
1132 		table->dpm_levels[i].enabled = true;
1133 	}
1134 
1135 	return i;
1136 }
1137 
vega12_find_highest_dpm_level(struct vega12_single_dpm_table * table)1138 static uint32_t vega12_find_highest_dpm_level(
1139 		struct vega12_single_dpm_table *table)
1140 {
1141 	int32_t i = 0;
1142 	PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1143 			"[FindHighestDPMLevel] DPM Table has too many entries!",
1144 			return MAX_REGULAR_DPM_NUMBER - 1);
1145 
1146 	for (i = table->count - 1; i >= 0; i--) {
1147 		if (table->dpm_levels[i].enabled)
1148 			break;
1149 	}
1150 
1151 	if (i < 0) {
1152 		i = 0;
1153 		table->dpm_levels[i].enabled = true;
1154 	}
1155 
1156 	return (uint32_t)i;
1157 }
1158 
vega12_upload_dpm_min_level(struct pp_hwmgr * hwmgr)1159 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1160 {
1161 	struct vega12_hwmgr *data = hwmgr->backend;
1162 	uint32_t min_freq;
1163 	int ret = 0;
1164 
1165 	if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1166 		min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1167 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1168 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1169 					(PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1170 					NULL)),
1171 					"Failed to set soft min gfxclk !",
1172 					return ret);
1173 	}
1174 
1175 	if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1176 		min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1177 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1178 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1179 					(PPCLK_UCLK << 16) | (min_freq & 0xffff),
1180 					NULL)),
1181 					"Failed to set soft min memclk !",
1182 					return ret);
1183 
1184 		min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1185 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1186 					hwmgr, PPSMC_MSG_SetHardMinByFreq,
1187 					(PPCLK_UCLK << 16) | (min_freq & 0xffff),
1188 					NULL)),
1189 					"Failed to set hard min memclk !",
1190 					return ret);
1191 	}
1192 
1193 	if (data->smu_features[GNLD_DPM_UVD].enabled) {
1194 		min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1195 
1196 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1197 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1198 					(PPCLK_VCLK << 16) | (min_freq & 0xffff),
1199 					NULL)),
1200 					"Failed to set soft min vclk!",
1201 					return ret);
1202 
1203 		min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1204 
1205 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1206 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1207 					(PPCLK_DCLK << 16) | (min_freq & 0xffff),
1208 					NULL)),
1209 					"Failed to set soft min dclk!",
1210 					return ret);
1211 	}
1212 
1213 	if (data->smu_features[GNLD_DPM_VCE].enabled) {
1214 		min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1215 
1216 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1217 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1218 					(PPCLK_ECLK << 16) | (min_freq & 0xffff),
1219 					NULL)),
1220 					"Failed to set soft min eclk!",
1221 					return ret);
1222 	}
1223 
1224 	if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1225 		min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1226 
1227 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1228 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1229 					(PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1230 					NULL)),
1231 					"Failed to set soft min socclk!",
1232 					return ret);
1233 	}
1234 
1235 	if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1236 		min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1237 
1238 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1239 					hwmgr, PPSMC_MSG_SetHardMinByFreq,
1240 					(PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1241 					NULL)),
1242 					"Failed to set hard min dcefclk!",
1243 					return ret);
1244 	}
1245 
1246 	return ret;
1247 
1248 }
1249 
vega12_upload_dpm_max_level(struct pp_hwmgr * hwmgr)1250 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1251 {
1252 	struct vega12_hwmgr *data = hwmgr->backend;
1253 	uint32_t max_freq;
1254 	int ret = 0;
1255 
1256 	if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1257 		max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1258 
1259 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1260 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1261 					(PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1262 					NULL)),
1263 					"Failed to set soft max gfxclk!",
1264 					return ret);
1265 	}
1266 
1267 	if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1268 		max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1269 
1270 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1271 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1272 					(PPCLK_UCLK << 16) | (max_freq & 0xffff),
1273 					NULL)),
1274 					"Failed to set soft max memclk!",
1275 					return ret);
1276 	}
1277 
1278 	if (data->smu_features[GNLD_DPM_UVD].enabled) {
1279 		max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1280 
1281 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1282 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1283 					(PPCLK_VCLK << 16) | (max_freq & 0xffff),
1284 					NULL)),
1285 					"Failed to set soft max vclk!",
1286 					return ret);
1287 
1288 		max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1289 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1290 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1291 					(PPCLK_DCLK << 16) | (max_freq & 0xffff),
1292 					NULL)),
1293 					"Failed to set soft max dclk!",
1294 					return ret);
1295 	}
1296 
1297 	if (data->smu_features[GNLD_DPM_VCE].enabled) {
1298 		max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1299 
1300 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1301 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1302 					(PPCLK_ECLK << 16) | (max_freq & 0xffff),
1303 					NULL)),
1304 					"Failed to set soft max eclk!",
1305 					return ret);
1306 	}
1307 
1308 	if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1309 		max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1310 
1311 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1312 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1313 					(PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1314 					NULL)),
1315 					"Failed to set soft max socclk!",
1316 					return ret);
1317 	}
1318 
1319 	return ret;
1320 }
1321 
vega12_enable_disable_vce_dpm(struct pp_hwmgr * hwmgr,bool enable)1322 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1323 {
1324 	struct vega12_hwmgr *data =
1325 			(struct vega12_hwmgr *)(hwmgr->backend);
1326 
1327 	if (data->smu_features[GNLD_DPM_VCE].supported) {
1328 		PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1329 				enable,
1330 				data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1331 				"Attempt to Enable/Disable DPM VCE Failed!",
1332 				return -1);
1333 		data->smu_features[GNLD_DPM_VCE].enabled = enable;
1334 	}
1335 
1336 	return 0;
1337 }
1338 
vega12_dpm_get_sclk(struct pp_hwmgr * hwmgr,bool low)1339 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1340 {
1341 	struct vega12_hwmgr *data =
1342 			(struct vega12_hwmgr *)(hwmgr->backend);
1343 	uint32_t gfx_clk;
1344 
1345 	if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1346 		return -1;
1347 
1348 	if (low)
1349 		PP_ASSERT_WITH_CODE(
1350 			vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1351 			"[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1352 			return -1);
1353 	else
1354 		PP_ASSERT_WITH_CODE(
1355 			vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1356 			"[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1357 			return -1);
1358 
1359 	return (gfx_clk * 100);
1360 }
1361 
vega12_dpm_get_mclk(struct pp_hwmgr * hwmgr,bool low)1362 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1363 {
1364 	struct vega12_hwmgr *data =
1365 			(struct vega12_hwmgr *)(hwmgr->backend);
1366 	uint32_t mem_clk;
1367 
1368 	if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1369 		return -1;
1370 
1371 	if (low)
1372 		PP_ASSERT_WITH_CODE(
1373 			vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1374 			"[GetMclks]: fail to get min PPCLK_UCLK\n",
1375 			return -1);
1376 	else
1377 		PP_ASSERT_WITH_CODE(
1378 			vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1379 			"[GetMclks]: fail to get max PPCLK_UCLK\n",
1380 			return -1);
1381 
1382 	return (mem_clk * 100);
1383 }
1384 
vega12_get_metrics_table(struct pp_hwmgr * hwmgr,SmuMetrics_t * metrics_table,bool bypass_cache)1385 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr,
1386 				    SmuMetrics_t *metrics_table,
1387 				    bool bypass_cache)
1388 {
1389 	struct vega12_hwmgr *data =
1390 			(struct vega12_hwmgr *)(hwmgr->backend);
1391 	int ret = 0;
1392 
1393 	if (bypass_cache ||
1394 	    !data->metrics_time ||
1395 	    time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) {
1396 		ret = smum_smc_table_manager(hwmgr,
1397 					     (uint8_t *)(&data->metrics_table),
1398 					     TABLE_SMU_METRICS,
1399 					     true);
1400 		if (ret) {
1401 			pr_info("Failed to export SMU metrics table!\n");
1402 			return ret;
1403 		}
1404 		data->metrics_time = jiffies;
1405 	}
1406 
1407 	if (metrics_table)
1408 		memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
1409 
1410 	return ret;
1411 }
1412 
vega12_get_gpu_power(struct pp_hwmgr * hwmgr,uint32_t * query)1413 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1414 {
1415 	SmuMetrics_t metrics_table;
1416 	int ret = 0;
1417 
1418 	ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1419 	if (ret)
1420 		return ret;
1421 
1422 	*query = metrics_table.CurrSocketPower << 8;
1423 
1424 	return ret;
1425 }
1426 
vega12_get_current_gfx_clk_freq(struct pp_hwmgr * hwmgr,uint32_t * gfx_freq)1427 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1428 {
1429 	uint32_t gfx_clk = 0;
1430 
1431 	*gfx_freq = 0;
1432 
1433 	PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1434 			PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16),
1435 			&gfx_clk) == 0,
1436 			"[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1437 			return -EINVAL);
1438 
1439 	*gfx_freq = gfx_clk * 100;
1440 
1441 	return 0;
1442 }
1443 
vega12_get_current_mclk_freq(struct pp_hwmgr * hwmgr,uint32_t * mclk_freq)1444 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1445 {
1446 	uint32_t mem_clk = 0;
1447 
1448 	*mclk_freq = 0;
1449 
1450 	PP_ASSERT_WITH_CODE(
1451 			smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16),
1452 				&mem_clk) == 0,
1453 			"[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1454 			return -EINVAL);
1455 
1456 	*mclk_freq = mem_clk * 100;
1457 
1458 	return 0;
1459 }
1460 
vega12_get_current_activity_percent(struct pp_hwmgr * hwmgr,int idx,uint32_t * activity_percent)1461 static int vega12_get_current_activity_percent(
1462 		struct pp_hwmgr *hwmgr,
1463 		int idx,
1464 		uint32_t *activity_percent)
1465 {
1466 	SmuMetrics_t metrics_table;
1467 	int ret = 0;
1468 
1469 	ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1470 	if (ret)
1471 		return ret;
1472 
1473 	switch (idx) {
1474 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1475 		*activity_percent = metrics_table.AverageGfxActivity;
1476 		break;
1477 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1478 		*activity_percent = metrics_table.AverageUclkActivity;
1479 		break;
1480 	default:
1481 		pr_err("Invalid index for retrieving clock activity\n");
1482 		return -EINVAL;
1483 	}
1484 
1485 	return ret;
1486 }
1487 
vega12_read_sensor(struct pp_hwmgr * hwmgr,int idx,void * value,int * size)1488 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1489 			      void *value, int *size)
1490 {
1491 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1492 	SmuMetrics_t metrics_table;
1493 	int ret = 0;
1494 
1495 	switch (idx) {
1496 	case AMDGPU_PP_SENSOR_GFX_SCLK:
1497 		ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1498 		if (!ret)
1499 			*size = 4;
1500 		break;
1501 	case AMDGPU_PP_SENSOR_GFX_MCLK:
1502 		ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1503 		if (!ret)
1504 			*size = 4;
1505 		break;
1506 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1507 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1508 		ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
1509 		if (!ret)
1510 			*size = 4;
1511 		break;
1512 	case AMDGPU_PP_SENSOR_GPU_TEMP:
1513 		*((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1514 		*size = 4;
1515 		break;
1516 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1517 		ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1518 		if (ret)
1519 			return ret;
1520 
1521 		*((uint32_t *)value) = metrics_table.TemperatureHotspot *
1522 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1523 		*size = 4;
1524 		break;
1525 	case AMDGPU_PP_SENSOR_MEM_TEMP:
1526 		ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1527 		if (ret)
1528 			return ret;
1529 
1530 		*((uint32_t *)value) = metrics_table.TemperatureHBM *
1531 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1532 		*size = 4;
1533 		break;
1534 	case AMDGPU_PP_SENSOR_UVD_POWER:
1535 		*((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1536 		*size = 4;
1537 		break;
1538 	case AMDGPU_PP_SENSOR_VCE_POWER:
1539 		*((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1540 		*size = 4;
1541 		break;
1542 	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1543 		ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1544 		if (!ret)
1545 			*size = 4;
1546 		break;
1547 	case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1548 		ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1549 		if (!ret)
1550 			*size = 8;
1551 		break;
1552 	default:
1553 		ret = -EOPNOTSUPP;
1554 		break;
1555 	}
1556 	return ret;
1557 }
1558 
vega12_notify_smc_display_change(struct pp_hwmgr * hwmgr,bool has_disp)1559 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1560 		bool has_disp)
1561 {
1562 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1563 
1564 	if (data->smu_features[GNLD_DPM_UCLK].enabled)
1565 		return smum_send_msg_to_smc_with_parameter(hwmgr,
1566 			PPSMC_MSG_SetUclkFastSwitch,
1567 			has_disp ? 1 : 0,
1568 			NULL);
1569 
1570 	return 0;
1571 }
1572 
vega12_display_clock_voltage_request(struct pp_hwmgr * hwmgr,struct pp_display_clock_request * clock_req)1573 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1574 		struct pp_display_clock_request *clock_req)
1575 {
1576 	int result = 0;
1577 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1578 	enum amd_pp_clock_type clk_type = clock_req->clock_type;
1579 	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1580 	PPCLK_e clk_select = 0;
1581 	uint32_t clk_request = 0;
1582 
1583 	if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1584 		switch (clk_type) {
1585 		case amd_pp_dcef_clock:
1586 			clk_select = PPCLK_DCEFCLK;
1587 			break;
1588 		case amd_pp_disp_clock:
1589 			clk_select = PPCLK_DISPCLK;
1590 			break;
1591 		case amd_pp_pixel_clock:
1592 			clk_select = PPCLK_PIXCLK;
1593 			break;
1594 		case amd_pp_phy_clock:
1595 			clk_select = PPCLK_PHYCLK;
1596 			break;
1597 		default:
1598 			pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1599 			result = -1;
1600 			break;
1601 		}
1602 
1603 		if (!result) {
1604 			clk_request = (clk_select << 16) | clk_freq;
1605 			result = smum_send_msg_to_smc_with_parameter(hwmgr,
1606 					PPSMC_MSG_SetHardMinByFreq,
1607 					clk_request,
1608 					NULL);
1609 		}
1610 	}
1611 
1612 	return result;
1613 }
1614 
vega12_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr * hwmgr)1615 static int vega12_notify_smc_display_config_after_ps_adjustment(
1616 		struct pp_hwmgr *hwmgr)
1617 {
1618 	struct vega12_hwmgr *data =
1619 			(struct vega12_hwmgr *)(hwmgr->backend);
1620 	struct PP_Clocks min_clocks = {0};
1621 	struct pp_display_clock_request clock_req;
1622 
1623 	if ((hwmgr->display_config->num_display > 1) &&
1624 	     !hwmgr->display_config->multi_monitor_in_sync &&
1625 	     !hwmgr->display_config->nb_pstate_switch_disable)
1626 		vega12_notify_smc_display_change(hwmgr, false);
1627 	else
1628 		vega12_notify_smc_display_change(hwmgr, true);
1629 
1630 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1631 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1632 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1633 
1634 	if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1635 		clock_req.clock_type = amd_pp_dcef_clock;
1636 		clock_req.clock_freq_in_khz = min_clocks.dcefClock / 10;
1637 		if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1638 			if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1639 				PP_ASSERT_WITH_CODE(
1640 					!smum_send_msg_to_smc_with_parameter(
1641 					hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1642 					min_clocks.dcefClockInSR / 100,
1643 					NULL),
1644 					"Attempt to set divider for DCEFCLK Failed!",
1645 					return -1);
1646 		} else {
1647 			pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1648 		}
1649 	}
1650 
1651 	return 0;
1652 }
1653 
vega12_force_dpm_highest(struct pp_hwmgr * hwmgr)1654 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1655 {
1656 	struct vega12_hwmgr *data =
1657 			(struct vega12_hwmgr *)(hwmgr->backend);
1658 
1659 	uint32_t soft_level;
1660 
1661 	soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1662 
1663 	data->dpm_table.gfx_table.dpm_state.soft_min_level =
1664 		data->dpm_table.gfx_table.dpm_state.soft_max_level =
1665 		data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1666 
1667 	soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1668 
1669 	data->dpm_table.mem_table.dpm_state.soft_min_level =
1670 		data->dpm_table.mem_table.dpm_state.soft_max_level =
1671 		data->dpm_table.mem_table.dpm_levels[soft_level].value;
1672 
1673 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1674 			"Failed to upload boot level to highest!",
1675 			return -1);
1676 
1677 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1678 			"Failed to upload dpm max level to highest!",
1679 			return -1);
1680 
1681 	return 0;
1682 }
1683 
vega12_force_dpm_lowest(struct pp_hwmgr * hwmgr)1684 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1685 {
1686 	struct vega12_hwmgr *data =
1687 			(struct vega12_hwmgr *)(hwmgr->backend);
1688 	uint32_t soft_level;
1689 
1690 	soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1691 
1692 	data->dpm_table.gfx_table.dpm_state.soft_min_level =
1693 		data->dpm_table.gfx_table.dpm_state.soft_max_level =
1694 		data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1695 
1696 	soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1697 
1698 	data->dpm_table.mem_table.dpm_state.soft_min_level =
1699 		data->dpm_table.mem_table.dpm_state.soft_max_level =
1700 		data->dpm_table.mem_table.dpm_levels[soft_level].value;
1701 
1702 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1703 			"Failed to upload boot level to highest!",
1704 			return -1);
1705 
1706 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1707 			"Failed to upload dpm max level to highest!",
1708 			return -1);
1709 
1710 	return 0;
1711 
1712 }
1713 
vega12_unforce_dpm_levels(struct pp_hwmgr * hwmgr)1714 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1715 {
1716 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1717 			"Failed to upload DPM Bootup Levels!",
1718 			return -1);
1719 
1720 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1721 			"Failed to upload DPM Max Levels!",
1722 			return -1);
1723 
1724 	return 0;
1725 }
1726 
vega12_get_profiling_clk_mask(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)1727 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1728 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1729 {
1730 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1731 	struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1732 	struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1733 	struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1734 
1735 	*sclk_mask = 0;
1736 	*mclk_mask = 0;
1737 	*soc_mask  = 0;
1738 
1739 	if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1740 	    mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1741 	    soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1742 		*sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1743 		*mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1744 		*soc_mask  = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1745 	}
1746 
1747 	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1748 		*sclk_mask = 0;
1749 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1750 		*mclk_mask = 0;
1751 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1752 		*sclk_mask = gfx_dpm_table->count - 1;
1753 		*mclk_mask = mem_dpm_table->count - 1;
1754 		*soc_mask  = soc_dpm_table->count - 1;
1755 	}
1756 
1757 	return 0;
1758 }
1759 
vega12_set_fan_control_mode(struct pp_hwmgr * hwmgr,uint32_t mode)1760 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1761 {
1762 	switch (mode) {
1763 	case AMD_FAN_CTRL_NONE:
1764 		break;
1765 	case AMD_FAN_CTRL_MANUAL:
1766 		if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1767 			vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1768 		break;
1769 	case AMD_FAN_CTRL_AUTO:
1770 		if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1771 			vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1772 		break;
1773 	default:
1774 		break;
1775 	}
1776 }
1777 
vega12_dpm_force_dpm_level(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level)1778 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1779 				enum amd_dpm_forced_level level)
1780 {
1781 	int ret = 0;
1782 	uint32_t sclk_mask = 0;
1783 	uint32_t mclk_mask = 0;
1784 	uint32_t soc_mask = 0;
1785 
1786 	switch (level) {
1787 	case AMD_DPM_FORCED_LEVEL_HIGH:
1788 		ret = vega12_force_dpm_highest(hwmgr);
1789 		break;
1790 	case AMD_DPM_FORCED_LEVEL_LOW:
1791 		ret = vega12_force_dpm_lowest(hwmgr);
1792 		break;
1793 	case AMD_DPM_FORCED_LEVEL_AUTO:
1794 		ret = vega12_unforce_dpm_levels(hwmgr);
1795 		break;
1796 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1797 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1798 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1799 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1800 		ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1801 		if (ret)
1802 			return ret;
1803 		vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1804 		vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1805 		break;
1806 	case AMD_DPM_FORCED_LEVEL_MANUAL:
1807 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1808 	default:
1809 		break;
1810 	}
1811 
1812 	return ret;
1813 }
1814 
vega12_get_fan_control_mode(struct pp_hwmgr * hwmgr)1815 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1816 {
1817 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1818 
1819 	if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1820 		return AMD_FAN_CTRL_MANUAL;
1821 	else
1822 		return AMD_FAN_CTRL_AUTO;
1823 }
1824 
vega12_get_dal_power_level(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * info)1825 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1826 		struct amd_pp_simple_clock_info *info)
1827 {
1828 #if 0
1829 	struct phm_ppt_v2_information *table_info =
1830 			(struct phm_ppt_v2_information *)hwmgr->pptable;
1831 	struct phm_clock_and_voltage_limits *max_limits =
1832 			&table_info->max_clock_voltage_on_ac;
1833 
1834 	info->engine_max_clock = max_limits->sclk;
1835 	info->memory_max_clock = max_limits->mclk;
1836 #endif
1837 	return 0;
1838 }
1839 
vega12_get_clock_ranges(struct pp_hwmgr * hwmgr,uint32_t * clock,PPCLK_e clock_select,bool max)1840 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1841 		uint32_t *clock,
1842 		PPCLK_e clock_select,
1843 		bool max)
1844 {
1845 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1846 
1847 	if (max)
1848 		*clock = data->clk_range[clock_select].ACMax;
1849 	else
1850 		*clock = data->clk_range[clock_select].ACMin;
1851 
1852 	return 0;
1853 }
1854 
vega12_get_sclks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1855 static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1856 		struct pp_clock_levels_with_latency *clocks)
1857 {
1858 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1859 	uint32_t ucount;
1860 	int i;
1861 	struct vega12_single_dpm_table *dpm_table;
1862 
1863 	if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1864 		return -1;
1865 
1866 	dpm_table = &(data->dpm_table.gfx_table);
1867 	ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1868 		MAX_NUM_CLOCKS : dpm_table->count;
1869 
1870 	for (i = 0; i < ucount; i++) {
1871 		clocks->data[i].clocks_in_khz =
1872 			dpm_table->dpm_levels[i].value * 1000;
1873 
1874 		clocks->data[i].latency_in_us = 0;
1875 	}
1876 
1877 	clocks->num_levels = ucount;
1878 
1879 	return 0;
1880 }
1881 
vega12_get_mem_latency(struct pp_hwmgr * hwmgr,uint32_t clock)1882 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1883 		uint32_t clock)
1884 {
1885 	return 25;
1886 }
1887 
vega12_get_memclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1888 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1889 		struct pp_clock_levels_with_latency *clocks)
1890 {
1891 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1892 	uint32_t ucount;
1893 	int i;
1894 	struct vega12_single_dpm_table *dpm_table;
1895 	if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1896 		return -1;
1897 
1898 	dpm_table = &(data->dpm_table.mem_table);
1899 	ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1900 		MAX_NUM_CLOCKS : dpm_table->count;
1901 
1902 	for (i = 0; i < ucount; i++) {
1903 		clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1904 		data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1905 		clocks->data[i].latency_in_us =
1906 			data->mclk_latency_table.entries[i].latency =
1907 			vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1908 	}
1909 
1910 	clocks->num_levels = data->mclk_latency_table.count = ucount;
1911 
1912 	return 0;
1913 }
1914 
vega12_get_dcefclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1915 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1916 		struct pp_clock_levels_with_latency *clocks)
1917 {
1918 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1919 	uint32_t ucount;
1920 	int i;
1921 	struct vega12_single_dpm_table *dpm_table;
1922 
1923 	if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1924 		return -1;
1925 
1926 
1927 	dpm_table = &(data->dpm_table.dcef_table);
1928 	ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1929 		MAX_NUM_CLOCKS : dpm_table->count;
1930 
1931 	for (i = 0; i < ucount; i++) {
1932 		clocks->data[i].clocks_in_khz =
1933 			dpm_table->dpm_levels[i].value * 1000;
1934 
1935 		clocks->data[i].latency_in_us = 0;
1936 	}
1937 
1938 	clocks->num_levels = ucount;
1939 
1940 	return 0;
1941 }
1942 
vega12_get_socclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1943 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1944 		struct pp_clock_levels_with_latency *clocks)
1945 {
1946 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1947 	uint32_t ucount;
1948 	int i;
1949 	struct vega12_single_dpm_table *dpm_table;
1950 
1951 	if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1952 		return -1;
1953 
1954 
1955 	dpm_table = &(data->dpm_table.soc_table);
1956 	ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1957 		MAX_NUM_CLOCKS : dpm_table->count;
1958 
1959 	for (i = 0; i < ucount; i++) {
1960 		clocks->data[i].clocks_in_khz =
1961 			dpm_table->dpm_levels[i].value * 1000;
1962 
1963 		clocks->data[i].latency_in_us = 0;
1964 	}
1965 
1966 	clocks->num_levels = ucount;
1967 
1968 	return 0;
1969 
1970 }
1971 
vega12_get_clock_by_type_with_latency(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)1972 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1973 		enum amd_pp_clock_type type,
1974 		struct pp_clock_levels_with_latency *clocks)
1975 {
1976 	int ret;
1977 
1978 	switch (type) {
1979 	case amd_pp_sys_clock:
1980 		ret = vega12_get_sclks(hwmgr, clocks);
1981 		break;
1982 	case amd_pp_mem_clock:
1983 		ret = vega12_get_memclocks(hwmgr, clocks);
1984 		break;
1985 	case amd_pp_dcef_clock:
1986 		ret = vega12_get_dcefclocks(hwmgr, clocks);
1987 		break;
1988 	case amd_pp_soc_clock:
1989 		ret = vega12_get_socclocks(hwmgr, clocks);
1990 		break;
1991 	default:
1992 		return -EINVAL;
1993 	}
1994 
1995 	return ret;
1996 }
1997 
vega12_get_clock_by_type_with_voltage(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)1998 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1999 		enum amd_pp_clock_type type,
2000 		struct pp_clock_levels_with_voltage *clocks)
2001 {
2002 	clocks->num_levels = 0;
2003 
2004 	return 0;
2005 }
2006 
vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr * hwmgr,void * clock_ranges)2007 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2008 							void *clock_ranges)
2009 {
2010 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2011 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2012 	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2013 
2014 	if (!data->registry_data.disable_water_mark &&
2015 			data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2016 			data->smu_features[GNLD_DPM_SOCCLK].supported) {
2017 		smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2018 		data->water_marks_bitmap |= WaterMarksExist;
2019 		data->water_marks_bitmap &= ~WaterMarksLoaded;
2020 	}
2021 
2022 	return 0;
2023 }
2024 
vega12_force_clock_level(struct pp_hwmgr * hwmgr,enum pp_clock_type type,uint32_t mask)2025 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
2026 		enum pp_clock_type type, uint32_t mask)
2027 {
2028 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2029 	uint32_t soft_min_level, soft_max_level, hard_min_level;
2030 	int ret = 0;
2031 
2032 	switch (type) {
2033 	case PP_SCLK:
2034 		soft_min_level = mask ? (ffs(mask) - 1) : 0;
2035 		soft_max_level = mask ? (fls(mask) - 1) : 0;
2036 
2037 		data->dpm_table.gfx_table.dpm_state.soft_min_level =
2038 			data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2039 		data->dpm_table.gfx_table.dpm_state.soft_max_level =
2040 			data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2041 
2042 		ret = vega12_upload_dpm_min_level(hwmgr);
2043 		PP_ASSERT_WITH_CODE(!ret,
2044 			"Failed to upload boot level to lowest!",
2045 			return ret);
2046 
2047 		ret = vega12_upload_dpm_max_level(hwmgr);
2048 		PP_ASSERT_WITH_CODE(!ret,
2049 			"Failed to upload dpm max level to highest!",
2050 			return ret);
2051 		break;
2052 
2053 	case PP_MCLK:
2054 		soft_min_level = mask ? (ffs(mask) - 1) : 0;
2055 		soft_max_level = mask ? (fls(mask) - 1) : 0;
2056 
2057 		data->dpm_table.mem_table.dpm_state.soft_min_level =
2058 			data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2059 		data->dpm_table.mem_table.dpm_state.soft_max_level =
2060 			data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2061 
2062 		ret = vega12_upload_dpm_min_level(hwmgr);
2063 		PP_ASSERT_WITH_CODE(!ret,
2064 			"Failed to upload boot level to lowest!",
2065 			return ret);
2066 
2067 		ret = vega12_upload_dpm_max_level(hwmgr);
2068 		PP_ASSERT_WITH_CODE(!ret,
2069 			"Failed to upload dpm max level to highest!",
2070 			return ret);
2071 
2072 		break;
2073 
2074 	case PP_SOCCLK:
2075 		soft_min_level = mask ? (ffs(mask) - 1) : 0;
2076 		soft_max_level = mask ? (fls(mask) - 1) : 0;
2077 
2078 		if (soft_max_level >= data->dpm_table.soc_table.count) {
2079 			pr_err("Clock level specified %d is over max allowed %d\n",
2080 					soft_max_level,
2081 					data->dpm_table.soc_table.count - 1);
2082 			return -EINVAL;
2083 		}
2084 
2085 		data->dpm_table.soc_table.dpm_state.soft_min_level =
2086 			data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2087 		data->dpm_table.soc_table.dpm_state.soft_max_level =
2088 			data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2089 
2090 		ret = vega12_upload_dpm_min_level(hwmgr);
2091 		PP_ASSERT_WITH_CODE(!ret,
2092 			"Failed to upload boot level to lowest!",
2093 			return ret);
2094 
2095 		ret = vega12_upload_dpm_max_level(hwmgr);
2096 		PP_ASSERT_WITH_CODE(!ret,
2097 			"Failed to upload dpm max level to highest!",
2098 			return ret);
2099 
2100 		break;
2101 
2102 	case PP_DCEFCLK:
2103 		hard_min_level = mask ? (ffs(mask) - 1) : 0;
2104 
2105 		if (hard_min_level >= data->dpm_table.dcef_table.count) {
2106 			pr_err("Clock level specified %d is over max allowed %d\n",
2107 					hard_min_level,
2108 					data->dpm_table.dcef_table.count - 1);
2109 			return -EINVAL;
2110 		}
2111 
2112 		data->dpm_table.dcef_table.dpm_state.hard_min_level =
2113 			data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2114 
2115 		ret = vega12_upload_dpm_min_level(hwmgr);
2116 		PP_ASSERT_WITH_CODE(!ret,
2117 			"Failed to upload boot level to lowest!",
2118 			return ret);
2119 
2120 		//TODO: Setting DCEFCLK max dpm level is not supported
2121 
2122 		break;
2123 
2124 	case PP_PCIE:
2125 		break;
2126 
2127 	default:
2128 		break;
2129 	}
2130 
2131 	return 0;
2132 }
2133 
vega12_get_ppfeature_status(struct pp_hwmgr * hwmgr,char * buf)2134 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
2135 {
2136 	static const char *ppfeature_name[] = {
2137 			"DPM_PREFETCHER",
2138 			"GFXCLK_DPM",
2139 			"UCLK_DPM",
2140 			"SOCCLK_DPM",
2141 			"UVD_DPM",
2142 			"VCE_DPM",
2143 			"ULV",
2144 			"MP0CLK_DPM",
2145 			"LINK_DPM",
2146 			"DCEFCLK_DPM",
2147 			"GFXCLK_DS",
2148 			"SOCCLK_DS",
2149 			"LCLK_DS",
2150 			"PPT",
2151 			"TDC",
2152 			"THERMAL",
2153 			"GFX_PER_CU_CG",
2154 			"RM",
2155 			"DCEFCLK_DS",
2156 			"ACDC",
2157 			"VR0HOT",
2158 			"VR1HOT",
2159 			"FW_CTF",
2160 			"LED_DISPLAY",
2161 			"FAN_CONTROL",
2162 			"DIDT",
2163 			"GFXOFF",
2164 			"CG",
2165 			"ACG"};
2166 	static const char *output_title[] = {
2167 			"FEATURES",
2168 			"BITMASK",
2169 			"ENABLEMENT"};
2170 	uint64_t features_enabled;
2171 	int i;
2172 	int ret = 0;
2173 	int size = 0;
2174 
2175 	phm_get_sysfs_buf(&buf, &size);
2176 
2177 	ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2178 	PP_ASSERT_WITH_CODE(!ret,
2179 		"[EnableAllSmuFeatures] Failed to get enabled smc features!",
2180 		return ret);
2181 
2182 	size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2183 	size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
2184 				output_title[0],
2185 				output_title[1],
2186 				output_title[2]);
2187 	for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2188 		size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
2189 				ppfeature_name[i],
2190 				1ULL << i,
2191 				(features_enabled & (1ULL << i)) ? "Y" : "N");
2192 	}
2193 
2194 	return size;
2195 }
2196 
vega12_set_ppfeature_status(struct pp_hwmgr * hwmgr,uint64_t new_ppfeature_masks)2197 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
2198 {
2199 	uint64_t features_enabled;
2200 	uint64_t features_to_enable;
2201 	uint64_t features_to_disable;
2202 	int ret = 0;
2203 
2204 	if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2205 		return -EINVAL;
2206 
2207 	ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2208 	if (ret)
2209 		return ret;
2210 
2211 	features_to_disable =
2212 		features_enabled & ~new_ppfeature_masks;
2213 	features_to_enable =
2214 		~features_enabled & new_ppfeature_masks;
2215 
2216 	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2217 	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2218 
2219 	if (features_to_disable) {
2220 		ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
2221 		if (ret)
2222 			return ret;
2223 	}
2224 
2225 	if (features_to_enable) {
2226 		ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
2227 		if (ret)
2228 			return ret;
2229 	}
2230 
2231 	return 0;
2232 }
2233 
vega12_get_current_pcie_link_width_level(struct pp_hwmgr * hwmgr)2234 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
2235 {
2236 	struct amdgpu_device *adev = hwmgr->adev;
2237 
2238 	return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2239 		PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2240 		>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2241 }
2242 
vega12_get_current_pcie_link_width(struct pp_hwmgr * hwmgr)2243 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
2244 {
2245 	uint32_t width_level;
2246 
2247 	width_level = vega12_get_current_pcie_link_width_level(hwmgr);
2248 	if (width_level > LINK_WIDTH_MAX)
2249 		width_level = 0;
2250 
2251 	return link_width[width_level];
2252 }
2253 
vega12_get_current_pcie_link_speed_level(struct pp_hwmgr * hwmgr)2254 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
2255 {
2256 	struct amdgpu_device *adev = hwmgr->adev;
2257 
2258 	return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2259 		PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2260 		>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2261 }
2262 
vega12_get_current_pcie_link_speed(struct pp_hwmgr * hwmgr)2263 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
2264 {
2265 	uint32_t speed_level;
2266 
2267 	speed_level = vega12_get_current_pcie_link_speed_level(hwmgr);
2268 	if (speed_level > LINK_SPEED_MAX)
2269 		speed_level = 0;
2270 
2271 	return link_speed[speed_level];
2272 }
2273 
vega12_print_clock_levels(struct pp_hwmgr * hwmgr,enum pp_clock_type type,char * buf)2274 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
2275 		enum pp_clock_type type, char *buf)
2276 {
2277 	int i, now, size = 0;
2278 	struct pp_clock_levels_with_latency clocks;
2279 
2280 	switch (type) {
2281 	case PP_SCLK:
2282 		PP_ASSERT_WITH_CODE(
2283 				vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
2284 				"Attempt to get current gfx clk Failed!",
2285 				return -1);
2286 
2287 		PP_ASSERT_WITH_CODE(
2288 				vega12_get_sclks(hwmgr, &clocks) == 0,
2289 				"Attempt to get gfx clk levels Failed!",
2290 				return -1);
2291 		for (i = 0; i < clocks.num_levels; i++)
2292 			size += sprintf(buf + size, "%d: %uMhz %s\n",
2293 				i, clocks.data[i].clocks_in_khz / 1000,
2294 				(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2295 		break;
2296 
2297 	case PP_MCLK:
2298 		PP_ASSERT_WITH_CODE(
2299 				vega12_get_current_mclk_freq(hwmgr, &now) == 0,
2300 				"Attempt to get current mclk freq Failed!",
2301 				return -1);
2302 
2303 		PP_ASSERT_WITH_CODE(
2304 				vega12_get_memclocks(hwmgr, &clocks) == 0,
2305 				"Attempt to get memory clk levels Failed!",
2306 				return -1);
2307 		for (i = 0; i < clocks.num_levels; i++)
2308 			size += sprintf(buf + size, "%d: %uMhz %s\n",
2309 				i, clocks.data[i].clocks_in_khz / 1000,
2310 				(clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2311 		break;
2312 
2313 	case PP_SOCCLK:
2314 		PP_ASSERT_WITH_CODE(
2315 				smum_send_msg_to_smc_with_parameter(hwmgr,
2316 					PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16),
2317 					&now) == 0,
2318 				"Attempt to get Current SOCCLK Frequency Failed!",
2319 				return -EINVAL);
2320 
2321 		PP_ASSERT_WITH_CODE(
2322 				vega12_get_socclocks(hwmgr, &clocks) == 0,
2323 				"Attempt to get soc clk levels Failed!",
2324 				return -1);
2325 		for (i = 0; i < clocks.num_levels; i++)
2326 			size += sprintf(buf + size, "%d: %uMhz %s\n",
2327 				i, clocks.data[i].clocks_in_khz / 1000,
2328 				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2329 		break;
2330 
2331 	case PP_DCEFCLK:
2332 		PP_ASSERT_WITH_CODE(
2333 				smum_send_msg_to_smc_with_parameter(hwmgr,
2334 					PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16),
2335 					&now) == 0,
2336 				"Attempt to get Current DCEFCLK Frequency Failed!",
2337 				return -EINVAL);
2338 
2339 		PP_ASSERT_WITH_CODE(
2340 				vega12_get_dcefclocks(hwmgr, &clocks) == 0,
2341 				"Attempt to get dcef clk levels Failed!",
2342 				return -1);
2343 		for (i = 0; i < clocks.num_levels; i++)
2344 			size += sprintf(buf + size, "%d: %uMhz %s\n",
2345 				i, clocks.data[i].clocks_in_khz / 1000,
2346 				(clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2347 		break;
2348 
2349 	case PP_PCIE:
2350 		break;
2351 
2352 	default:
2353 		break;
2354 	}
2355 	return size;
2356 }
2357 
vega12_apply_clocks_adjust_rules(struct pp_hwmgr * hwmgr)2358 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2359 {
2360 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2361 	struct vega12_single_dpm_table *dpm_table;
2362 	bool vblank_too_short = false;
2363 	bool disable_mclk_switching;
2364 	uint32_t i, latency;
2365 
2366 	disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2367 				!hwmgr->display_config->multi_monitor_in_sync) ||
2368 				vblank_too_short;
2369 	latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2370 
2371 	/* gfxclk */
2372 	dpm_table = &(data->dpm_table.gfx_table);
2373 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2374 	dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2375 	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2376 	dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2377 
2378 	if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2379 		if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2380 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2381 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2382 		}
2383 
2384 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2385 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2386 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2387 		}
2388 
2389 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2390 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2391 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2392 		}
2393 	}
2394 
2395 	/* memclk */
2396 	dpm_table = &(data->dpm_table.mem_table);
2397 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2398 	dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2399 	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2400 	dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2401 
2402 	if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2403 		if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2404 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2405 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2406 		}
2407 
2408 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2409 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2410 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2411 		}
2412 
2413 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2414 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2415 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2416 		}
2417 	}
2418 
2419 	/* honour DAL's UCLK Hardmin */
2420 	if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
2421 		dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
2422 
2423 	/* Hardmin is dependent on displayconfig */
2424 	if (disable_mclk_switching) {
2425 		dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2426 		for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
2427 			if (data->mclk_latency_table.entries[i].latency <= latency) {
2428 				if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
2429 					dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2430 					break;
2431 				}
2432 			}
2433 		}
2434 	}
2435 
2436 	if (hwmgr->display_config->nb_pstate_switch_disable)
2437 		dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2438 
2439 	/* vclk */
2440 	dpm_table = &(data->dpm_table.vclk_table);
2441 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2442 	dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2443 	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2444 	dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2445 
2446 	if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2447 		if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2448 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2449 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2450 		}
2451 
2452 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2453 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2454 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2455 		}
2456 	}
2457 
2458 	/* dclk */
2459 	dpm_table = &(data->dpm_table.dclk_table);
2460 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2461 	dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2462 	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2463 	dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2464 
2465 	if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2466 		if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2467 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2468 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2469 		}
2470 
2471 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2472 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2473 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2474 		}
2475 	}
2476 
2477 	/* socclk */
2478 	dpm_table = &(data->dpm_table.soc_table);
2479 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2480 	dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2481 	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2482 	dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2483 
2484 	if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2485 		if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2486 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2487 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2488 		}
2489 
2490 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2491 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2492 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2493 		}
2494 	}
2495 
2496 	/* eclk */
2497 	dpm_table = &(data->dpm_table.eclk_table);
2498 	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2499 	dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2500 	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2501 	dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2502 
2503 	if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2504 		if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2505 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2506 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2507 		}
2508 
2509 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2510 			dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2511 			dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2512 		}
2513 	}
2514 
2515 	return 0;
2516 }
2517 
vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr * hwmgr,struct vega12_single_dpm_table * dpm_table)2518 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2519 		struct vega12_single_dpm_table *dpm_table)
2520 {
2521 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2522 	int ret = 0;
2523 
2524 	if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2525 		PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2526 				"[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2527 				return -EINVAL);
2528 		PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2529 				"[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2530 				return -EINVAL);
2531 
2532 		dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2533 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2534 				PPSMC_MSG_SetHardMinByFreq,
2535 				(PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
2536 				NULL)),
2537 				"[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2538 				return ret);
2539 	}
2540 
2541 	return ret;
2542 }
2543 
vega12_pre_display_configuration_changed_task(struct pp_hwmgr * hwmgr)2544 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2545 {
2546 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2547 	int ret = 0;
2548 
2549 	smum_send_msg_to_smc_with_parameter(hwmgr,
2550 			PPSMC_MSG_NumOfDisplays, 0,
2551 			NULL);
2552 
2553 	ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2554 			&data->dpm_table.mem_table);
2555 
2556 	return ret;
2557 }
2558 
vega12_display_configuration_changed_task(struct pp_hwmgr * hwmgr)2559 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2560 {
2561 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2562 	int result = 0;
2563 	Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2564 
2565 	if ((data->water_marks_bitmap & WaterMarksExist) &&
2566 			!(data->water_marks_bitmap & WaterMarksLoaded)) {
2567 		result = smum_smc_table_manager(hwmgr,
2568 						(uint8_t *)wm_table, TABLE_WATERMARKS, false);
2569 		PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
2570 		data->water_marks_bitmap |= WaterMarksLoaded;
2571 	}
2572 
2573 	if ((data->water_marks_bitmap & WaterMarksExist) &&
2574 		data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2575 		data->smu_features[GNLD_DPM_SOCCLK].supported)
2576 		smum_send_msg_to_smc_with_parameter(hwmgr,
2577 			PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
2578 			NULL);
2579 
2580 	return result;
2581 }
2582 
vega12_enable_disable_uvd_dpm(struct pp_hwmgr * hwmgr,bool enable)2583 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2584 {
2585 	struct vega12_hwmgr *data =
2586 			(struct vega12_hwmgr *)(hwmgr->backend);
2587 
2588 	if (data->smu_features[GNLD_DPM_UVD].supported) {
2589 		PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2590 				enable,
2591 				data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2592 				"Attempt to Enable/Disable DPM UVD Failed!",
2593 				return -1);
2594 		data->smu_features[GNLD_DPM_UVD].enabled = enable;
2595 	}
2596 
2597 	return 0;
2598 }
2599 
vega12_power_gate_vce(struct pp_hwmgr * hwmgr,bool bgate)2600 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2601 {
2602 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2603 
2604 	if (data->vce_power_gated == bgate)
2605 		return;
2606 
2607 	data->vce_power_gated = bgate;
2608 	vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2609 }
2610 
vega12_power_gate_uvd(struct pp_hwmgr * hwmgr,bool bgate)2611 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2612 {
2613 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2614 
2615 	if (data->uvd_power_gated == bgate)
2616 		return;
2617 
2618 	data->uvd_power_gated = bgate;
2619 	vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2620 }
2621 
2622 static bool
vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr * hwmgr)2623 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2624 {
2625 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2626 	bool is_update_required = false;
2627 
2628 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2629 		is_update_required = true;
2630 
2631 	if (data->registry_data.gfx_clk_deep_sleep_support) {
2632 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2633 			is_update_required = true;
2634 	}
2635 
2636 	return is_update_required;
2637 }
2638 
vega12_disable_dpm_tasks(struct pp_hwmgr * hwmgr)2639 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2640 {
2641 	int tmp_result, result = 0;
2642 
2643 	tmp_result = vega12_disable_all_smu_features(hwmgr);
2644 	PP_ASSERT_WITH_CODE((tmp_result == 0),
2645 			"Failed to disable all smu features!", result = tmp_result);
2646 
2647 	return result;
2648 }
2649 
vega12_power_off_asic(struct pp_hwmgr * hwmgr)2650 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2651 {
2652 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2653 	int result;
2654 
2655 	result = vega12_disable_dpm_tasks(hwmgr);
2656 	PP_ASSERT_WITH_CODE((0 == result),
2657 			"[disable_dpm_tasks] Failed to disable DPM!",
2658 			);
2659 	data->water_marks_bitmap &= ~(WaterMarksLoaded);
2660 
2661 	return result;
2662 }
2663 
2664 #if 0
2665 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2666 		uint32_t *sclk_idx, uint32_t *mclk_idx,
2667 		uint32_t min_sclk, uint32_t min_mclk)
2668 {
2669 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2670 	struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2671 	uint32_t i;
2672 
2673 	for (i = 0; i < dpm_table->gfx_table.count; i++) {
2674 		if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2675 			dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2676 			*sclk_idx = i;
2677 			break;
2678 		}
2679 	}
2680 
2681 	for (i = 0; i < dpm_table->mem_table.count; i++) {
2682 		if (dpm_table->mem_table.dpm_levels[i].enabled &&
2683 			dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2684 			*mclk_idx = i;
2685 			break;
2686 		}
2687 	}
2688 }
2689 #endif
2690 
2691 #if 0
2692 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2693 		struct amd_pp_profile *request)
2694 {
2695 	return 0;
2696 }
2697 
2698 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2699 {
2700 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2701 	struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2702 	struct vega12_single_dpm_table *golden_sclk_table =
2703 			&(data->golden_dpm_table.gfx_table);
2704 	int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2705 	int golden_value = golden_sclk_table->dpm_levels
2706 			[golden_sclk_table->count - 1].value;
2707 
2708 	value -= golden_value;
2709 	value = DIV_ROUND_UP(value * 100, golden_value);
2710 
2711 	return value;
2712 }
2713 
2714 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2715 {
2716 	return 0;
2717 }
2718 
2719 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2720 {
2721 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2722 	struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2723 	struct vega12_single_dpm_table *golden_mclk_table =
2724 			&(data->golden_dpm_table.mem_table);
2725 	int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2726 	int golden_value = golden_mclk_table->dpm_levels
2727 			[golden_mclk_table->count - 1].value;
2728 
2729 	value -= golden_value;
2730 	value = DIV_ROUND_UP(value * 100, golden_value);
2731 
2732 	return value;
2733 }
2734 
2735 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2736 {
2737 	return 0;
2738 }
2739 #endif
2740 
vega12_notify_cac_buffer_info(struct pp_hwmgr * hwmgr,uint32_t virtual_addr_low,uint32_t virtual_addr_hi,uint32_t mc_addr_low,uint32_t mc_addr_hi,uint32_t size)2741 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2742 					uint32_t virtual_addr_low,
2743 					uint32_t virtual_addr_hi,
2744 					uint32_t mc_addr_low,
2745 					uint32_t mc_addr_hi,
2746 					uint32_t size)
2747 {
2748 	smum_send_msg_to_smc_with_parameter(hwmgr,
2749 					PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2750 					virtual_addr_hi,
2751 					NULL);
2752 	smum_send_msg_to_smc_with_parameter(hwmgr,
2753 					PPSMC_MSG_SetSystemVirtualDramAddrLow,
2754 					virtual_addr_low,
2755 					NULL);
2756 	smum_send_msg_to_smc_with_parameter(hwmgr,
2757 					PPSMC_MSG_DramLogSetDramAddrHigh,
2758 					mc_addr_hi,
2759 					NULL);
2760 
2761 	smum_send_msg_to_smc_with_parameter(hwmgr,
2762 					PPSMC_MSG_DramLogSetDramAddrLow,
2763 					mc_addr_low,
2764 					NULL);
2765 
2766 	smum_send_msg_to_smc_with_parameter(hwmgr,
2767 					PPSMC_MSG_DramLogSetDramSize,
2768 					size,
2769 					NULL);
2770 	return 0;
2771 }
2772 
vega12_get_thermal_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * thermal_data)2773 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2774 		struct PP_TemperatureRange *thermal_data)
2775 {
2776 	struct phm_ppt_v3_information *pptable_information =
2777 		(struct phm_ppt_v3_information *)hwmgr->pptable;
2778 	struct vega12_hwmgr *data =
2779 			(struct vega12_hwmgr *)(hwmgr->backend);
2780 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2781 
2782 	memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2783 
2784 	thermal_data->max = pp_table->TedgeLimit *
2785 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2786 	thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
2787 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2788 	thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
2789 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2790 	thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2791 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2792 	thermal_data->mem_crit_max = pp_table->ThbmLimit *
2793 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2794 	thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
2795 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2796 	thermal_data->sw_ctf_threshold = pptable_information->us_software_shutdown_temp *
2797 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2798 
2799 	return 0;
2800 }
2801 
vega12_enable_gfx_off(struct pp_hwmgr * hwmgr)2802 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2803 {
2804 	struct vega12_hwmgr *data =
2805 			(struct vega12_hwmgr *)(hwmgr->backend);
2806 	int ret = 0;
2807 
2808 	if (data->gfxoff_controlled_by_driver)
2809 		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL);
2810 
2811 	return ret;
2812 }
2813 
vega12_disable_gfx_off(struct pp_hwmgr * hwmgr)2814 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2815 {
2816 	struct vega12_hwmgr *data =
2817 			(struct vega12_hwmgr *)(hwmgr->backend);
2818 	int ret = 0;
2819 
2820 	if (data->gfxoff_controlled_by_driver)
2821 		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL);
2822 
2823 	return ret;
2824 }
2825 
vega12_gfx_off_control(struct pp_hwmgr * hwmgr,bool enable)2826 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2827 {
2828 	if (enable)
2829 		return vega12_enable_gfx_off(hwmgr);
2830 	else
2831 		return vega12_disable_gfx_off(hwmgr);
2832 }
2833 
vega12_get_performance_level(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,PHM_PerformanceLevelDesignation designation,uint32_t index,PHM_PerformanceLevel * level)2834 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2835 				PHM_PerformanceLevelDesignation designation, uint32_t index,
2836 				PHM_PerformanceLevel *level)
2837 {
2838 	return 0;
2839 }
2840 
vega12_set_mp1_state(struct pp_hwmgr * hwmgr,enum pp_mp1_state mp1_state)2841 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
2842 				enum pp_mp1_state mp1_state)
2843 {
2844 	uint16_t msg;
2845 	int ret;
2846 
2847 	switch (mp1_state) {
2848 	case PP_MP1_STATE_UNLOAD:
2849 		msg = PPSMC_MSG_PrepareMp1ForUnload;
2850 		break;
2851 	case PP_MP1_STATE_SHUTDOWN:
2852 	case PP_MP1_STATE_RESET:
2853 	case PP_MP1_STATE_NONE:
2854 	default:
2855 		return 0;
2856 	}
2857 
2858 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
2859 			    "[PrepareMp1] Failed!",
2860 			    return ret);
2861 
2862 	return 0;
2863 }
2864 
vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 * gpu_metrics)2865 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2866 {
2867 	memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2868 
2869 	gpu_metrics->common_header.structure_size =
2870 				sizeof(struct gpu_metrics_v1_0);
2871 	gpu_metrics->common_header.format_revision = 1;
2872 	gpu_metrics->common_header.content_revision = 0;
2873 
2874 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2875 }
2876 
vega12_get_gpu_metrics(struct pp_hwmgr * hwmgr,void ** table)2877 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr,
2878 				      void **table)
2879 {
2880 	struct vega12_hwmgr *data =
2881 			(struct vega12_hwmgr *)(hwmgr->backend);
2882 	struct gpu_metrics_v1_0 *gpu_metrics =
2883 			&data->gpu_metrics_table;
2884 	SmuMetrics_t metrics;
2885 	uint32_t fan_speed_rpm;
2886 	int ret;
2887 
2888 	ret = vega12_get_metrics_table(hwmgr, &metrics, true);
2889 	if (ret)
2890 		return ret;
2891 
2892 	vega12_init_gpu_metrics_v1_0(gpu_metrics);
2893 
2894 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2895 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2896 	gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2897 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2898 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2899 
2900 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2901 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2902 
2903 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2904 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2905 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2906 
2907 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2908 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2909 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2910 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2911 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2912 
2913 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2914 
2915 	vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
2916 	gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
2917 
2918 	gpu_metrics->pcie_link_width =
2919 			vega12_get_current_pcie_link_width(hwmgr);
2920 	gpu_metrics->pcie_link_speed =
2921 			vega12_get_current_pcie_link_speed(hwmgr);
2922 
2923 	*table = (void *)gpu_metrics;
2924 
2925 	return sizeof(struct gpu_metrics_v1_0);
2926 }
2927 
2928 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2929 	.backend_init = vega12_hwmgr_backend_init,
2930 	.backend_fini = vega12_hwmgr_backend_fini,
2931 	.asic_setup = vega12_setup_asic_task,
2932 	.dynamic_state_management_enable = vega12_enable_dpm_tasks,
2933 	.dynamic_state_management_disable = vega12_disable_dpm_tasks,
2934 	.patch_boot_state = vega12_patch_boot_state,
2935 	.get_sclk = vega12_dpm_get_sclk,
2936 	.get_mclk = vega12_dpm_get_mclk,
2937 	.notify_smc_display_config_after_ps_adjustment =
2938 			vega12_notify_smc_display_config_after_ps_adjustment,
2939 	.force_dpm_level = vega12_dpm_force_dpm_level,
2940 	.stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2941 	.get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2942 	.reset_fan_speed_to_default =
2943 			vega12_fan_ctrl_reset_fan_speed_to_default,
2944 	.get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2945 	.set_fan_control_mode = vega12_set_fan_control_mode,
2946 	.get_fan_control_mode = vega12_get_fan_control_mode,
2947 	.read_sensor = vega12_read_sensor,
2948 	.get_dal_power_level = vega12_get_dal_power_level,
2949 	.get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2950 	.get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2951 	.set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2952 	.display_clock_voltage_request = vega12_display_clock_voltage_request,
2953 	.force_clock_level = vega12_force_clock_level,
2954 	.print_clock_levels = vega12_print_clock_levels,
2955 	.apply_clocks_adjust_rules =
2956 		vega12_apply_clocks_adjust_rules,
2957 	.pre_display_config_changed =
2958 		vega12_pre_display_configuration_changed_task,
2959 	.display_config_changed = vega12_display_configuration_changed_task,
2960 	.powergate_uvd = vega12_power_gate_uvd,
2961 	.powergate_vce = vega12_power_gate_vce,
2962 	.check_smc_update_required_for_display_configuration =
2963 			vega12_check_smc_update_required_for_display_configuration,
2964 	.power_off_asic = vega12_power_off_asic,
2965 	.disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2966 #if 0
2967 	.set_power_profile_state = vega12_set_power_profile_state,
2968 	.get_sclk_od = vega12_get_sclk_od,
2969 	.set_sclk_od = vega12_set_sclk_od,
2970 	.get_mclk_od = vega12_get_mclk_od,
2971 	.set_mclk_od = vega12_set_mclk_od,
2972 #endif
2973 	.notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2974 	.get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2975 	.register_irq_handlers = smu9_register_irq_handlers,
2976 	.start_thermal_controller = vega12_start_thermal_controller,
2977 	.powergate_gfx = vega12_gfx_off_control,
2978 	.get_performance_level = vega12_get_performance_level,
2979 	.get_asic_baco_capability = smu9_baco_get_capability,
2980 	.get_asic_baco_state = smu9_baco_get_state,
2981 	.set_asic_baco_state = vega12_baco_set_state,
2982 	.get_ppfeature_status = vega12_get_ppfeature_status,
2983 	.set_ppfeature_status = vega12_set_ppfeature_status,
2984 	.set_mp1_state = vega12_set_mp1_state,
2985 	.get_gpu_metrics = vega12_get_gpu_metrics,
2986 };
2987 
vega12_hwmgr_init(struct pp_hwmgr * hwmgr)2988 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2989 {
2990 	hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2991 	hwmgr->pptable_func = &vega12_pptable_funcs;
2992 
2993 	return 0;
2994 }
2995