1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2018 BayLibre, SAS
4  * Author: Maxime Jourdan <mjourdan@baylibre.com>
5  *
6  * VDEC_1 is a video decoding block that allows decoding of
7  * MPEG 1/2/4, H.263, H.264, MJPEG, VC1
8  */
9 
10 #include <linux/firmware.h>
11 #include <linux/clk.h>
12 
13 #include "vdec_1.h"
14 #include "vdec_helpers.h"
15 #include "dos_regs.h"
16 
17 /* AO Registers */
18 #define AO_RTI_GEN_PWR_SLEEP0	0xe8
19 #define AO_RTI_GEN_PWR_ISO0	0xec
20 	#define GEN_PWR_VDEC_1 (BIT(3) | BIT(2))
21 	#define GEN_PWR_VDEC_1_SM1 (BIT(1))
22 
23 #define MC_SIZE			(4096 * 4)
24 
25 static int
vdec_1_load_firmware(struct amvdec_session * sess,const char * fwname)26 vdec_1_load_firmware(struct amvdec_session *sess, const char *fwname)
27 {
28 	const struct firmware *fw;
29 	struct amvdec_core *core = sess->core;
30 	struct device *dev = core->dev_dec;
31 	struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
32 	static void *mc_addr;
33 	static dma_addr_t mc_addr_map;
34 	int ret;
35 	u32 i = 1000;
36 
37 	ret = request_firmware(&fw, fwname, dev);
38 	if (ret < 0)
39 		return -EINVAL;
40 
41 	if (fw->size < MC_SIZE) {
42 		dev_err(dev, "Firmware size %zu is too small. Expected %u.\n",
43 			fw->size, MC_SIZE);
44 		ret = -EINVAL;
45 		goto release_firmware;
46 	}
47 
48 	mc_addr = dma_alloc_coherent(core->dev, MC_SIZE,
49 				     &mc_addr_map, GFP_KERNEL);
50 	if (!mc_addr) {
51 		ret = -ENOMEM;
52 		goto release_firmware;
53 	}
54 
55 	memcpy(mc_addr, fw->data, MC_SIZE);
56 
57 	amvdec_write_dos(core, MPSR, 0);
58 	amvdec_write_dos(core, CPSR, 0);
59 
60 	amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31));
61 
62 	amvdec_write_dos(core, IMEM_DMA_ADR, mc_addr_map);
63 	amvdec_write_dos(core, IMEM_DMA_COUNT, MC_SIZE / 4);
64 	amvdec_write_dos(core, IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
65 
66 	while (--i && amvdec_read_dos(core, IMEM_DMA_CTRL) & 0x8000);
67 
68 	if (i == 0) {
69 		dev_err(dev, "Firmware load fail (DMA hang?)\n");
70 		ret = -EINVAL;
71 		goto free_mc;
72 	}
73 
74 	if (codec_ops->load_extended_firmware)
75 		ret = codec_ops->load_extended_firmware(sess,
76 							fw->data + MC_SIZE,
77 							fw->size - MC_SIZE);
78 
79 free_mc:
80 	dma_free_coherent(core->dev, MC_SIZE, mc_addr, mc_addr_map);
81 release_firmware:
82 	release_firmware(fw);
83 	return ret;
84 }
85 
vdec_1_stbuf_power_up(struct amvdec_session * sess)86 static int vdec_1_stbuf_power_up(struct amvdec_session *sess)
87 {
88 	struct amvdec_core *core = sess->core;
89 
90 	amvdec_write_dos(core, VLD_MEM_VIFIFO_CONTROL, 0);
91 	amvdec_write_dos(core, VLD_MEM_VIFIFO_WRAP_COUNT, 0);
92 	amvdec_write_dos(core, POWER_CTL_VLD, BIT(4));
93 
94 	amvdec_write_dos(core, VLD_MEM_VIFIFO_START_PTR, sess->vififo_paddr);
95 	amvdec_write_dos(core, VLD_MEM_VIFIFO_CURR_PTR, sess->vififo_paddr);
96 	amvdec_write_dos(core, VLD_MEM_VIFIFO_END_PTR,
97 			 sess->vififo_paddr + sess->vififo_size - 8);
98 
99 	amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);
100 	amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);
101 
102 	amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_MANUAL);
103 	amvdec_write_dos(core, VLD_MEM_VIFIFO_WP, sess->vififo_paddr);
104 
105 	amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
106 	amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
107 
108 	amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL,
109 			      (0x11 << MEM_FIFO_CNT_BIT) | MEM_FILL_ON_LEVEL |
110 			      MEM_CTRL_FILL_EN | MEM_CTRL_EMPTY_EN);
111 
112 	return 0;
113 }
114 
vdec_1_conf_esparser(struct amvdec_session * sess)115 static void vdec_1_conf_esparser(struct amvdec_session *sess)
116 {
117 	struct amvdec_core *core = sess->core;
118 
119 	/* VDEC_1 specific ESPARSER stuff */
120 	amvdec_write_dos(core, DOS_GEN_CTRL0, 0);
121 	amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
122 	amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
123 }
124 
vdec_1_vififo_level(struct amvdec_session * sess)125 static u32 vdec_1_vififo_level(struct amvdec_session *sess)
126 {
127 	struct amvdec_core *core = sess->core;
128 
129 	return amvdec_read_dos(core, VLD_MEM_VIFIFO_LEVEL);
130 }
131 
vdec_1_stop(struct amvdec_session * sess)132 static int vdec_1_stop(struct amvdec_session *sess)
133 {
134 	struct amvdec_core *core = sess->core;
135 	struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
136 
137 	amvdec_write_dos(core, MPSR, 0);
138 	amvdec_write_dos(core, CPSR, 0);
139 	amvdec_write_dos(core, ASSIST_MBOX1_MASK, 0);
140 
141 	amvdec_write_dos(core, DOS_SW_RESET0, BIT(12) | BIT(11));
142 	amvdec_write_dos(core, DOS_SW_RESET0, 0);
143 	amvdec_read_dos(core, DOS_SW_RESET0);
144 
145 	/* enable vdec1 isolation */
146 	if (core->platform->revision == VDEC_REVISION_SM1)
147 		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
148 				   GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);
149 	else
150 		regmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0xc0);
151 	/* power off vdec1 memories */
152 	amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0xffffffff);
153 	/* power off vdec1 */
154 	if (core->platform->revision == VDEC_REVISION_SM1)
155 		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
156 				   GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);
157 	else
158 		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
159 				   GEN_PWR_VDEC_1, GEN_PWR_VDEC_1);
160 
161 	clk_disable_unprepare(core->vdec_1_clk);
162 
163 	if (sess->priv)
164 		codec_ops->stop(sess);
165 
166 	return 0;
167 }
168 
vdec_1_start(struct amvdec_session * sess)169 static int vdec_1_start(struct amvdec_session *sess)
170 {
171 	int ret;
172 	struct amvdec_core *core = sess->core;
173 	struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
174 
175 	/* Configure the vdec clk to the maximum available */
176 	clk_set_rate(core->vdec_1_clk, 666666666);
177 	ret = clk_prepare_enable(core->vdec_1_clk);
178 	if (ret)
179 		return ret;
180 
181 	/* Enable power for VDEC_1 */
182 	if (core->platform->revision == VDEC_REVISION_SM1)
183 		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
184 				   GEN_PWR_VDEC_1_SM1, 0);
185 	else
186 		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
187 				   GEN_PWR_VDEC_1, 0);
188 	usleep_range(10, 20);
189 
190 	/* Reset VDEC1 */
191 	amvdec_write_dos(core, DOS_SW_RESET0, 0xfffffffc);
192 	amvdec_write_dos(core, DOS_SW_RESET0, 0x00000000);
193 
194 	amvdec_write_dos(core, DOS_GCLK_EN0, 0x3ff);
195 
196 	/* enable VDEC Memories */
197 	amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0);
198 	/* Remove VDEC1 Isolation */
199 	if (core->platform->revision == VDEC_REVISION_SM1)
200 		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
201 				   GEN_PWR_VDEC_1_SM1, 0);
202 	else
203 		regmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0);
204 	/* Reset DOS top registers */
205 	amvdec_write_dos(core, DOS_VDEC_MCRCC_STALL_CTRL, 0);
206 
207 	amvdec_write_dos(core, GCLK_EN, 0x3ff);
208 	amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31));
209 
210 	vdec_1_stbuf_power_up(sess);
211 
212 	ret = vdec_1_load_firmware(sess, sess->fmt_out->firmware_path);
213 	if (ret)
214 		goto stop;
215 
216 	ret = codec_ops->start(sess);
217 	if (ret)
218 		goto stop;
219 
220 	/* Enable IRQ */
221 	amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
222 	amvdec_write_dos(core, ASSIST_MBOX1_MASK, 1);
223 
224 	/* Enable 2-plane output */
225 	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
226 		amvdec_write_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17));
227 	else
228 		amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17));
229 
230 	/* Enable firmware processor */
231 	amvdec_write_dos(core, MPSR, 1);
232 	/* Let the firmware settle */
233 	usleep_range(10, 20);
234 
235 	return 0;
236 
237 stop:
238 	vdec_1_stop(sess);
239 	return ret;
240 }
241 
242 struct amvdec_ops vdec_1_ops = {
243 	.start = vdec_1_start,
244 	.stop = vdec_1_stop,
245 	.conf_esparser = vdec_1_conf_esparser,
246 	.vififo_level = vdec_1_vififo_level,
247 };
248