1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 */
5
6 /**
7 * DOC: VC4 HVS module.
8 *
9 * The Hardware Video Scaler (HVS) is the piece of hardware that does
10 * translation, scaling, colorspace conversion, and compositing of
11 * pixels stored in framebuffers into a FIFO of pixels going out to
12 * the Pixel Valve (CRTC). It operates at the system clock rate (the
13 * system audio clock gate, specifically), which is much higher than
14 * the pixel clock rate.
15 *
16 * There is a single global HVS, with multiple output FIFOs that can
17 * be consumed by the PVs. This file just manages the resources for
18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
19 * each CRTC.
20 */
21
22 #include <linux/bitfield.h>
23 #include <linux/clk.h>
24 #include <linux/component.h>
25 #include <linux/platform_device.h>
26
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_drv.h>
29 #include <drm/drm_vblank.h>
30
31 #include <soc/bcm2835/raspberrypi-firmware.h>
32
33 #include "vc4_drv.h"
34 #include "vc4_regs.h"
35
36 static const struct debugfs_reg32 hvs_regs[] = {
37 VC4_REG32(SCALER_DISPCTRL),
38 VC4_REG32(SCALER_DISPSTAT),
39 VC4_REG32(SCALER_DISPID),
40 VC4_REG32(SCALER_DISPECTRL),
41 VC4_REG32(SCALER_DISPPROF),
42 VC4_REG32(SCALER_DISPDITHER),
43 VC4_REG32(SCALER_DISPEOLN),
44 VC4_REG32(SCALER_DISPLIST0),
45 VC4_REG32(SCALER_DISPLIST1),
46 VC4_REG32(SCALER_DISPLIST2),
47 VC4_REG32(SCALER_DISPLSTAT),
48 VC4_REG32(SCALER_DISPLACT0),
49 VC4_REG32(SCALER_DISPLACT1),
50 VC4_REG32(SCALER_DISPLACT2),
51 VC4_REG32(SCALER_DISPCTRL0),
52 VC4_REG32(SCALER_DISPBKGND0),
53 VC4_REG32(SCALER_DISPSTAT0),
54 VC4_REG32(SCALER_DISPBASE0),
55 VC4_REG32(SCALER_DISPCTRL1),
56 VC4_REG32(SCALER_DISPBKGND1),
57 VC4_REG32(SCALER_DISPSTAT1),
58 VC4_REG32(SCALER_DISPBASE1),
59 VC4_REG32(SCALER_DISPCTRL2),
60 VC4_REG32(SCALER_DISPBKGND2),
61 VC4_REG32(SCALER_DISPSTAT2),
62 VC4_REG32(SCALER_DISPBASE2),
63 VC4_REG32(SCALER_DISPALPHA2),
64 VC4_REG32(SCALER_OLEDOFFS),
65 VC4_REG32(SCALER_OLEDCOEF0),
66 VC4_REG32(SCALER_OLEDCOEF1),
67 VC4_REG32(SCALER_OLEDCOEF2),
68 };
69
vc4_hvs_dump_state(struct vc4_hvs * hvs)70 void vc4_hvs_dump_state(struct vc4_hvs *hvs)
71 {
72 struct drm_device *drm = &hvs->vc4->base;
73 struct drm_printer p = drm_info_printer(&hvs->pdev->dev);
74 int idx, i;
75
76 if (!drm_dev_enter(drm, &idx))
77 return;
78
79 drm_print_regset32(&p, &hvs->regset);
80
81 DRM_INFO("HVS ctx:\n");
82 for (i = 0; i < 64; i += 4) {
83 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
84 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
85 readl((u32 __iomem *)hvs->dlist + i + 0),
86 readl((u32 __iomem *)hvs->dlist + i + 1),
87 readl((u32 __iomem *)hvs->dlist + i + 2),
88 readl((u32 __iomem *)hvs->dlist + i + 3));
89 }
90
91 drm_dev_exit(idx);
92 }
93
vc4_hvs_debugfs_underrun(struct seq_file * m,void * data)94 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
95 {
96 struct drm_debugfs_entry *entry = m->private;
97 struct drm_device *dev = entry->dev;
98 struct vc4_dev *vc4 = to_vc4_dev(dev);
99 struct drm_printer p = drm_seq_file_printer(m);
100
101 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
102
103 return 0;
104 }
105
vc4_hvs_debugfs_dlist(struct seq_file * m,void * data)106 static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data)
107 {
108 struct drm_debugfs_entry *entry = m->private;
109 struct drm_device *dev = entry->dev;
110 struct vc4_dev *vc4 = to_vc4_dev(dev);
111 struct vc4_hvs *hvs = vc4->hvs;
112 struct drm_printer p = drm_seq_file_printer(m);
113 unsigned int dlist_mem_size = hvs->dlist_mem_size;
114 unsigned int next_entry_start;
115 unsigned int i, j;
116 u32 dlist_word, dispstat;
117
118 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) {
119 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)),
120 SCALER_DISPSTATX_MODE);
121 if (dispstat == SCALER_DISPSTATX_MODE_DISABLED ||
122 dispstat == SCALER_DISPSTATX_MODE_EOF) {
123 drm_printf(&p, "HVS chan %u disabled\n", i);
124 continue;
125 }
126
127 drm_printf(&p, "HVS chan %u:\n", i);
128 next_entry_start = 0;
129
130 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < dlist_mem_size; j++) {
131 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j);
132 drm_printf(&p, "dlist: %02d: 0x%08x\n", j,
133 dlist_word);
134 if (!next_entry_start ||
135 next_entry_start == j) {
136 if (dlist_word & SCALER_CTL0_END)
137 break;
138 next_entry_start = j +
139 VC4_GET_FIELD(dlist_word,
140 SCALER_CTL0_SIZE);
141 }
142 }
143 }
144
145 return 0;
146 }
147
148 /* The filter kernel is composed of dwords each containing 3 9-bit
149 * signed integers packed next to each other.
150 */
151 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
152 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \
153 ((((c0) & 0x1ff) << 0) | \
154 (((c1) & 0x1ff) << 9) | \
155 (((c2) & 0x1ff) << 18))
156
157 /* The whole filter kernel is arranged as the coefficients 0-16 going
158 * up, then a pad, then 17-31 going down and reversed within the
159 * dwords. This means that a linear phase kernel (where it's
160 * symmetrical at the boundary between 15 and 16) has the last 5
161 * dwords matching the first 5, but reversed.
162 */
163 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
164 c9, c10, c11, c12, c13, c14, c15) \
165 {VC4_PPF_FILTER_WORD(c0, c1, c2), \
166 VC4_PPF_FILTER_WORD(c3, c4, c5), \
167 VC4_PPF_FILTER_WORD(c6, c7, c8), \
168 VC4_PPF_FILTER_WORD(c9, c10, c11), \
169 VC4_PPF_FILTER_WORD(c12, c13, c14), \
170 VC4_PPF_FILTER_WORD(c15, c15, 0)}
171
172 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
173 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
174
175 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
176 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
177 */
178 static const u32 mitchell_netravali_1_3_1_3_kernel[] =
179 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
180 50, 82, 119, 155, 187, 213, 227);
181
vc4_hvs_upload_linear_kernel(struct vc4_hvs * hvs,struct drm_mm_node * space,const u32 * kernel)182 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
183 struct drm_mm_node *space,
184 const u32 *kernel)
185 {
186 int ret, i;
187 u32 __iomem *dst_kernel;
188
189 /*
190 * NOTE: We don't need a call to drm_dev_enter()/drm_dev_exit()
191 * here since that function is only called from vc4_hvs_bind().
192 */
193
194 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
195 if (ret) {
196 DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
197 ret);
198 return ret;
199 }
200
201 dst_kernel = hvs->dlist + space->start;
202
203 for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
204 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
205 writel(kernel[i], &dst_kernel[i]);
206 else {
207 writel(kernel[VC4_KERNEL_DWORDS - i - 1],
208 &dst_kernel[i]);
209 }
210 }
211
212 return 0;
213 }
214
vc4_hvs_lut_load(struct vc4_hvs * hvs,struct vc4_crtc * vc4_crtc)215 static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
216 struct vc4_crtc *vc4_crtc)
217 {
218 struct drm_device *drm = &hvs->vc4->base;
219 struct drm_crtc *crtc = &vc4_crtc->base;
220 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
221 int idx;
222 u32 i;
223
224 if (!drm_dev_enter(drm, &idx))
225 return;
226
227 if (hvs->vc4->is_vc5)
228 return;
229
230 /* The LUT memory is laid out with each HVS channel in order,
231 * each of which takes 256 writes for R, 256 for G, then 256
232 * for B.
233 */
234 HVS_WRITE(SCALER_GAMADDR,
235 SCALER_GAMADDR_AUTOINC |
236 (vc4_state->assigned_channel * 3 * crtc->gamma_size));
237
238 for (i = 0; i < crtc->gamma_size; i++)
239 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
240 for (i = 0; i < crtc->gamma_size; i++)
241 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
242 for (i = 0; i < crtc->gamma_size; i++)
243 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
244
245 drm_dev_exit(idx);
246 }
247
vc4_hvs_update_gamma_lut(struct vc4_hvs * hvs,struct vc4_crtc * vc4_crtc)248 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs,
249 struct vc4_crtc *vc4_crtc)
250 {
251 struct drm_crtc_state *crtc_state = vc4_crtc->base.state;
252 struct drm_color_lut *lut = crtc_state->gamma_lut->data;
253 u32 length = drm_color_lut_size(crtc_state->gamma_lut);
254 u32 i;
255
256 for (i = 0; i < length; i++) {
257 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
258 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
259 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
260 }
261
262 vc4_hvs_lut_load(hvs, vc4_crtc);
263 }
264
vc4_hvs_get_fifo_frame_count(struct vc4_hvs * hvs,unsigned int fifo)265 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
266 {
267 struct drm_device *drm = &hvs->vc4->base;
268 u8 field = 0;
269 int idx;
270
271 if (!drm_dev_enter(drm, &idx))
272 return 0;
273
274 switch (fifo) {
275 case 0:
276 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
277 SCALER_DISPSTAT1_FRCNT0);
278 break;
279 case 1:
280 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
281 SCALER_DISPSTAT1_FRCNT1);
282 break;
283 case 2:
284 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),
285 SCALER_DISPSTAT2_FRCNT2);
286 break;
287 }
288
289 drm_dev_exit(idx);
290 return field;
291 }
292
vc4_hvs_get_fifo_from_output(struct vc4_hvs * hvs,unsigned int output)293 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
294 {
295 struct vc4_dev *vc4 = hvs->vc4;
296 u32 reg;
297 int ret;
298
299 if (!vc4->is_vc5)
300 return output;
301
302 /*
303 * NOTE: We should probably use drm_dev_enter()/drm_dev_exit()
304 * here, but this function is only used during the DRM device
305 * initialization, so we should be fine.
306 */
307
308 switch (output) {
309 case 0:
310 return 0;
311
312 case 1:
313 return 1;
314
315 case 2:
316 reg = HVS_READ(SCALER_DISPECTRL);
317 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
318 if (ret == 0)
319 return 2;
320
321 return 0;
322
323 case 3:
324 reg = HVS_READ(SCALER_DISPCTRL);
325 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
326 if (ret == 3)
327 return -EPIPE;
328
329 return ret;
330
331 case 4:
332 reg = HVS_READ(SCALER_DISPEOLN);
333 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
334 if (ret == 3)
335 return -EPIPE;
336
337 return ret;
338
339 case 5:
340 reg = HVS_READ(SCALER_DISPDITHER);
341 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
342 if (ret == 3)
343 return -EPIPE;
344
345 return ret;
346
347 default:
348 return -EPIPE;
349 }
350 }
351
vc4_hvs_init_channel(struct vc4_hvs * hvs,struct drm_crtc * crtc,struct drm_display_mode * mode,bool oneshot)352 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
353 struct drm_display_mode *mode, bool oneshot)
354 {
355 struct vc4_dev *vc4 = hvs->vc4;
356 struct drm_device *drm = &vc4->base;
357 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
358 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
359 unsigned int chan = vc4_crtc_state->assigned_channel;
360 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
361 u32 dispbkgndx;
362 u32 dispctrl;
363 int idx;
364
365 if (!drm_dev_enter(drm, &idx))
366 return -ENODEV;
367
368 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
369 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
370 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
371
372 /* Turn on the scaler, which will wait for vstart to start
373 * compositing.
374 * When feeding the transposer, we should operate in oneshot
375 * mode.
376 */
377 dispctrl = SCALER_DISPCTRLX_ENABLE;
378 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
379
380 if (!vc4->is_vc5) {
381 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
382 SCALER_DISPCTRLX_WIDTH) |
383 VC4_SET_FIELD(mode->vdisplay,
384 SCALER_DISPCTRLX_HEIGHT) |
385 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
386 dispbkgndx |= SCALER_DISPBKGND_AUTOHS;
387 } else {
388 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
389 SCALER5_DISPCTRLX_WIDTH) |
390 VC4_SET_FIELD(mode->vdisplay,
391 SCALER5_DISPCTRLX_HEIGHT) |
392 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
393 dispbkgndx &= ~SCALER5_DISPBKGND_BCK2BCK;
394 }
395
396 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
397
398 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
399 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
400
401 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
402 ((!vc4->is_vc5) ? SCALER_DISPBKGND_GAMMA : 0) |
403 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
404
405 /* Reload the LUT, since the SRAMs would have been disabled if
406 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
407 */
408 vc4_hvs_lut_load(hvs, vc4_crtc);
409
410 drm_dev_exit(idx);
411
412 return 0;
413 }
414
vc4_hvs_stop_channel(struct vc4_hvs * hvs,unsigned int chan)415 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
416 {
417 struct drm_device *drm = &hvs->vc4->base;
418 int idx;
419
420 if (!drm_dev_enter(drm, &idx))
421 return;
422
423 if (!(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE))
424 goto out;
425
426 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
427 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
428
429 /* Once we leave, the scaler should be disabled and its fifo empty. */
430 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
431
432 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
433 SCALER_DISPSTATX_MODE) !=
434 SCALER_DISPSTATX_MODE_DISABLED);
435
436 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
437 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
438 SCALER_DISPSTATX_EMPTY);
439
440 out:
441 drm_dev_exit(idx);
442 }
443
vc4_hvs_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)444 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
445 {
446 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
447 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
448 struct drm_device *dev = crtc->dev;
449 struct vc4_dev *vc4 = to_vc4_dev(dev);
450 struct drm_plane *plane;
451 unsigned long flags;
452 const struct drm_plane_state *plane_state;
453 u32 dlist_count = 0;
454 int ret;
455
456 /* The pixelvalve can only feed one encoder (and encoders are
457 * 1:1 with connectors.)
458 */
459 if (hweight32(crtc_state->connector_mask) > 1)
460 return -EINVAL;
461
462 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)
463 dlist_count += vc4_plane_dlist_size(plane_state);
464
465 dlist_count++; /* Account for SCALER_CTL0_END. */
466
467 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
468 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
469 dlist_count);
470 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
471 if (ret)
472 return ret;
473
474 return 0;
475 }
476
vc4_hvs_install_dlist(struct drm_crtc * crtc)477 static void vc4_hvs_install_dlist(struct drm_crtc *crtc)
478 {
479 struct drm_device *dev = crtc->dev;
480 struct vc4_dev *vc4 = to_vc4_dev(dev);
481 struct vc4_hvs *hvs = vc4->hvs;
482 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
483 int idx;
484
485 if (!drm_dev_enter(dev, &idx))
486 return;
487
488 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
489 vc4_state->mm.start);
490
491 drm_dev_exit(idx);
492 }
493
vc4_hvs_update_dlist(struct drm_crtc * crtc)494 static void vc4_hvs_update_dlist(struct drm_crtc *crtc)
495 {
496 struct drm_device *dev = crtc->dev;
497 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
498 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
499 unsigned long flags;
500
501 if (crtc->state->event) {
502 crtc->state->event->pipe = drm_crtc_index(crtc);
503
504 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
505
506 spin_lock_irqsave(&dev->event_lock, flags);
507
508 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) {
509 vc4_crtc->event = crtc->state->event;
510 crtc->state->event = NULL;
511 }
512
513 spin_unlock_irqrestore(&dev->event_lock, flags);
514 }
515
516 spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
517 vc4_crtc->current_dlist = vc4_state->mm.start;
518 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
519 }
520
vc4_hvs_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)521 void vc4_hvs_atomic_begin(struct drm_crtc *crtc,
522 struct drm_atomic_state *state)
523 {
524 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
525 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
526 unsigned long flags;
527
528 spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
529 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel;
530 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
531 }
532
vc4_hvs_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)533 void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
534 struct drm_atomic_state *state)
535 {
536 struct drm_device *dev = crtc->dev;
537 struct vc4_dev *vc4 = to_vc4_dev(dev);
538 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
539 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
540 bool oneshot = vc4_crtc->feeds_txp;
541
542 vc4_hvs_install_dlist(crtc);
543 vc4_hvs_update_dlist(crtc);
544 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot);
545 }
546
vc4_hvs_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)547 void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
548 struct drm_atomic_state *state)
549 {
550 struct drm_device *dev = crtc->dev;
551 struct vc4_dev *vc4 = to_vc4_dev(dev);
552 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
553 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
554 unsigned int chan = vc4_state->assigned_channel;
555
556 vc4_hvs_stop_channel(vc4->hvs, chan);
557 }
558
vc4_hvs_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)559 void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
560 struct drm_atomic_state *state)
561 {
562 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
563 crtc);
564 struct drm_device *dev = crtc->dev;
565 struct vc4_dev *vc4 = to_vc4_dev(dev);
566 struct vc4_hvs *hvs = vc4->hvs;
567 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
568 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
569 unsigned int channel = vc4_state->assigned_channel;
570 struct drm_plane *plane;
571 struct vc4_plane_state *vc4_plane_state;
572 bool debug_dump_regs = false;
573 bool enable_bg_fill = false;
574 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
575 u32 __iomem *dlist_next = dlist_start;
576 unsigned int zpos = 0;
577 bool found = false;
578 int idx;
579
580 if (!drm_dev_enter(dev, &idx)) {
581 vc4_crtc_send_vblank(crtc);
582 return;
583 }
584
585 if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
586 goto exit;
587
588 if (debug_dump_regs) {
589 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
590 vc4_hvs_dump_state(hvs);
591 }
592
593 /* Copy all the active planes' dlist contents to the hardware dlist. */
594 do {
595 found = false;
596
597 drm_atomic_crtc_for_each_plane(plane, crtc) {
598 if (plane->state->normalized_zpos != zpos)
599 continue;
600
601 /* Is this the first active plane? */
602 if (dlist_next == dlist_start) {
603 /* We need to enable background fill when a plane
604 * could be alpha blending from the background, i.e.
605 * where no other plane is underneath. It suffices to
606 * consider the first active plane here since we set
607 * needs_bg_fill such that either the first plane
608 * already needs it or all planes on top blend from
609 * the first or a lower plane.
610 */
611 vc4_plane_state = to_vc4_plane_state(plane->state);
612 enable_bg_fill = vc4_plane_state->needs_bg_fill;
613 }
614
615 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
616
617 found = true;
618 }
619
620 zpos++;
621 } while (found);
622
623 writel(SCALER_CTL0_END, dlist_next);
624 dlist_next++;
625
626 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
627
628 if (enable_bg_fill)
629 /* This sets a black background color fill, as is the case
630 * with other DRM drivers.
631 */
632 HVS_WRITE(SCALER_DISPBKGNDX(channel),
633 HVS_READ(SCALER_DISPBKGNDX(channel)) |
634 SCALER_DISPBKGND_FILL);
635
636 /* Only update DISPLIST if the CRTC was already running and is not
637 * being disabled.
638 * vc4_crtc_enable() takes care of updating the dlist just after
639 * re-enabling VBLANK interrupts and before enabling the engine.
640 * If the CRTC is being disabled, there's no point in updating this
641 * information.
642 */
643 if (crtc->state->active && old_state->active) {
644 vc4_hvs_install_dlist(crtc);
645 vc4_hvs_update_dlist(crtc);
646 }
647
648 if (crtc->state->color_mgmt_changed) {
649 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
650
651 if (crtc->state->gamma_lut) {
652 vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
653 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
654 } else {
655 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
656 * in hardware, which is the same as a linear lut that
657 * DRM expects us to use in absence of a user lut.
658 */
659 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
660 }
661 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx);
662 }
663
664 if (debug_dump_regs) {
665 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
666 vc4_hvs_dump_state(hvs);
667 }
668
669 exit:
670 drm_dev_exit(idx);
671 }
672
vc4_hvs_mask_underrun(struct vc4_hvs * hvs,int channel)673 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
674 {
675 struct drm_device *drm = &hvs->vc4->base;
676 u32 dispctrl;
677 int idx;
678
679 if (!drm_dev_enter(drm, &idx))
680 return;
681
682 dispctrl = HVS_READ(SCALER_DISPCTRL);
683 dispctrl &= ~(hvs->vc4->is_vc5 ? SCALER5_DISPCTRL_DSPEISLUR(channel) :
684 SCALER_DISPCTRL_DSPEISLUR(channel));
685
686 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
687
688 drm_dev_exit(idx);
689 }
690
vc4_hvs_unmask_underrun(struct vc4_hvs * hvs,int channel)691 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
692 {
693 struct drm_device *drm = &hvs->vc4->base;
694 u32 dispctrl;
695 int idx;
696
697 if (!drm_dev_enter(drm, &idx))
698 return;
699
700 dispctrl = HVS_READ(SCALER_DISPCTRL);
701 dispctrl |= (hvs->vc4->is_vc5 ? SCALER5_DISPCTRL_DSPEISLUR(channel) :
702 SCALER_DISPCTRL_DSPEISLUR(channel));
703
704 HVS_WRITE(SCALER_DISPSTAT,
705 SCALER_DISPSTAT_EUFLOW(channel));
706 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
707
708 drm_dev_exit(idx);
709 }
710
vc4_hvs_report_underrun(struct drm_device * dev)711 static void vc4_hvs_report_underrun(struct drm_device *dev)
712 {
713 struct vc4_dev *vc4 = to_vc4_dev(dev);
714
715 atomic_inc(&vc4->underrun);
716 DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
717 }
718
vc4_hvs_irq_handler(int irq,void * data)719 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
720 {
721 struct drm_device *dev = data;
722 struct vc4_dev *vc4 = to_vc4_dev(dev);
723 struct vc4_hvs *hvs = vc4->hvs;
724 irqreturn_t irqret = IRQ_NONE;
725 int channel;
726 u32 control;
727 u32 status;
728 u32 dspeislur;
729
730 /*
731 * NOTE: We don't need to protect the register access using
732 * drm_dev_enter() there because the interrupt handler lifetime
733 * is tied to the device itself, and not to the DRM device.
734 *
735 * So when the device will be gone, one of the first thing we
736 * will be doing will be to unregister the interrupt handler,
737 * and then unregister the DRM device. drm_dev_enter() would
738 * thus always succeed if we are here.
739 */
740
741 status = HVS_READ(SCALER_DISPSTAT);
742 control = HVS_READ(SCALER_DISPCTRL);
743
744 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
745 dspeislur = vc4->is_vc5 ? SCALER5_DISPCTRL_DSPEISLUR(channel) :
746 SCALER_DISPCTRL_DSPEISLUR(channel);
747 /* Interrupt masking is not always honored, so check it here. */
748 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
749 control & dspeislur) {
750 vc4_hvs_mask_underrun(hvs, channel);
751 vc4_hvs_report_underrun(dev);
752
753 irqret = IRQ_HANDLED;
754 }
755 }
756
757 /* Clear every per-channel interrupt flag. */
758 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
759 SCALER_DISPSTAT_IRQMASK(1) |
760 SCALER_DISPSTAT_IRQMASK(2));
761
762 return irqret;
763 }
764
vc4_hvs_debugfs_init(struct drm_minor * minor)765 int vc4_hvs_debugfs_init(struct drm_minor *minor)
766 {
767 struct drm_device *drm = minor->dev;
768 struct vc4_dev *vc4 = to_vc4_dev(drm);
769 struct vc4_hvs *hvs = vc4->hvs;
770
771 if (!vc4->hvs)
772 return -ENODEV;
773
774 if (!vc4->is_vc5)
775 debugfs_create_bool("hvs_load_tracker", S_IRUGO | S_IWUSR,
776 minor->debugfs_root,
777 &vc4->load_tracker_enabled);
778
779 drm_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist, NULL);
780
781 drm_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun, NULL);
782
783 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
784
785 return 0;
786 }
787
__vc4_hvs_alloc(struct vc4_dev * vc4,struct platform_device * pdev)788 struct vc4_hvs *__vc4_hvs_alloc(struct vc4_dev *vc4, struct platform_device *pdev)
789 {
790 struct drm_device *drm = &vc4->base;
791 struct vc4_hvs *hvs;
792
793 hvs = drmm_kzalloc(drm, sizeof(*hvs), GFP_KERNEL);
794 if (!hvs)
795 return ERR_PTR(-ENOMEM);
796
797 hvs->vc4 = vc4;
798 hvs->pdev = pdev;
799
800 spin_lock_init(&hvs->mm_lock);
801
802 /* Set up the HVS display list memory manager. We never
803 * overwrite the setup from the bootloader (just 128b out of
804 * our 16K), since we don't want to scramble the screen when
805 * transitioning from the firmware's boot setup to runtime.
806 */
807 hvs->dlist_mem_size = (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END;
808 drm_mm_init(&hvs->dlist_mm,
809 HVS_BOOTLOADER_DLIST_END,
810 hvs->dlist_mem_size);
811
812 /* Set up the HVS LBM memory manager. We could have some more
813 * complicated data structure that allowed reuse of LBM areas
814 * between planes when they don't overlap on the screen, but
815 * for now we just allocate globally.
816 */
817 if (!vc4->is_vc5)
818 /* 48k words of 2x12-bit pixels */
819 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
820 else
821 /* 60k words of 4x12-bit pixels */
822 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024);
823
824 vc4->hvs = hvs;
825
826 return hvs;
827 }
828
vc4_hvs_bind(struct device * dev,struct device * master,void * data)829 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
830 {
831 struct platform_device *pdev = to_platform_device(dev);
832 struct drm_device *drm = dev_get_drvdata(master);
833 struct vc4_dev *vc4 = to_vc4_dev(drm);
834 struct vc4_hvs *hvs = NULL;
835 int ret;
836 u32 dispctrl;
837 u32 reg, top;
838
839 hvs = __vc4_hvs_alloc(vc4, NULL);
840 if (IS_ERR(hvs))
841 return PTR_ERR(hvs);
842
843 hvs->regs = vc4_ioremap_regs(pdev, 0);
844 if (IS_ERR(hvs->regs))
845 return PTR_ERR(hvs->regs);
846
847 hvs->regset.base = hvs->regs;
848 hvs->regset.regs = hvs_regs;
849 hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
850
851 if (vc4->is_vc5) {
852 struct rpi_firmware *firmware;
853 struct device_node *node;
854 unsigned int max_rate;
855
856 node = rpi_firmware_find_node();
857 if (!node)
858 return -EINVAL;
859
860 firmware = rpi_firmware_get(node);
861 of_node_put(node);
862 if (!firmware)
863 return -EPROBE_DEFER;
864
865 hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
866 if (IS_ERR(hvs->core_clk)) {
867 dev_err(&pdev->dev, "Couldn't get core clock\n");
868 return PTR_ERR(hvs->core_clk);
869 }
870
871 max_rate = rpi_firmware_clk_get_max_rate(firmware,
872 RPI_FIRMWARE_CORE_CLK_ID);
873 rpi_firmware_put(firmware);
874 if (max_rate >= 550000000)
875 hvs->vc5_hdmi_enable_hdmi_20 = true;
876
877 if (max_rate >= 600000000)
878 hvs->vc5_hdmi_enable_4096by2160 = true;
879
880 hvs->max_core_rate = max_rate;
881
882 ret = clk_prepare_enable(hvs->core_clk);
883 if (ret) {
884 dev_err(&pdev->dev, "Couldn't enable the core clock\n");
885 return ret;
886 }
887 }
888
889 if (!vc4->is_vc5)
890 hvs->dlist = hvs->regs + SCALER_DLIST_START;
891 else
892 hvs->dlist = hvs->regs + SCALER5_DLIST_START;
893
894 /* Upload filter kernels. We only have the one for now, so we
895 * keep it around for the lifetime of the driver.
896 */
897 ret = vc4_hvs_upload_linear_kernel(hvs,
898 &hvs->mitchell_netravali_filter,
899 mitchell_netravali_1_3_1_3_kernel);
900 if (ret)
901 return ret;
902
903 reg = HVS_READ(SCALER_DISPECTRL);
904 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK;
905 HVS_WRITE(SCALER_DISPECTRL,
906 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));
907
908 reg = HVS_READ(SCALER_DISPCTRL);
909 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
910 HVS_WRITE(SCALER_DISPCTRL,
911 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX));
912
913 reg = HVS_READ(SCALER_DISPEOLN);
914 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK;
915 HVS_WRITE(SCALER_DISPEOLN,
916 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX));
917
918 reg = HVS_READ(SCALER_DISPDITHER);
919 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK;
920 HVS_WRITE(SCALER_DISPDITHER,
921 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX));
922
923 dispctrl = HVS_READ(SCALER_DISPCTRL);
924
925 dispctrl |= SCALER_DISPCTRL_ENABLE;
926 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
927 SCALER_DISPCTRL_DISPEIRQ(1) |
928 SCALER_DISPCTRL_DISPEIRQ(2);
929
930 if (!vc4->is_vc5)
931 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
932 SCALER_DISPCTRL_SLVWREIRQ |
933 SCALER_DISPCTRL_SLVRDEIRQ |
934 SCALER_DISPCTRL_DSPEIEOF(0) |
935 SCALER_DISPCTRL_DSPEIEOF(1) |
936 SCALER_DISPCTRL_DSPEIEOF(2) |
937 SCALER_DISPCTRL_DSPEIEOLN(0) |
938 SCALER_DISPCTRL_DSPEIEOLN(1) |
939 SCALER_DISPCTRL_DSPEIEOLN(2) |
940 SCALER_DISPCTRL_DSPEISLUR(0) |
941 SCALER_DISPCTRL_DSPEISLUR(1) |
942 SCALER_DISPCTRL_DSPEISLUR(2) |
943 SCALER_DISPCTRL_SCLEIRQ);
944 else
945 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
946 SCALER5_DISPCTRL_SLVEIRQ |
947 SCALER5_DISPCTRL_DSPEIEOF(0) |
948 SCALER5_DISPCTRL_DSPEIEOF(1) |
949 SCALER5_DISPCTRL_DSPEIEOF(2) |
950 SCALER5_DISPCTRL_DSPEIEOLN(0) |
951 SCALER5_DISPCTRL_DSPEIEOLN(1) |
952 SCALER5_DISPCTRL_DSPEIEOLN(2) |
953 SCALER5_DISPCTRL_DSPEISLUR(0) |
954 SCALER5_DISPCTRL_DSPEISLUR(1) |
955 SCALER5_DISPCTRL_DSPEISLUR(2) |
956 SCALER_DISPCTRL_SCLEIRQ);
957
958
959 /* Set AXI panic mode.
960 * VC4 panics when < 2 lines in FIFO.
961 * VC5 panics when less than 1 line in the FIFO.
962 */
963 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK |
964 SCALER_DISPCTRL_PANIC1_MASK |
965 SCALER_DISPCTRL_PANIC2_MASK);
966 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
967 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);
968 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
969
970 /* Set AXI panic mode.
971 * VC4 panics when < 2 lines in FIFO.
972 * VC5 panics when less than 1 line in the FIFO.
973 */
974 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK |
975 SCALER_DISPCTRL_PANIC1_MASK |
976 SCALER_DISPCTRL_PANIC2_MASK);
977 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
978 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);
979 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
980
981 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
982
983 /* Recompute Composite Output Buffer (COB) allocations for the displays
984 */
985 if (!vc4->is_vc5) {
986 /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
987 * The bottom 2048 pixels are full 32bpp RGBA (intended for the
988 * TXP composing RGBA to memory), whilst the remainder are only
989 * 24bpp RGB.
990 *
991 * Assign 3 lines to channels 1 & 2, and just over 4 lines to
992 * channel 0.
993 */
994 #define VC4_COB_SIZE 20736
995 #define VC4_COB_LINE_WIDTH 2048
996 #define VC4_COB_NUM_LINES 3
997 reg = 0;
998 top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
999 reg |= (top - 1) << 16;
1000 HVS_WRITE(SCALER_DISPBASE2, reg);
1001 reg = top;
1002 top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
1003 reg |= (top - 1) << 16;
1004 HVS_WRITE(SCALER_DISPBASE1, reg);
1005 reg = top;
1006 top = VC4_COB_SIZE;
1007 reg |= (top - 1) << 16;
1008 HVS_WRITE(SCALER_DISPBASE0, reg);
1009 } else {
1010 /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
1011 * The bottom 4096 pixels are full RGBA (intended for the TXP
1012 * composing RGBA to memory), whilst the remainder are only
1013 * RGB. Addressing is always pixel wide.
1014 *
1015 * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
1016 * lines. to channel 0.
1017 */
1018 #define VC5_COB_SIZE 44416
1019 #define VC5_COB_LINE_WIDTH 4096
1020 #define VC5_COB_NUM_LINES 3
1021 reg = 0;
1022 top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
1023 reg |= top << 16;
1024 HVS_WRITE(SCALER_DISPBASE2, reg);
1025 top += 16;
1026 reg = top;
1027 top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
1028 reg |= top << 16;
1029 HVS_WRITE(SCALER_DISPBASE1, reg);
1030 top += 16;
1031 reg = top;
1032 top = VC5_COB_SIZE;
1033 reg |= top << 16;
1034 HVS_WRITE(SCALER_DISPBASE0, reg);
1035 }
1036
1037 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1038 vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
1039 if (ret)
1040 return ret;
1041
1042 return 0;
1043 }
1044
vc4_hvs_unbind(struct device * dev,struct device * master,void * data)1045 static void vc4_hvs_unbind(struct device *dev, struct device *master,
1046 void *data)
1047 {
1048 struct drm_device *drm = dev_get_drvdata(master);
1049 struct vc4_dev *vc4 = to_vc4_dev(drm);
1050 struct vc4_hvs *hvs = vc4->hvs;
1051 struct drm_mm_node *node, *next;
1052
1053 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
1054 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
1055
1056 drm_mm_for_each_node_safe(node, next, &vc4->hvs->dlist_mm)
1057 drm_mm_remove_node(node);
1058
1059 drm_mm_takedown(&vc4->hvs->dlist_mm);
1060
1061 drm_mm_for_each_node_safe(node, next, &vc4->hvs->lbm_mm)
1062 drm_mm_remove_node(node);
1063 drm_mm_takedown(&vc4->hvs->lbm_mm);
1064
1065 clk_disable_unprepare(hvs->core_clk);
1066
1067 vc4->hvs = NULL;
1068 }
1069
1070 static const struct component_ops vc4_hvs_ops = {
1071 .bind = vc4_hvs_bind,
1072 .unbind = vc4_hvs_unbind,
1073 };
1074
vc4_hvs_dev_probe(struct platform_device * pdev)1075 static int vc4_hvs_dev_probe(struct platform_device *pdev)
1076 {
1077 return component_add(&pdev->dev, &vc4_hvs_ops);
1078 }
1079
vc4_hvs_dev_remove(struct platform_device * pdev)1080 static void vc4_hvs_dev_remove(struct platform_device *pdev)
1081 {
1082 component_del(&pdev->dev, &vc4_hvs_ops);
1083 }
1084
1085 static const struct of_device_id vc4_hvs_dt_match[] = {
1086 { .compatible = "brcm,bcm2711-hvs" },
1087 { .compatible = "brcm,bcm2835-hvs" },
1088 {}
1089 };
1090
1091 struct platform_driver vc4_hvs_driver = {
1092 .probe = vc4_hvs_dev_probe,
1093 .remove_new = vc4_hvs_dev_remove,
1094 .driver = {
1095 .name = "vc4_hvs",
1096 .of_match_table = vc4_hvs_dt_match,
1097 },
1098 };
1099