1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
5 */
6
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <syscon.h>
11 #include <linux/io.h>
12 #include <mach/at91_pmc.h>
13 #include <mach/sama5_sfr.h>
14 #include "pmc.h"
15
16 /*
17 * The purpose of this clock is to generate a 480 MHz signal. A different
18 * rate can't be configured.
19 */
20 #define UTMI_RATE 480000000
21
utmi_clk_enable(struct clk * clk)22 static int utmi_clk_enable(struct clk *clk)
23 {
24 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
25 struct at91_pmc *pmc = plat->reg_base;
26 struct clk clk_dev;
27 ulong clk_rate;
28 u32 utmi_ref_clk_freq;
29 u32 tmp;
30 int err;
31 int timeout = 2000000;
32
33 if (readl(&pmc->sr) & AT91_PMC_LOCKU)
34 return 0;
35
36 /*
37 * If mainck rate is different from 12 MHz, we have to configure the
38 * FREQ field of the SFR_UTMICKTRIM register to generate properly
39 * the utmi clock.
40 */
41 err = clk_get_by_index(clk->dev, 0, &clk_dev);
42 if (err)
43 return -EINVAL;
44
45 clk_rate = clk_get_rate(&clk_dev);
46 switch (clk_rate) {
47 case 12000000:
48 utmi_ref_clk_freq = 0;
49 break;
50 case 16000000:
51 utmi_ref_clk_freq = 1;
52 break;
53 case 24000000:
54 utmi_ref_clk_freq = 2;
55 break;
56 /*
57 * Not supported on SAMA5D2 but it's not an issue since MAINCK
58 * maximum value is 24 MHz.
59 */
60 case 48000000:
61 utmi_ref_clk_freq = 3;
62 break;
63 default:
64 printf("UTMICK: unsupported mainck rate\n");
65 return -EINVAL;
66 }
67
68 if (plat->regmap_sfr) {
69 err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
70 if (err)
71 return -EINVAL;
72
73 tmp &= ~AT91_UTMICKTRIM_FREQ;
74 tmp |= utmi_ref_clk_freq;
75 err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
76 if (err)
77 return -EINVAL;
78 } else if (utmi_ref_clk_freq) {
79 printf("UTMICK: sfr node required\n");
80 return -EINVAL;
81 }
82
83 tmp = readl(&pmc->uckr);
84 tmp |= AT91_PMC_UPLLEN |
85 AT91_PMC_UPLLCOUNT |
86 AT91_PMC_BIASEN;
87 writel(tmp, &pmc->uckr);
88
89 while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
90 ;
91 if (!timeout) {
92 printf("UTMICK: timeout waiting for UPLL lock\n");
93 return -ETIMEDOUT;
94 }
95
96 return 0;
97 }
98
utmi_clk_get_rate(struct clk * clk)99 static ulong utmi_clk_get_rate(struct clk *clk)
100 {
101 /* UTMI clk rate is fixed. */
102 return UTMI_RATE;
103 }
104
105 static struct clk_ops utmi_clk_ops = {
106 .enable = utmi_clk_enable,
107 .get_rate = utmi_clk_get_rate,
108 };
109
utmi_clk_ofdata_to_platdata(struct udevice * dev)110 static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
111 {
112 struct pmc_platdata *plat = dev_get_platdata(dev);
113 struct udevice *syscon;
114
115 uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
116 "regmap-sfr", &syscon);
117
118 if (syscon)
119 plat->regmap_sfr = syscon_get_regmap(syscon);
120
121 return 0;
122 }
123
utmi_clk_probe(struct udevice * dev)124 static int utmi_clk_probe(struct udevice *dev)
125 {
126 return at91_pmc_core_probe(dev);
127 }
128
129 static const struct udevice_id utmi_clk_match[] = {
130 { .compatible = "atmel,at91sam9x5-clk-utmi" },
131 {}
132 };
133
134 U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
135 .name = "at91sam9x5-utmi-clk",
136 .id = UCLASS_CLK,
137 .of_match = utmi_clk_match,
138 .probe = utmi_clk_probe,
139 .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
140 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
141 .ops = &utmi_clk_ops,
142 };
143