1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27
28 #include <linux/file.h>
29 #include <linux/pagemap.h>
30 #include <linux/sync_file.h>
31 #include <linux/dma-buf.h>
32
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_syncobj.h>
35 #include <drm/ttm/ttm_tt.h>
36
37 #include "amdgpu_cs.h"
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 #include "amdgpu_gmc.h"
41 #include "amdgpu_gem.h"
42 #include "amdgpu_ras.h"
43
amdgpu_cs_parser_init(struct amdgpu_cs_parser * p,struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_cs * cs)44 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
45 struct amdgpu_device *adev,
46 struct drm_file *filp,
47 union drm_amdgpu_cs *cs)
48 {
49 struct amdgpu_fpriv *fpriv = filp->driver_priv;
50
51 if (cs->in.num_chunks == 0)
52 return -EINVAL;
53
54 memset(p, 0, sizeof(*p));
55 p->adev = adev;
56 p->filp = filp;
57
58 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
59 if (!p->ctx)
60 return -EINVAL;
61
62 if (atomic_read(&p->ctx->guilty)) {
63 amdgpu_ctx_put(p->ctx);
64 return -ECANCELED;
65 }
66
67 amdgpu_sync_create(&p->sync);
68 drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
69 DRM_EXEC_IGNORE_DUPLICATES);
70 return 0;
71 }
72
amdgpu_cs_job_idx(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_ib * chunk_ib)73 static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
74 struct drm_amdgpu_cs_chunk_ib *chunk_ib)
75 {
76 struct drm_sched_entity *entity;
77 unsigned int i;
78 int r;
79
80 r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
81 chunk_ib->ip_instance,
82 chunk_ib->ring, &entity);
83 if (r)
84 return r;
85
86 /*
87 * Abort if there is no run queue associated with this entity.
88 * Possibly because of disabled HW IP.
89 */
90 if (entity->rq == NULL)
91 return -EINVAL;
92
93 /* Check if we can add this IB to some existing job */
94 for (i = 0; i < p->gang_size; ++i)
95 if (p->entities[i] == entity)
96 return i;
97
98 /* If not increase the gang size if possible */
99 if (i == AMDGPU_CS_GANG_SIZE)
100 return -EINVAL;
101
102 p->entities[i] = entity;
103 p->gang_size = i + 1;
104 return i;
105 }
106
amdgpu_cs_p1_ib(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_ib * chunk_ib,unsigned int * num_ibs)107 static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
108 struct drm_amdgpu_cs_chunk_ib *chunk_ib,
109 unsigned int *num_ibs)
110 {
111 int r;
112
113 r = amdgpu_cs_job_idx(p, chunk_ib);
114 if (r < 0)
115 return r;
116
117 if (num_ibs[r] >= amdgpu_ring_max_ibs(chunk_ib->ip_type))
118 return -EINVAL;
119
120 ++(num_ibs[r]);
121 p->gang_leader_idx = r;
122 return 0;
123 }
124
amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_fence * data,uint32_t * offset)125 static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
126 struct drm_amdgpu_cs_chunk_fence *data,
127 uint32_t *offset)
128 {
129 struct drm_gem_object *gobj;
130 unsigned long size;
131
132 gobj = drm_gem_object_lookup(p->filp, data->handle);
133 if (gobj == NULL)
134 return -EINVAL;
135
136 p->uf_bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
137 drm_gem_object_put(gobj);
138
139 size = amdgpu_bo_size(p->uf_bo);
140 if (size != PAGE_SIZE || data->offset > (size - 8))
141 return -EINVAL;
142
143 if (amdgpu_ttm_tt_get_usermm(p->uf_bo->tbo.ttm))
144 return -EINVAL;
145
146 *offset = data->offset;
147 return 0;
148 }
149
amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser * p,struct drm_amdgpu_bo_list_in * data)150 static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
151 struct drm_amdgpu_bo_list_in *data)
152 {
153 struct drm_amdgpu_bo_list_entry *info;
154 int r;
155
156 r = amdgpu_bo_create_list_entry_array(data, &info);
157 if (r)
158 return r;
159
160 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
161 &p->bo_list);
162 if (r)
163 goto error_free;
164
165 kvfree(info);
166 return 0;
167
168 error_free:
169 kvfree(info);
170
171 return r;
172 }
173
174 /* Copy the data from userspace and go over it the first time */
amdgpu_cs_pass1(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)175 static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
176 union drm_amdgpu_cs *cs)
177 {
178 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
179 unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
180 struct amdgpu_vm *vm = &fpriv->vm;
181 uint64_t *chunk_array_user;
182 uint64_t *chunk_array;
183 uint32_t uf_offset = 0;
184 size_t size;
185 int ret;
186 int i;
187
188 chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
189 GFP_KERNEL);
190 if (!chunk_array)
191 return -ENOMEM;
192
193 /* get chunks */
194 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
195 if (copy_from_user(chunk_array, chunk_array_user,
196 sizeof(uint64_t)*cs->in.num_chunks)) {
197 ret = -EFAULT;
198 goto free_chunk;
199 }
200
201 p->nchunks = cs->in.num_chunks;
202 p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
203 GFP_KERNEL);
204 if (!p->chunks) {
205 ret = -ENOMEM;
206 goto free_chunk;
207 }
208
209 for (i = 0; i < p->nchunks; i++) {
210 struct drm_amdgpu_cs_chunk __user *chunk_ptr = NULL;
211 struct drm_amdgpu_cs_chunk user_chunk;
212 uint32_t __user *cdata;
213
214 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
215 if (copy_from_user(&user_chunk, chunk_ptr,
216 sizeof(struct drm_amdgpu_cs_chunk))) {
217 ret = -EFAULT;
218 i--;
219 goto free_partial_kdata;
220 }
221 p->chunks[i].chunk_id = user_chunk.chunk_id;
222 p->chunks[i].length_dw = user_chunk.length_dw;
223
224 size = p->chunks[i].length_dw;
225 cdata = u64_to_user_ptr(user_chunk.chunk_data);
226
227 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),
228 GFP_KERNEL);
229 if (p->chunks[i].kdata == NULL) {
230 ret = -ENOMEM;
231 i--;
232 goto free_partial_kdata;
233 }
234 size *= sizeof(uint32_t);
235 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
236 ret = -EFAULT;
237 goto free_partial_kdata;
238 }
239
240 /* Assume the worst on the following checks */
241 ret = -EINVAL;
242 switch (p->chunks[i].chunk_id) {
243 case AMDGPU_CHUNK_ID_IB:
244 if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
245 goto free_partial_kdata;
246
247 ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
248 if (ret)
249 goto free_partial_kdata;
250 break;
251
252 case AMDGPU_CHUNK_ID_FENCE:
253 if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
254 goto free_partial_kdata;
255
256 ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
257 &uf_offset);
258 if (ret)
259 goto free_partial_kdata;
260 break;
261
262 case AMDGPU_CHUNK_ID_BO_HANDLES:
263 if (size < sizeof(struct drm_amdgpu_bo_list_in))
264 goto free_partial_kdata;
265
266 /* Only a single BO list is allowed to simplify handling. */
267 if (p->bo_list)
268 goto free_partial_kdata;
269
270 ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
271 if (ret)
272 goto free_partial_kdata;
273 break;
274
275 case AMDGPU_CHUNK_ID_DEPENDENCIES:
276 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
277 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
278 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
279 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
280 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
281 case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
282 break;
283
284 default:
285 goto free_partial_kdata;
286 }
287 }
288
289 if (!p->gang_size) {
290 ret = -EINVAL;
291 goto free_all_kdata;
292 }
293
294 for (i = 0; i < p->gang_size; ++i) {
295 ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
296 num_ibs[i], &p->jobs[i]);
297 if (ret)
298 goto free_all_kdata;
299 }
300 p->gang_leader = p->jobs[p->gang_leader_idx];
301
302 if (p->ctx->generation != p->gang_leader->generation) {
303 ret = -ECANCELED;
304 goto free_all_kdata;
305 }
306
307 if (p->uf_bo)
308 p->gang_leader->uf_addr = uf_offset;
309 kvfree(chunk_array);
310
311 /* Use this opportunity to fill in task info for the vm */
312 amdgpu_vm_set_task_info(vm);
313
314 return 0;
315
316 free_all_kdata:
317 i = p->nchunks - 1;
318 free_partial_kdata:
319 for (; i >= 0; i--)
320 kvfree(p->chunks[i].kdata);
321 kvfree(p->chunks);
322 p->chunks = NULL;
323 p->nchunks = 0;
324 free_chunk:
325 kvfree(chunk_array);
326
327 return ret;
328 }
329
amdgpu_cs_p2_ib(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk,unsigned int * ce_preempt,unsigned int * de_preempt)330 static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
331 struct amdgpu_cs_chunk *chunk,
332 unsigned int *ce_preempt,
333 unsigned int *de_preempt)
334 {
335 struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
336 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
337 struct amdgpu_vm *vm = &fpriv->vm;
338 struct amdgpu_ring *ring;
339 struct amdgpu_job *job;
340 struct amdgpu_ib *ib;
341 int r;
342
343 r = amdgpu_cs_job_idx(p, chunk_ib);
344 if (r < 0)
345 return r;
346
347 job = p->jobs[r];
348 ring = amdgpu_job_ring(job);
349 ib = &job->ibs[job->num_ibs++];
350
351 /* MM engine doesn't support user fences */
352 if (p->uf_bo && ring->funcs->no_user_fence)
353 return -EINVAL;
354
355 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
356 chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
357 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
358 (*ce_preempt)++;
359 else
360 (*de_preempt)++;
361
362 /* Each GFX command submit allows only 1 IB max
363 * preemptible for CE & DE */
364 if (*ce_preempt > 1 || *de_preempt > 1)
365 return -EINVAL;
366 }
367
368 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
369 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
370
371 r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
372 chunk_ib->ib_bytes : 0,
373 AMDGPU_IB_POOL_DELAYED, ib);
374 if (r) {
375 DRM_ERROR("Failed to get ib !\n");
376 return r;
377 }
378
379 ib->gpu_addr = chunk_ib->va_start;
380 ib->length_dw = chunk_ib->ib_bytes / 4;
381 ib->flags = chunk_ib->flags;
382 return 0;
383 }
384
amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)385 static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
386 struct amdgpu_cs_chunk *chunk)
387 {
388 struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
389 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
390 unsigned int num_deps;
391 int i, r;
392
393 num_deps = chunk->length_dw * 4 /
394 sizeof(struct drm_amdgpu_cs_chunk_dep);
395
396 for (i = 0; i < num_deps; ++i) {
397 struct amdgpu_ctx *ctx;
398 struct drm_sched_entity *entity;
399 struct dma_fence *fence;
400
401 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
402 if (ctx == NULL)
403 return -EINVAL;
404
405 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
406 deps[i].ip_instance,
407 deps[i].ring, &entity);
408 if (r) {
409 amdgpu_ctx_put(ctx);
410 return r;
411 }
412
413 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
414 amdgpu_ctx_put(ctx);
415
416 if (IS_ERR(fence))
417 return PTR_ERR(fence);
418 else if (!fence)
419 continue;
420
421 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
422 struct drm_sched_fence *s_fence;
423 struct dma_fence *old = fence;
424
425 s_fence = to_drm_sched_fence(fence);
426 fence = dma_fence_get(&s_fence->scheduled);
427 dma_fence_put(old);
428 }
429
430 r = amdgpu_sync_fence(&p->sync, fence);
431 dma_fence_put(fence);
432 if (r)
433 return r;
434 }
435 return 0;
436 }
437
amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser * p,uint32_t handle,u64 point,u64 flags)438 static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
439 uint32_t handle, u64 point,
440 u64 flags)
441 {
442 struct dma_fence *fence;
443 int r;
444
445 r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
446 if (r) {
447 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
448 handle, point, r);
449 return r;
450 }
451
452 r = amdgpu_sync_fence(&p->sync, fence);
453 dma_fence_put(fence);
454 return r;
455 }
456
amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)457 static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
458 struct amdgpu_cs_chunk *chunk)
459 {
460 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
461 unsigned int num_deps;
462 int i, r;
463
464 num_deps = chunk->length_dw * 4 /
465 sizeof(struct drm_amdgpu_cs_chunk_sem);
466 for (i = 0; i < num_deps; ++i) {
467 r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
468 if (r)
469 return r;
470 }
471
472 return 0;
473 }
474
amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)475 static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
476 struct amdgpu_cs_chunk *chunk)
477 {
478 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
479 unsigned int num_deps;
480 int i, r;
481
482 num_deps = chunk->length_dw * 4 /
483 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
484 for (i = 0; i < num_deps; ++i) {
485 r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
486 syncobj_deps[i].point,
487 syncobj_deps[i].flags);
488 if (r)
489 return r;
490 }
491
492 return 0;
493 }
494
amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)495 static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
496 struct amdgpu_cs_chunk *chunk)
497 {
498 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
499 unsigned int num_deps;
500 int i;
501
502 num_deps = chunk->length_dw * 4 /
503 sizeof(struct drm_amdgpu_cs_chunk_sem);
504
505 if (p->post_deps)
506 return -EINVAL;
507
508 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
509 GFP_KERNEL);
510 p->num_post_deps = 0;
511
512 if (!p->post_deps)
513 return -ENOMEM;
514
515
516 for (i = 0; i < num_deps; ++i) {
517 p->post_deps[i].syncobj =
518 drm_syncobj_find(p->filp, deps[i].handle);
519 if (!p->post_deps[i].syncobj)
520 return -EINVAL;
521 p->post_deps[i].chain = NULL;
522 p->post_deps[i].point = 0;
523 p->num_post_deps++;
524 }
525
526 return 0;
527 }
528
amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)529 static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
530 struct amdgpu_cs_chunk *chunk)
531 {
532 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
533 unsigned int num_deps;
534 int i;
535
536 num_deps = chunk->length_dw * 4 /
537 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
538
539 if (p->post_deps)
540 return -EINVAL;
541
542 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
543 GFP_KERNEL);
544 p->num_post_deps = 0;
545
546 if (!p->post_deps)
547 return -ENOMEM;
548
549 for (i = 0; i < num_deps; ++i) {
550 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
551
552 dep->chain = NULL;
553 if (syncobj_deps[i].point) {
554 dep->chain = dma_fence_chain_alloc();
555 if (!dep->chain)
556 return -ENOMEM;
557 }
558
559 dep->syncobj = drm_syncobj_find(p->filp,
560 syncobj_deps[i].handle);
561 if (!dep->syncobj) {
562 dma_fence_chain_free(dep->chain);
563 return -EINVAL;
564 }
565 dep->point = syncobj_deps[i].point;
566 p->num_post_deps++;
567 }
568
569 return 0;
570 }
571
amdgpu_cs_p2_shadow(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)572 static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p,
573 struct amdgpu_cs_chunk *chunk)
574 {
575 struct drm_amdgpu_cs_chunk_cp_gfx_shadow *shadow = chunk->kdata;
576 int i;
577
578 if (shadow->flags & ~AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW)
579 return -EINVAL;
580
581 for (i = 0; i < p->gang_size; ++i) {
582 p->jobs[i]->shadow_va = shadow->shadow_va;
583 p->jobs[i]->csa_va = shadow->csa_va;
584 p->jobs[i]->gds_va = shadow->gds_va;
585 p->jobs[i]->init_shadow =
586 shadow->flags & AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW;
587 }
588
589 return 0;
590 }
591
amdgpu_cs_pass2(struct amdgpu_cs_parser * p)592 static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
593 {
594 unsigned int ce_preempt = 0, de_preempt = 0;
595 int i, r;
596
597 for (i = 0; i < p->nchunks; ++i) {
598 struct amdgpu_cs_chunk *chunk;
599
600 chunk = &p->chunks[i];
601
602 switch (chunk->chunk_id) {
603 case AMDGPU_CHUNK_ID_IB:
604 r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
605 if (r)
606 return r;
607 break;
608 case AMDGPU_CHUNK_ID_DEPENDENCIES:
609 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
610 r = amdgpu_cs_p2_dependencies(p, chunk);
611 if (r)
612 return r;
613 break;
614 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
615 r = amdgpu_cs_p2_syncobj_in(p, chunk);
616 if (r)
617 return r;
618 break;
619 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
620 r = amdgpu_cs_p2_syncobj_out(p, chunk);
621 if (r)
622 return r;
623 break;
624 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
625 r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
626 if (r)
627 return r;
628 break;
629 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
630 r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
631 if (r)
632 return r;
633 break;
634 case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
635 r = amdgpu_cs_p2_shadow(p, chunk);
636 if (r)
637 return r;
638 break;
639 }
640 }
641
642 return 0;
643 }
644
645 /* Convert microseconds to bytes. */
us_to_bytes(struct amdgpu_device * adev,s64 us)646 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
647 {
648 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
649 return 0;
650
651 /* Since accum_us is incremented by a million per second, just
652 * multiply it by the number of MB/s to get the number of bytes.
653 */
654 return us << adev->mm_stats.log2_max_MBps;
655 }
656
bytes_to_us(struct amdgpu_device * adev,u64 bytes)657 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
658 {
659 if (!adev->mm_stats.log2_max_MBps)
660 return 0;
661
662 return bytes >> adev->mm_stats.log2_max_MBps;
663 }
664
665 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
666 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
667 * which means it can go over the threshold once. If that happens, the driver
668 * will be in debt and no other buffer migrations can be done until that debt
669 * is repaid.
670 *
671 * This approach allows moving a buffer of any size (it's important to allow
672 * that).
673 *
674 * The currency is simply time in microseconds and it increases as the clock
675 * ticks. The accumulated microseconds (us) are converted to bytes and
676 * returned.
677 */
amdgpu_cs_get_threshold_for_moves(struct amdgpu_device * adev,u64 * max_bytes,u64 * max_vis_bytes)678 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
679 u64 *max_bytes,
680 u64 *max_vis_bytes)
681 {
682 s64 time_us, increment_us;
683 u64 free_vram, total_vram, used_vram;
684 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
685 * throttling.
686 *
687 * It means that in order to get full max MBps, at least 5 IBs per
688 * second must be submitted and not more than 200ms apart from each
689 * other.
690 */
691 const s64 us_upper_bound = 200000;
692
693 if (!adev->mm_stats.log2_max_MBps) {
694 *max_bytes = 0;
695 *max_vis_bytes = 0;
696 return;
697 }
698
699 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
700 used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
701 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
702
703 spin_lock(&adev->mm_stats.lock);
704
705 /* Increase the amount of accumulated us. */
706 time_us = ktime_to_us(ktime_get());
707 increment_us = time_us - adev->mm_stats.last_update_us;
708 adev->mm_stats.last_update_us = time_us;
709 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
710 us_upper_bound);
711
712 /* This prevents the short period of low performance when the VRAM
713 * usage is low and the driver is in debt or doesn't have enough
714 * accumulated us to fill VRAM quickly.
715 *
716 * The situation can occur in these cases:
717 * - a lot of VRAM is freed by userspace
718 * - the presence of a big buffer causes a lot of evictions
719 * (solution: split buffers into smaller ones)
720 *
721 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
722 * accum_us to a positive number.
723 */
724 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
725 s64 min_us;
726
727 /* Be more aggressive on dGPUs. Try to fill a portion of free
728 * VRAM now.
729 */
730 if (!(adev->flags & AMD_IS_APU))
731 min_us = bytes_to_us(adev, free_vram / 4);
732 else
733 min_us = 0; /* Reset accum_us on APUs. */
734
735 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
736 }
737
738 /* This is set to 0 if the driver is in debt to disallow (optional)
739 * buffer moves.
740 */
741 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
742
743 /* Do the same for visible VRAM if half of it is free */
744 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
745 u64 total_vis_vram = adev->gmc.visible_vram_size;
746 u64 used_vis_vram =
747 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
748
749 if (used_vis_vram < total_vis_vram) {
750 u64 free_vis_vram = total_vis_vram - used_vis_vram;
751
752 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
753 increment_us, us_upper_bound);
754
755 if (free_vis_vram >= total_vis_vram / 2)
756 adev->mm_stats.accum_us_vis =
757 max(bytes_to_us(adev, free_vis_vram / 2),
758 adev->mm_stats.accum_us_vis);
759 }
760
761 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
762 } else {
763 *max_vis_bytes = 0;
764 }
765
766 spin_unlock(&adev->mm_stats.lock);
767 }
768
769 /* Report how many bytes have really been moved for the last command
770 * submission. This can result in a debt that can stop buffer migrations
771 * temporarily.
772 */
amdgpu_cs_report_moved_bytes(struct amdgpu_device * adev,u64 num_bytes,u64 num_vis_bytes)773 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
774 u64 num_vis_bytes)
775 {
776 spin_lock(&adev->mm_stats.lock);
777 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
778 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
779 spin_unlock(&adev->mm_stats.lock);
780 }
781
amdgpu_cs_bo_validate(void * param,struct amdgpu_bo * bo)782 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
783 {
784 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
785 struct amdgpu_cs_parser *p = param;
786 struct ttm_operation_ctx ctx = {
787 .interruptible = true,
788 .no_wait_gpu = false,
789 .resv = bo->tbo.base.resv
790 };
791 uint32_t domain;
792 int r;
793
794 if (bo->tbo.pin_count)
795 return 0;
796
797 /* Don't move this buffer if we have depleted our allowance
798 * to move it. Don't move anything if the threshold is zero.
799 */
800 if (p->bytes_moved < p->bytes_moved_threshold &&
801 (!bo->tbo.base.dma_buf ||
802 list_empty(&bo->tbo.base.dma_buf->attachments))) {
803 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
804 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
805 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
806 * visible VRAM if we've depleted our allowance to do
807 * that.
808 */
809 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
810 domain = bo->preferred_domains;
811 else
812 domain = bo->allowed_domains;
813 } else {
814 domain = bo->preferred_domains;
815 }
816 } else {
817 domain = bo->allowed_domains;
818 }
819
820 retry:
821 amdgpu_bo_placement_from_domain(bo, domain);
822 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
823
824 p->bytes_moved += ctx.bytes_moved;
825 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
826 amdgpu_res_cpu_visible(adev, bo->tbo.resource))
827 p->bytes_moved_vis += ctx.bytes_moved;
828
829 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
830 domain = bo->allowed_domains;
831 goto retry;
832 }
833
834 return r;
835 }
836
amdgpu_cs_parser_bos(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)837 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
838 union drm_amdgpu_cs *cs)
839 {
840 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
841 struct ttm_operation_ctx ctx = { true, false };
842 struct amdgpu_vm *vm = &fpriv->vm;
843 struct amdgpu_bo_list_entry *e;
844 struct drm_gem_object *obj;
845 unsigned long index;
846 unsigned int i;
847 int r;
848
849 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
850 if (cs->in.bo_list_handle) {
851 if (p->bo_list)
852 return -EINVAL;
853
854 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
855 &p->bo_list);
856 if (r)
857 return r;
858 } else if (!p->bo_list) {
859 /* Create a empty bo_list when no handle is provided */
860 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
861 &p->bo_list);
862 if (r)
863 return r;
864 }
865
866 mutex_lock(&p->bo_list->bo_list_mutex);
867
868 /* Get userptr backing pages. If pages are updated after registered
869 * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
870 * amdgpu_ttm_backend_bind() to flush and invalidate new pages
871 */
872 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
873 bool userpage_invalidated = false;
874 struct amdgpu_bo *bo = e->bo;
875 int i;
876
877 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
878 sizeof(struct page *),
879 GFP_KERNEL | __GFP_ZERO);
880 if (!e->user_pages) {
881 DRM_ERROR("kvmalloc_array failure\n");
882 r = -ENOMEM;
883 goto out_free_user_pages;
884 }
885
886 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, &e->range);
887 if (r) {
888 kvfree(e->user_pages);
889 e->user_pages = NULL;
890 goto out_free_user_pages;
891 }
892
893 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
894 if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
895 userpage_invalidated = true;
896 break;
897 }
898 }
899 e->user_invalidated = userpage_invalidated;
900 }
901
902 drm_exec_until_all_locked(&p->exec) {
903 r = amdgpu_vm_lock_pd(&fpriv->vm, &p->exec, 1 + p->gang_size);
904 drm_exec_retry_on_contention(&p->exec);
905 if (unlikely(r))
906 goto out_free_user_pages;
907
908 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
909 /* One fence for TTM and one for each CS job */
910 r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base,
911 1 + p->gang_size);
912 drm_exec_retry_on_contention(&p->exec);
913 if (unlikely(r))
914 goto out_free_user_pages;
915
916 e->bo_va = amdgpu_vm_bo_find(vm, e->bo);
917 }
918
919 if (p->uf_bo) {
920 r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base,
921 1 + p->gang_size);
922 drm_exec_retry_on_contention(&p->exec);
923 if (unlikely(r))
924 goto out_free_user_pages;
925 }
926 }
927
928 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
929 struct mm_struct *usermm;
930
931 usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm);
932 if (usermm && usermm != current->mm) {
933 r = -EPERM;
934 goto out_free_user_pages;
935 }
936
937 if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) &&
938 e->user_invalidated && e->user_pages) {
939 amdgpu_bo_placement_from_domain(e->bo,
940 AMDGPU_GEM_DOMAIN_CPU);
941 r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement,
942 &ctx);
943 if (r)
944 goto out_free_user_pages;
945
946 amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm,
947 e->user_pages);
948 }
949
950 kvfree(e->user_pages);
951 e->user_pages = NULL;
952 }
953
954 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
955 &p->bytes_moved_vis_threshold);
956 p->bytes_moved = 0;
957 p->bytes_moved_vis = 0;
958
959 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
960 amdgpu_cs_bo_validate, p);
961 if (r) {
962 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
963 goto out_free_user_pages;
964 }
965
966 drm_exec_for_each_locked_object(&p->exec, index, obj) {
967 r = amdgpu_cs_bo_validate(p, gem_to_amdgpu_bo(obj));
968 if (unlikely(r))
969 goto out_free_user_pages;
970 }
971
972 if (p->uf_bo) {
973 r = amdgpu_ttm_alloc_gart(&p->uf_bo->tbo);
974 if (unlikely(r))
975 goto out_free_user_pages;
976
977 p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(p->uf_bo);
978 }
979
980 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
981 p->bytes_moved_vis);
982
983 for (i = 0; i < p->gang_size; ++i)
984 amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
985 p->bo_list->gws_obj,
986 p->bo_list->oa_obj);
987 return 0;
988
989 out_free_user_pages:
990 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
991 struct amdgpu_bo *bo = e->bo;
992
993 if (!e->user_pages)
994 continue;
995 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
996 kvfree(e->user_pages);
997 e->user_pages = NULL;
998 e->range = NULL;
999 }
1000 mutex_unlock(&p->bo_list->bo_list_mutex);
1001 return r;
1002 }
1003
trace_amdgpu_cs_ibs(struct amdgpu_cs_parser * p)1004 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
1005 {
1006 int i, j;
1007
1008 if (!trace_amdgpu_cs_enabled())
1009 return;
1010
1011 for (i = 0; i < p->gang_size; ++i) {
1012 struct amdgpu_job *job = p->jobs[i];
1013
1014 for (j = 0; j < job->num_ibs; ++j)
1015 trace_amdgpu_cs(p, job, &job->ibs[j]);
1016 }
1017 }
1018
amdgpu_cs_patch_ibs(struct amdgpu_cs_parser * p,struct amdgpu_job * job)1019 static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1020 struct amdgpu_job *job)
1021 {
1022 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1023 unsigned int i;
1024 int r;
1025
1026 /* Only for UVD/VCE VM emulation */
1027 if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1028 return 0;
1029
1030 for (i = 0; i < job->num_ibs; ++i) {
1031 struct amdgpu_ib *ib = &job->ibs[i];
1032 struct amdgpu_bo_va_mapping *m;
1033 struct amdgpu_bo *aobj;
1034 uint64_t va_start;
1035 uint8_t *kptr;
1036
1037 va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
1038 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
1039 if (r) {
1040 DRM_ERROR("IB va_start is invalid\n");
1041 return r;
1042 }
1043
1044 if ((va_start + ib->length_dw * 4) >
1045 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
1046 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
1047 return -EINVAL;
1048 }
1049
1050 /* the IB should be reserved at this point */
1051 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
1052 if (r)
1053 return r;
1054
1055 kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
1056
1057 if (ring->funcs->parse_cs) {
1058 memcpy(ib->ptr, kptr, ib->length_dw * 4);
1059 amdgpu_bo_kunmap(aobj);
1060
1061 r = amdgpu_ring_parse_cs(ring, p, job, ib);
1062 if (r)
1063 return r;
1064
1065 if (ib->sa_bo)
1066 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
1067 } else {
1068 ib->ptr = (uint32_t *)kptr;
1069 r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
1070 amdgpu_bo_kunmap(aobj);
1071 if (r)
1072 return r;
1073 }
1074 }
1075
1076 return 0;
1077 }
1078
amdgpu_cs_patch_jobs(struct amdgpu_cs_parser * p)1079 static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1080 {
1081 unsigned int i;
1082 int r;
1083
1084 for (i = 0; i < p->gang_size; ++i) {
1085 r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1086 if (r)
1087 return r;
1088 }
1089 return 0;
1090 }
1091
amdgpu_cs_vm_handling(struct amdgpu_cs_parser * p)1092 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1093 {
1094 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1095 struct amdgpu_job *job = p->gang_leader;
1096 struct amdgpu_device *adev = p->adev;
1097 struct amdgpu_vm *vm = &fpriv->vm;
1098 struct amdgpu_bo_list_entry *e;
1099 struct amdgpu_bo_va *bo_va;
1100 unsigned int i;
1101 int r;
1102
1103 /*
1104 * We can't use gang submit on with reserved VMIDs when the VM changes
1105 * can't be invalidated by more than one engine at the same time.
1106 */
1107 if (p->gang_size > 1 && !p->adev->vm_manager.concurrent_flush) {
1108 for (i = 0; i < p->gang_size; ++i) {
1109 struct drm_sched_entity *entity = p->entities[i];
1110 struct drm_gpu_scheduler *sched = entity->rq->sched;
1111 struct amdgpu_ring *ring = to_amdgpu_ring(sched);
1112
1113 if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub))
1114 return -EINVAL;
1115 }
1116 }
1117
1118 r = amdgpu_vm_clear_freed(adev, vm, NULL);
1119 if (r)
1120 return r;
1121
1122 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1123 if (r)
1124 return r;
1125
1126 r = amdgpu_sync_fence(&p->sync, fpriv->prt_va->last_pt_update);
1127 if (r)
1128 return r;
1129
1130 if (fpriv->csa_va) {
1131 bo_va = fpriv->csa_va;
1132 BUG_ON(!bo_va);
1133 r = amdgpu_vm_bo_update(adev, bo_va, false);
1134 if (r)
1135 return r;
1136
1137 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1138 if (r)
1139 return r;
1140 }
1141
1142 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1143 bo_va = e->bo_va;
1144 if (bo_va == NULL)
1145 continue;
1146
1147 r = amdgpu_vm_bo_update(adev, bo_va, false);
1148 if (r)
1149 return r;
1150
1151 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1152 if (r)
1153 return r;
1154 }
1155
1156 r = amdgpu_vm_handle_moved(adev, vm);
1157 if (r)
1158 return r;
1159
1160 r = amdgpu_vm_update_pdes(adev, vm, false);
1161 if (r)
1162 return r;
1163
1164 r = amdgpu_sync_fence(&p->sync, vm->last_update);
1165 if (r)
1166 return r;
1167
1168 for (i = 0; i < p->gang_size; ++i) {
1169 job = p->jobs[i];
1170
1171 if (!job->vm)
1172 continue;
1173
1174 job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1175 }
1176
1177 if (amdgpu_vm_debug) {
1178 /* Invalidate all BOs to test for userspace bugs */
1179 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1180 struct amdgpu_bo *bo = e->bo;
1181
1182 /* ignore duplicates */
1183 if (!bo)
1184 continue;
1185
1186 amdgpu_vm_bo_invalidate(adev, bo, false);
1187 }
1188 }
1189
1190 return 0;
1191 }
1192
amdgpu_cs_sync_rings(struct amdgpu_cs_parser * p)1193 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1194 {
1195 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1196 struct drm_gpu_scheduler *sched;
1197 struct drm_gem_object *obj;
1198 struct dma_fence *fence;
1199 unsigned long index;
1200 unsigned int i;
1201 int r;
1202
1203 r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_leader_idx]);
1204 if (r) {
1205 if (r != -ERESTARTSYS)
1206 DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
1207 return r;
1208 }
1209
1210 drm_exec_for_each_locked_object(&p->exec, index, obj) {
1211 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
1212
1213 struct dma_resv *resv = bo->tbo.base.resv;
1214 enum amdgpu_sync_mode sync_mode;
1215
1216 sync_mode = amdgpu_bo_explicit_sync(bo) ?
1217 AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
1218 r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode,
1219 &fpriv->vm);
1220 if (r)
1221 return r;
1222 }
1223
1224 for (i = 0; i < p->gang_size; ++i) {
1225 r = amdgpu_sync_push_to_job(&p->sync, p->jobs[i]);
1226 if (r)
1227 return r;
1228 }
1229
1230 sched = p->gang_leader->base.entity->rq->sched;
1231 while ((fence = amdgpu_sync_get_fence(&p->sync))) {
1232 struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1233
1234 /*
1235 * When we have an dependency it might be necessary to insert a
1236 * pipeline sync to make sure that all caches etc are flushed and the
1237 * next job actually sees the results from the previous one
1238 * before we start executing on the same scheduler ring.
1239 */
1240 if (!s_fence || s_fence->sched != sched) {
1241 dma_fence_put(fence);
1242 continue;
1243 }
1244
1245 r = amdgpu_sync_fence(&p->gang_leader->explicit_sync, fence);
1246 dma_fence_put(fence);
1247 if (r)
1248 return r;
1249 }
1250 return 0;
1251 }
1252
amdgpu_cs_post_dependencies(struct amdgpu_cs_parser * p)1253 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1254 {
1255 int i;
1256
1257 for (i = 0; i < p->num_post_deps; ++i) {
1258 if (p->post_deps[i].chain && p->post_deps[i].point) {
1259 drm_syncobj_add_point(p->post_deps[i].syncobj,
1260 p->post_deps[i].chain,
1261 p->fence, p->post_deps[i].point);
1262 p->post_deps[i].chain = NULL;
1263 } else {
1264 drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1265 p->fence);
1266 }
1267 }
1268 }
1269
amdgpu_cs_submit(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)1270 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1271 union drm_amdgpu_cs *cs)
1272 {
1273 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1274 struct amdgpu_job *leader = p->gang_leader;
1275 struct amdgpu_bo_list_entry *e;
1276 struct drm_gem_object *gobj;
1277 unsigned long index;
1278 unsigned int i;
1279 uint64_t seq;
1280 int r;
1281
1282 for (i = 0; i < p->gang_size; ++i)
1283 drm_sched_job_arm(&p->jobs[i]->base);
1284
1285 for (i = 0; i < p->gang_size; ++i) {
1286 struct dma_fence *fence;
1287
1288 if (p->jobs[i] == leader)
1289 continue;
1290
1291 fence = &p->jobs[i]->base.s_fence->scheduled;
1292 dma_fence_get(fence);
1293 r = drm_sched_job_add_dependency(&leader->base, fence);
1294 if (r) {
1295 dma_fence_put(fence);
1296 return r;
1297 }
1298 }
1299
1300 if (p->gang_size > 1) {
1301 for (i = 0; i < p->gang_size; ++i)
1302 amdgpu_job_set_gang_leader(p->jobs[i], leader);
1303 }
1304
1305 /* No memory allocation is allowed while holding the notifier lock.
1306 * The lock is held until amdgpu_cs_submit is finished and fence is
1307 * added to BOs.
1308 */
1309 mutex_lock(&p->adev->notifier_lock);
1310
1311 /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1312 * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1313 */
1314 r = 0;
1315 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1316 r |= !amdgpu_ttm_tt_get_user_pages_done(e->bo->tbo.ttm,
1317 e->range);
1318 e->range = NULL;
1319 }
1320 if (r) {
1321 r = -EAGAIN;
1322 mutex_unlock(&p->adev->notifier_lock);
1323 return r;
1324 }
1325
1326 p->fence = dma_fence_get(&leader->base.s_fence->finished);
1327 drm_exec_for_each_locked_object(&p->exec, index, gobj) {
1328
1329 ttm_bo_move_to_lru_tail_unlocked(&gem_to_amdgpu_bo(gobj)->tbo);
1330
1331 /* Everybody except for the gang leader uses READ */
1332 for (i = 0; i < p->gang_size; ++i) {
1333 if (p->jobs[i] == leader)
1334 continue;
1335
1336 dma_resv_add_fence(gobj->resv,
1337 &p->jobs[i]->base.s_fence->finished,
1338 DMA_RESV_USAGE_READ);
1339 }
1340
1341 /* The gang leader as remembered as writer */
1342 dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE);
1343 }
1344
1345 seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
1346 p->fence);
1347 amdgpu_cs_post_dependencies(p);
1348
1349 if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1350 !p->ctx->preamble_presented) {
1351 leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1352 p->ctx->preamble_presented = true;
1353 }
1354
1355 cs->out.handle = seq;
1356 leader->uf_sequence = seq;
1357
1358 amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->exec.ticket);
1359 for (i = 0; i < p->gang_size; ++i) {
1360 amdgpu_job_free_resources(p->jobs[i]);
1361 trace_amdgpu_cs_ioctl(p->jobs[i]);
1362 drm_sched_entity_push_job(&p->jobs[i]->base);
1363 p->jobs[i] = NULL;
1364 }
1365
1366 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1367
1368 mutex_unlock(&p->adev->notifier_lock);
1369 mutex_unlock(&p->bo_list->bo_list_mutex);
1370 return 0;
1371 }
1372
1373 /* Cleanup the parser structure */
amdgpu_cs_parser_fini(struct amdgpu_cs_parser * parser)1374 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1375 {
1376 unsigned int i;
1377
1378 amdgpu_sync_free(&parser->sync);
1379 drm_exec_fini(&parser->exec);
1380
1381 for (i = 0; i < parser->num_post_deps; i++) {
1382 drm_syncobj_put(parser->post_deps[i].syncobj);
1383 kfree(parser->post_deps[i].chain);
1384 }
1385 kfree(parser->post_deps);
1386
1387 dma_fence_put(parser->fence);
1388
1389 if (parser->ctx)
1390 amdgpu_ctx_put(parser->ctx);
1391 if (parser->bo_list)
1392 amdgpu_bo_list_put(parser->bo_list);
1393
1394 for (i = 0; i < parser->nchunks; i++)
1395 kvfree(parser->chunks[i].kdata);
1396 kvfree(parser->chunks);
1397 for (i = 0; i < parser->gang_size; ++i) {
1398 if (parser->jobs[i])
1399 amdgpu_job_free(parser->jobs[i]);
1400 }
1401 amdgpu_bo_unref(&parser->uf_bo);
1402 }
1403
amdgpu_cs_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1404 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1405 {
1406 struct amdgpu_device *adev = drm_to_adev(dev);
1407 struct amdgpu_cs_parser parser;
1408 int r;
1409
1410 if (amdgpu_ras_intr_triggered())
1411 return -EHWPOISON;
1412
1413 if (!adev->accel_working)
1414 return -EBUSY;
1415
1416 r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1417 if (r) {
1418 if (printk_ratelimit())
1419 DRM_ERROR("Failed to initialize parser %d!\n", r);
1420 return r;
1421 }
1422
1423 r = amdgpu_cs_pass1(&parser, data);
1424 if (r)
1425 goto error_fini;
1426
1427 r = amdgpu_cs_pass2(&parser);
1428 if (r)
1429 goto error_fini;
1430
1431 r = amdgpu_cs_parser_bos(&parser, data);
1432 if (r) {
1433 if (r == -ENOMEM)
1434 DRM_ERROR("Not enough memory for command submission!\n");
1435 else if (r != -ERESTARTSYS && r != -EAGAIN)
1436 DRM_DEBUG("Failed to process the buffer list %d!\n", r);
1437 goto error_fini;
1438 }
1439
1440 r = amdgpu_cs_patch_jobs(&parser);
1441 if (r)
1442 goto error_backoff;
1443
1444 r = amdgpu_cs_vm_handling(&parser);
1445 if (r)
1446 goto error_backoff;
1447
1448 r = amdgpu_cs_sync_rings(&parser);
1449 if (r)
1450 goto error_backoff;
1451
1452 trace_amdgpu_cs_ibs(&parser);
1453
1454 r = amdgpu_cs_submit(&parser, data);
1455 if (r)
1456 goto error_backoff;
1457
1458 amdgpu_cs_parser_fini(&parser);
1459 return 0;
1460
1461 error_backoff:
1462 mutex_unlock(&parser.bo_list->bo_list_mutex);
1463
1464 error_fini:
1465 amdgpu_cs_parser_fini(&parser);
1466 return r;
1467 }
1468
1469 /**
1470 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1471 *
1472 * @dev: drm device
1473 * @data: data from userspace
1474 * @filp: file private
1475 *
1476 * Wait for the command submission identified by handle to finish.
1477 */
amdgpu_cs_wait_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1478 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1479 struct drm_file *filp)
1480 {
1481 union drm_amdgpu_wait_cs *wait = data;
1482 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1483 struct drm_sched_entity *entity;
1484 struct amdgpu_ctx *ctx;
1485 struct dma_fence *fence;
1486 long r;
1487
1488 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1489 if (ctx == NULL)
1490 return -EINVAL;
1491
1492 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1493 wait->in.ring, &entity);
1494 if (r) {
1495 amdgpu_ctx_put(ctx);
1496 return r;
1497 }
1498
1499 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1500 if (IS_ERR(fence))
1501 r = PTR_ERR(fence);
1502 else if (fence) {
1503 r = dma_fence_wait_timeout(fence, true, timeout);
1504 if (r > 0 && fence->error)
1505 r = fence->error;
1506 dma_fence_put(fence);
1507 } else
1508 r = 1;
1509
1510 amdgpu_ctx_put(ctx);
1511 if (r < 0)
1512 return r;
1513
1514 memset(wait, 0, sizeof(*wait));
1515 wait->out.status = (r == 0);
1516
1517 return 0;
1518 }
1519
1520 /**
1521 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1522 *
1523 * @adev: amdgpu device
1524 * @filp: file private
1525 * @user: drm_amdgpu_fence copied from user space
1526 */
amdgpu_cs_get_fence(struct amdgpu_device * adev,struct drm_file * filp,struct drm_amdgpu_fence * user)1527 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1528 struct drm_file *filp,
1529 struct drm_amdgpu_fence *user)
1530 {
1531 struct drm_sched_entity *entity;
1532 struct amdgpu_ctx *ctx;
1533 struct dma_fence *fence;
1534 int r;
1535
1536 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1537 if (ctx == NULL)
1538 return ERR_PTR(-EINVAL);
1539
1540 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1541 user->ring, &entity);
1542 if (r) {
1543 amdgpu_ctx_put(ctx);
1544 return ERR_PTR(r);
1545 }
1546
1547 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1548 amdgpu_ctx_put(ctx);
1549
1550 return fence;
1551 }
1552
amdgpu_cs_fence_to_handle_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1553 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1554 struct drm_file *filp)
1555 {
1556 struct amdgpu_device *adev = drm_to_adev(dev);
1557 union drm_amdgpu_fence_to_handle *info = data;
1558 struct dma_fence *fence;
1559 struct drm_syncobj *syncobj;
1560 struct sync_file *sync_file;
1561 int fd, r;
1562
1563 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1564 if (IS_ERR(fence))
1565 return PTR_ERR(fence);
1566
1567 if (!fence)
1568 fence = dma_fence_get_stub();
1569
1570 switch (info->in.what) {
1571 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1572 r = drm_syncobj_create(&syncobj, 0, fence);
1573 dma_fence_put(fence);
1574 if (r)
1575 return r;
1576 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1577 drm_syncobj_put(syncobj);
1578 return r;
1579
1580 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1581 r = drm_syncobj_create(&syncobj, 0, fence);
1582 dma_fence_put(fence);
1583 if (r)
1584 return r;
1585 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1586 drm_syncobj_put(syncobj);
1587 return r;
1588
1589 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1590 fd = get_unused_fd_flags(O_CLOEXEC);
1591 if (fd < 0) {
1592 dma_fence_put(fence);
1593 return fd;
1594 }
1595
1596 sync_file = sync_file_create(fence);
1597 dma_fence_put(fence);
1598 if (!sync_file) {
1599 put_unused_fd(fd);
1600 return -ENOMEM;
1601 }
1602
1603 fd_install(fd, sync_file->file);
1604 info->out.handle = fd;
1605 return 0;
1606
1607 default:
1608 dma_fence_put(fence);
1609 return -EINVAL;
1610 }
1611 }
1612
1613 /**
1614 * amdgpu_cs_wait_all_fences - wait on all fences to signal
1615 *
1616 * @adev: amdgpu device
1617 * @filp: file private
1618 * @wait: wait parameters
1619 * @fences: array of drm_amdgpu_fence
1620 */
amdgpu_cs_wait_all_fences(struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_wait_fences * wait,struct drm_amdgpu_fence * fences)1621 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1622 struct drm_file *filp,
1623 union drm_amdgpu_wait_fences *wait,
1624 struct drm_amdgpu_fence *fences)
1625 {
1626 uint32_t fence_count = wait->in.fence_count;
1627 unsigned int i;
1628 long r = 1;
1629
1630 for (i = 0; i < fence_count; i++) {
1631 struct dma_fence *fence;
1632 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1633
1634 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1635 if (IS_ERR(fence))
1636 return PTR_ERR(fence);
1637 else if (!fence)
1638 continue;
1639
1640 r = dma_fence_wait_timeout(fence, true, timeout);
1641 if (r > 0 && fence->error)
1642 r = fence->error;
1643
1644 dma_fence_put(fence);
1645 if (r < 0)
1646 return r;
1647
1648 if (r == 0)
1649 break;
1650 }
1651
1652 memset(wait, 0, sizeof(*wait));
1653 wait->out.status = (r > 0);
1654
1655 return 0;
1656 }
1657
1658 /**
1659 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1660 *
1661 * @adev: amdgpu device
1662 * @filp: file private
1663 * @wait: wait parameters
1664 * @fences: array of drm_amdgpu_fence
1665 */
amdgpu_cs_wait_any_fence(struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_wait_fences * wait,struct drm_amdgpu_fence * fences)1666 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1667 struct drm_file *filp,
1668 union drm_amdgpu_wait_fences *wait,
1669 struct drm_amdgpu_fence *fences)
1670 {
1671 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1672 uint32_t fence_count = wait->in.fence_count;
1673 uint32_t first = ~0;
1674 struct dma_fence **array;
1675 unsigned int i;
1676 long r;
1677
1678 /* Prepare the fence array */
1679 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1680
1681 if (array == NULL)
1682 return -ENOMEM;
1683
1684 for (i = 0; i < fence_count; i++) {
1685 struct dma_fence *fence;
1686
1687 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1688 if (IS_ERR(fence)) {
1689 r = PTR_ERR(fence);
1690 goto err_free_fence_array;
1691 } else if (fence) {
1692 array[i] = fence;
1693 } else { /* NULL, the fence has been already signaled */
1694 r = 1;
1695 first = i;
1696 goto out;
1697 }
1698 }
1699
1700 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1701 &first);
1702 if (r < 0)
1703 goto err_free_fence_array;
1704
1705 out:
1706 memset(wait, 0, sizeof(*wait));
1707 wait->out.status = (r > 0);
1708 wait->out.first_signaled = first;
1709
1710 if (first < fence_count && array[first])
1711 r = array[first]->error;
1712 else
1713 r = 0;
1714
1715 err_free_fence_array:
1716 for (i = 0; i < fence_count; i++)
1717 dma_fence_put(array[i]);
1718 kfree(array);
1719
1720 return r;
1721 }
1722
1723 /**
1724 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1725 *
1726 * @dev: drm device
1727 * @data: data from userspace
1728 * @filp: file private
1729 */
amdgpu_cs_wait_fences_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1730 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1731 struct drm_file *filp)
1732 {
1733 struct amdgpu_device *adev = drm_to_adev(dev);
1734 union drm_amdgpu_wait_fences *wait = data;
1735 uint32_t fence_count = wait->in.fence_count;
1736 struct drm_amdgpu_fence *fences_user;
1737 struct drm_amdgpu_fence *fences;
1738 int r;
1739
1740 /* Get the fences from userspace */
1741 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1742 GFP_KERNEL);
1743 if (fences == NULL)
1744 return -ENOMEM;
1745
1746 fences_user = u64_to_user_ptr(wait->in.fences);
1747 if (copy_from_user(fences, fences_user,
1748 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1749 r = -EFAULT;
1750 goto err_free_fences;
1751 }
1752
1753 if (wait->in.wait_all)
1754 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1755 else
1756 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1757
1758 err_free_fences:
1759 kfree(fences);
1760
1761 return r;
1762 }
1763
1764 /**
1765 * amdgpu_cs_find_mapping - find bo_va for VM address
1766 *
1767 * @parser: command submission parser context
1768 * @addr: VM address
1769 * @bo: resulting BO of the mapping found
1770 * @map: Placeholder to return found BO mapping
1771 *
1772 * Search the buffer objects in the command submission context for a certain
1773 * virtual memory address. Returns allocation structure when found, NULL
1774 * otherwise.
1775 */
amdgpu_cs_find_mapping(struct amdgpu_cs_parser * parser,uint64_t addr,struct amdgpu_bo ** bo,struct amdgpu_bo_va_mapping ** map)1776 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1777 uint64_t addr, struct amdgpu_bo **bo,
1778 struct amdgpu_bo_va_mapping **map)
1779 {
1780 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1781 struct ttm_operation_ctx ctx = { false, false };
1782 struct amdgpu_vm *vm = &fpriv->vm;
1783 struct amdgpu_bo_va_mapping *mapping;
1784 int r;
1785
1786 addr /= AMDGPU_GPU_PAGE_SIZE;
1787
1788 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1789 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1790 return -EINVAL;
1791
1792 *bo = mapping->bo_va->base.bo;
1793 *map = mapping;
1794
1795 /* Double check that the BO is reserved by this CS */
1796 if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket)
1797 return -EINVAL;
1798
1799 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1800 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1801 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1802 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1803 if (r)
1804 return r;
1805 }
1806
1807 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1808 }
1809