1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 */
7
8 #include <linux/delay.h>
9 #include <linux/errno.h>
10 #include <linux/io.h>
11 #include <linux/sizes.h>
12 #include <linux/types.h>
13 #include <dm.h>
14 #include <fdtdec.h>
15 #include <i2c.h>
16
17 struct uniphier_i2c_regs {
18 u32 dtrm; /* data transmission */
19 #define I2C_DTRM_STA (1 << 10)
20 #define I2C_DTRM_STO (1 << 9)
21 #define I2C_DTRM_NACK (1 << 8)
22 #define I2C_DTRM_RD (1 << 0)
23 u32 drec; /* data reception */
24 #define I2C_DREC_STS (1 << 12)
25 #define I2C_DREC_LRB (1 << 11)
26 #define I2C_DREC_LAB (1 << 9)
27 u32 myad; /* slave address */
28 u32 clk; /* clock frequency control */
29 u32 brst; /* bus reset */
30 #define I2C_BRST_FOEN (1 << 1)
31 #define I2C_BRST_BRST (1 << 0)
32 u32 hold; /* hold time control */
33 u32 bsts; /* bus status monitor */
34 u32 noise; /* noise filter control */
35 u32 setup; /* setup time control */
36 };
37
38 #define IOBUS_FREQ 100000000
39
40 struct uniphier_i2c_priv {
41 struct udevice *dev;
42 struct uniphier_i2c_regs __iomem *regs; /* register base */
43 unsigned long input_clk; /* master clock (Hz) */
44 unsigned long wait_us; /* wait for every byte transfer (us) */
45 };
46
uniphier_i2c_probe(struct udevice * dev)47 static int uniphier_i2c_probe(struct udevice *dev)
48 {
49 fdt_addr_t addr;
50 struct uniphier_i2c_priv *priv = dev_get_priv(dev);
51
52 addr = devfdt_get_addr(dev);
53 if (addr == FDT_ADDR_T_NONE)
54 return -EINVAL;
55
56 priv->regs = devm_ioremap(dev, addr, SZ_64);
57 if (!priv->regs)
58 return -ENOMEM;
59
60 priv->input_clk = IOBUS_FREQ;
61
62 priv->dev = dev;
63
64 /* deassert reset */
65 writel(0x3, &priv->regs->brst);
66
67 return 0;
68 }
69
send_and_recv_byte(struct uniphier_i2c_priv * priv,u32 dtrm)70 static int send_and_recv_byte(struct uniphier_i2c_priv *priv, u32 dtrm)
71 {
72 writel(dtrm, &priv->regs->dtrm);
73
74 /*
75 * This controller only provides interruption to inform the completion
76 * of each byte transfer. (No status register to poll it.)
77 * Unfortunately, U-Boot does not have a good support of interrupt.
78 * Wait for a while.
79 */
80 udelay(priv->wait_us);
81
82 return readl(&priv->regs->drec);
83 }
84
send_byte(struct uniphier_i2c_priv * priv,u32 dtrm,bool * stop)85 static int send_byte(struct uniphier_i2c_priv *priv, u32 dtrm, bool *stop)
86 {
87 int ret = 0;
88 u32 drec;
89
90 drec = send_and_recv_byte(priv, dtrm);
91
92 if (drec & I2C_DREC_LAB) {
93 dev_dbg(priv->dev, "uniphier_i2c: bus arbitration failed\n");
94 *stop = false;
95 ret = -EREMOTEIO;
96 }
97 if (drec & I2C_DREC_LRB) {
98 dev_dbg(priv->dev, "uniphier_i2c: slave did not return ACK\n");
99 ret = -EREMOTEIO;
100 }
101 return ret;
102 }
103
uniphier_i2c_transmit(struct uniphier_i2c_priv * priv,uint addr,uint len,const u8 * buf,bool * stop)104 static int uniphier_i2c_transmit(struct uniphier_i2c_priv *priv, uint addr,
105 uint len, const u8 *buf, bool *stop)
106 {
107 int ret;
108
109 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
110
111 ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK | addr << 1, stop);
112 if (ret < 0)
113 goto fail;
114
115 while (len--) {
116 ret = send_byte(priv, I2C_DTRM_NACK | *buf++, stop);
117 if (ret < 0)
118 goto fail;
119 }
120
121 fail:
122 if (*stop)
123 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
124
125 return ret;
126 }
127
uniphier_i2c_receive(struct uniphier_i2c_priv * priv,uint addr,uint len,u8 * buf,bool * stop)128 static int uniphier_i2c_receive(struct uniphier_i2c_priv *priv, uint addr,
129 uint len, u8 *buf, bool *stop)
130 {
131 int ret;
132
133 dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
134
135 ret = send_byte(priv, I2C_DTRM_STA | I2C_DTRM_NACK |
136 I2C_DTRM_RD | addr << 1, stop);
137 if (ret < 0)
138 goto fail;
139
140 while (len--)
141 *buf++ = send_and_recv_byte(priv, len ? 0 : I2C_DTRM_NACK);
142
143 fail:
144 if (*stop)
145 writel(I2C_DTRM_STO | I2C_DTRM_NACK, &priv->regs->dtrm);
146
147 return ret;
148 }
149
uniphier_i2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)150 static int uniphier_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
151 int nmsgs)
152 {
153 int ret = 0;
154 struct uniphier_i2c_priv *priv = dev_get_priv(bus);
155 bool stop;
156
157 for (; nmsgs > 0; nmsgs--, msg++) {
158 /* If next message is read, skip the stop condition */
159 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
160
161 if (msg->flags & I2C_M_RD)
162 ret = uniphier_i2c_receive(priv, msg->addr, msg->len,
163 msg->buf, &stop);
164 else
165 ret = uniphier_i2c_transmit(priv, msg->addr, msg->len,
166 msg->buf, &stop);
167
168 if (ret < 0)
169 break;
170 }
171
172 return ret;
173 }
174
uniphier_i2c_set_bus_speed(struct udevice * bus,unsigned int speed)175 static int uniphier_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
176 {
177 struct uniphier_i2c_priv *priv = dev_get_priv(bus);
178
179 /* max supported frequency is 400 kHz */
180 if (speed > 400000)
181 return -EINVAL;
182
183 /* bus reset: make sure the bus is idle when change the frequency */
184 writel(0x1, &priv->regs->brst);
185
186 writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed),
187 &priv->regs->clk);
188
189 writel(0x3, &priv->regs->brst);
190
191 /*
192 * Theoretically, each byte can be transferred in
193 * 1000000 * 9 / speed usec. For safety, wait more than double.
194 */
195 priv->wait_us = 20000000 / speed;
196
197 return 0;
198 }
199
200
201 static const struct dm_i2c_ops uniphier_i2c_ops = {
202 .xfer = uniphier_i2c_xfer,
203 .set_bus_speed = uniphier_i2c_set_bus_speed,
204 };
205
206 static const struct udevice_id uniphier_i2c_of_match[] = {
207 { .compatible = "socionext,uniphier-i2c" },
208 { /* sentinel */ }
209 };
210
211 U_BOOT_DRIVER(uniphier_i2c) = {
212 .name = "uniphier-i2c",
213 .id = UCLASS_I2C,
214 .of_match = uniphier_i2c_of_match,
215 .probe = uniphier_i2c_probe,
216 .priv_auto_alloc_size = sizeof(struct uniphier_i2c_priv),
217 .ops = &uniphier_i2c_ops,
218 };
219