1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21 
22 #include <ufs/unipro.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
29 
30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
31 
32 /* QPHY_SW_RESET bit */
33 #define SW_RESET				BIT(0)
34 /* QPHY_POWER_DOWN_CONTROL */
35 #define SW_PWRDN				BIT(0)
36 /* QPHY_START_CONTROL bits */
37 #define SERDES_START				BIT(0)
38 #define PCS_START				BIT(1)
39 /* QPHY_PCS_READY_STATUS bit */
40 #define PCS_READY				BIT(0)
41 
42 #define PHY_INIT_COMPLETE_TIMEOUT		10000
43 
44 struct qmp_phy_init_tbl {
45 	unsigned int offset;
46 	unsigned int val;
47 	/*
48 	 * mask of lanes for which this register is written
49 	 * for cases when second lane needs different values
50 	 */
51 	u8 lane_mask;
52 };
53 
54 #define QMP_PHY_INIT_CFG(o, v)		\
55 	{				\
56 		.offset = o,		\
57 		.val = v,		\
58 		.lane_mask = 0xff,	\
59 	}
60 
61 #define QMP_PHY_INIT_CFG_LANE(o, v, l)	\
62 	{				\
63 		.offset = o,		\
64 		.val = v,		\
65 		.lane_mask = l,		\
66 	}
67 
68 /* set of registers with offsets different per-PHY */
69 enum qphy_reg_layout {
70 	/* PCS registers */
71 	QPHY_SW_RESET,
72 	QPHY_START_CTRL,
73 	QPHY_PCS_READY_STATUS,
74 	QPHY_PCS_POWER_DOWN_CONTROL,
75 	/* Keep last to ensure regs_layout arrays are properly initialized */
76 	QPHY_LAYOUT_SIZE
77 };
78 
79 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
80 	[QPHY_START_CTRL]		= QPHY_V2_PCS_UFS_PHY_START,
81 	[QPHY_PCS_READY_STATUS]		= QPHY_V2_PCS_UFS_READY_STATUS,
82 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
83 };
84 
85 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
86 	[QPHY_START_CTRL]		= QPHY_V3_PCS_UFS_PHY_START,
87 	[QPHY_PCS_READY_STATUS]		= QPHY_V3_PCS_UFS_READY_STATUS,
88 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
89 };
90 
91 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
92 	[QPHY_START_CTRL]		= QPHY_V4_PCS_UFS_PHY_START,
93 	[QPHY_PCS_READY_STATUS]		= QPHY_V4_PCS_UFS_READY_STATUS,
94 	[QPHY_SW_RESET]			= QPHY_V4_PCS_UFS_SW_RESET,
95 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
96 };
97 
98 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
99 	[QPHY_START_CTRL]		= QPHY_V5_PCS_UFS_PHY_START,
100 	[QPHY_PCS_READY_STATUS]		= QPHY_V5_PCS_UFS_READY_STATUS,
101 	[QPHY_SW_RESET]			= QPHY_V5_PCS_UFS_SW_RESET,
102 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
103 };
104 
105 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
106 	[QPHY_START_CTRL]		= QPHY_V6_PCS_UFS_PHY_START,
107 	[QPHY_PCS_READY_STATUS]		= QPHY_V6_PCS_UFS_READY_STATUS,
108 	[QPHY_SW_RESET]			= QPHY_V6_PCS_UFS_SW_RESET,
109 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
110 };
111 
112 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
113 	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
114 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
115 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
116 	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
117 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
118 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
119 	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
120 	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
121 	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
122 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
123 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
124 	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
125 	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
126 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
127 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
128 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
129 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
130 	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
131 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
132 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
133 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
134 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
135 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
136 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
137 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
138 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
139 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
140 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
141 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
142 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
143 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
144 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
145 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
146 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
147 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
148 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
149 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
150 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
151 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
152 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
153 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
154 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
155 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
156 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
157 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
158 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
159 };
160 
161 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
162 	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
163 	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
164 };
165 
166 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
167 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
168 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
169 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
170 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
171 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
172 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
173 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
174 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
175 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
176 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
177 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
178 };
179 
180 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
181 	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
182 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
183 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
184 	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
185 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
186 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
187 	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
188 	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
189 	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
190 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
191 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
192 	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
193 	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
194 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
195 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
196 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
197 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
198 	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
199 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
200 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
201 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
202 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
203 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
204 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
205 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
206 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
207 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
208 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
209 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
210 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
211 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
212 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
213 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
214 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
215 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
216 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
217 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
218 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
219 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
220 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
221 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
222 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
223 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
224 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
225 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
226 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
227 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
228 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
229 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
230 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
231 };
232 
233 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
234 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
235 };
236 
237 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
238 	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
239 	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
240 };
241 
242 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
243 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
244 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
245 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
246 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
247 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
248 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
249 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
250 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
251 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
252 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
253 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
254 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
255 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
256 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
257 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
258 };
259 
260 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
261 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
262 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
263 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
264 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
265 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
266 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
267 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
268 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
269 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
270 };
271 
272 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
273 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
274 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
275 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
276 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
277 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
278 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
279 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
280 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
281 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
282 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
283 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
284 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
285 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
286 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
287 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
288 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
289 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
290 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
291 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
292 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
293 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
294 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
295 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
296 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
297 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
298 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
299 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
300 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
301 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
302 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
303 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
304 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
305 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
306 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
307 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
308 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
309 };
310 
311 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
312 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
313 };
314 
315 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
316 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
317 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
318 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
319 };
320 
321 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
322 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
323 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
324 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
325 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
326 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
327 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
328 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
329 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
330 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
331 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
332 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
333 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
334 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
335 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
336 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
337 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
338 };
339 
340 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
341 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
342 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
343 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
344 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
345 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
346 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
347 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
348 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
349 };
350 
351 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
352 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
353 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
354 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
355 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
356 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
357 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
358 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
359 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
360 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
361 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
362 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
363 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
364 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
365 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
366 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
367 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
368 };
369 
370 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
371 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
372 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
373 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
374 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
375 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
376 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
377 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
378 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
379 };
380 
381 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
382 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
383 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
384 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
385 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
386 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
387 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
388 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
389 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
390 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
391 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
392 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
393 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
394 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
395 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
396 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
397 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
398 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
399 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
400 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
401 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
402 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
403 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
404 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
405 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
406 };
407 
408 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
409 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
410 };
411 
412 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
413 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
414 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
415 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
416 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
417 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
418 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
419 };
420 
421 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
422 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
423 };
424 
425 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
426 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
427 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
428 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
429 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
430 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
431 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
432 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
433 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
434 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
435 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
436 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
437 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
438 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
439 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
440 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
441 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
442 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
443 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
444 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
445 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
446 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
447 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
448 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
449 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
450 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
451 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
452 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
453 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
454 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
455 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
456 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
457 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
458 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
459 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
460 };
461 
462 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
463 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
464 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
465 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
466 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
467 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
468 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
469 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
470 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
471 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
472 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
473 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
474 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
475 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
476 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
477 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
478 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
479 };
480 
481 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
482 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
483 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
484 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
485 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
486 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
487 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
488 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
489 };
490 
491 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
492 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
493 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
494 };
495 
496 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
497 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
498 };
499 
500 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
501 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
502 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
503 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
504 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
505 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
506 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
507 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
508 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
509 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
510 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
511 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
512 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
513 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
514 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
515 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
516 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
517 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
518 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
519 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
520 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
521 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
522 };
523 
524 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
525 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
526 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
527 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
528 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
529 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
530 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
531 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
532 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
533 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
534 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
535 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
536 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
537 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
538 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
539 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
540 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
541 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
542 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
543 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
544 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
545 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
546 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
547 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
548 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
549 };
550 
551 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
552 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
553 };
554 
555 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
556 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
557 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
558 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
559 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
560 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
561 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
562 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
563 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
564 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
565 };
566 
567 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
568 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
569 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
570 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
571 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
572 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
573 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
574 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
575 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
576 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
577 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
578 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
579 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
580 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
581 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
582 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
583 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
584 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
585 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
586 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
587 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
588 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
589 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
590 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
591 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
592 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
593 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
594 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
595 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
596 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
597 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
598 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
599 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
600 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
601 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
602 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
603 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
604 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
605 };
606 
607 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
608 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
609 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
610 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
611 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
612 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
613 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
614 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
615 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
616 };
617 
618 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
619 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
620 };
621 
622 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
623 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
624 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
625 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
626 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
627 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
628 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
629 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
630 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
631 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
632 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
633 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
634 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
635 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
636 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
637 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
638 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
639 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
640 };
641 
642 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
643 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
644 };
645 
646 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
647 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
648 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
649 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
650 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
651 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
652 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
653 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
654 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
655 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
656 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
657 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
658 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
659 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
660 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
661 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
662 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
663 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
664 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
665 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
666 	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
667 };
668 
669 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
670 	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
671 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
672 };
673 
674 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
675 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
676 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
677 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
678 
679 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
680 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
681 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
682 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
683 
684 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
685 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
686 
687 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
688 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
689 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
690 	QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
691 };
692 
693 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
694 	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
695 	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
696 	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
697 	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
698 	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
699 };
700 
701 struct qmp_ufs_offsets {
702 	u16 serdes;
703 	u16 pcs;
704 	u16 tx;
705 	u16 rx;
706 	u16 tx2;
707 	u16 rx2;
708 };
709 
710 struct qmp_phy_cfg_tbls {
711 	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
712 	const struct qmp_phy_init_tbl *serdes;
713 	int serdes_num;
714 	const struct qmp_phy_init_tbl *tx;
715 	int tx_num;
716 	const struct qmp_phy_init_tbl *rx;
717 	int rx_num;
718 	const struct qmp_phy_init_tbl *pcs;
719 	int pcs_num;
720 };
721 
722 /* struct qmp_phy_cfg - per-PHY initialization config */
723 struct qmp_phy_cfg {
724 	int lanes;
725 
726 	const struct qmp_ufs_offsets *offsets;
727 
728 	/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
729 	const struct qmp_phy_cfg_tbls tbls;
730 	/* Additional sequence for HS Series B */
731 	const struct qmp_phy_cfg_tbls tbls_hs_b;
732 	/* Additional sequence for HS G4 */
733 	const struct qmp_phy_cfg_tbls tbls_hs_g4;
734 
735 	/* clock ids to be requested */
736 	const char * const *clk_list;
737 	int num_clks;
738 	/* regulators to be requested */
739 	const char * const *vreg_list;
740 	int num_vregs;
741 
742 	/* array of registers with different offsets */
743 	const unsigned int *regs;
744 
745 	/* true, if PCS block has no separate SW_RESET register */
746 	bool no_pcs_sw_reset;
747 };
748 
749 struct qmp_ufs {
750 	struct device *dev;
751 
752 	const struct qmp_phy_cfg *cfg;
753 
754 	void __iomem *serdes;
755 	void __iomem *pcs;
756 	void __iomem *pcs_misc;
757 	void __iomem *tx;
758 	void __iomem *rx;
759 	void __iomem *tx2;
760 	void __iomem *rx2;
761 
762 	struct clk_bulk_data *clks;
763 	struct regulator_bulk_data *vregs;
764 	struct reset_control *ufs_reset;
765 
766 	struct phy *phy;
767 	u32 mode;
768 	u32 submode;
769 };
770 
qphy_setbits(void __iomem * base,u32 offset,u32 val)771 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
772 {
773 	u32 reg;
774 
775 	reg = readl(base + offset);
776 	reg |= val;
777 	writel(reg, base + offset);
778 
779 	/* ensure that above write is through */
780 	readl(base + offset);
781 }
782 
qphy_clrbits(void __iomem * base,u32 offset,u32 val)783 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
784 {
785 	u32 reg;
786 
787 	reg = readl(base + offset);
788 	reg &= ~val;
789 	writel(reg, base + offset);
790 
791 	/* ensure that above write is through */
792 	readl(base + offset);
793 }
794 
795 /* list of clocks required by phy */
796 static const char * const msm8996_ufs_phy_clk_l[] = {
797 	"ref",
798 };
799 
800 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
801 static const char * const sm8450_ufs_phy_clk_l[] = {
802 	"qref", "ref", "ref_aux",
803 };
804 
805 static const char * const sdm845_ufs_phy_clk_l[] = {
806 	"ref", "ref_aux",
807 };
808 
809 /* list of regulators */
810 static const char * const qmp_phy_vreg_l[] = {
811 	"vdda-phy", "vdda-pll",
812 };
813 
814 static const struct qmp_ufs_offsets qmp_ufs_offsets = {
815 	.serdes		= 0,
816 	.pcs		= 0xc00,
817 	.tx		= 0x400,
818 	.rx		= 0x600,
819 	.tx2		= 0x800,
820 	.rx2		= 0xa00,
821 };
822 
823 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
824 	.serdes		= 0,
825 	.pcs		= 0x0400,
826 	.tx		= 0x1000,
827 	.rx		= 0x1200,
828 	.tx2		= 0x1800,
829 	.rx2		= 0x1a00,
830 };
831 
832 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
833 	.lanes			= 1,
834 
835 	.offsets		= &qmp_ufs_offsets,
836 
837 	.tbls = {
838 		.serdes		= msm8996_ufsphy_serdes,
839 		.serdes_num	= ARRAY_SIZE(msm8996_ufsphy_serdes),
840 		.tx		= msm8996_ufsphy_tx,
841 		.tx_num		= ARRAY_SIZE(msm8996_ufsphy_tx),
842 		.rx		= msm8996_ufsphy_rx,
843 		.rx_num		= ARRAY_SIZE(msm8996_ufsphy_rx),
844 	},
845 
846 	.clk_list		= msm8996_ufs_phy_clk_l,
847 	.num_clks		= ARRAY_SIZE(msm8996_ufs_phy_clk_l),
848 
849 	.vreg_list		= qmp_phy_vreg_l,
850 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
851 
852 	.regs			= ufsphy_v2_regs_layout,
853 
854 	.no_pcs_sw_reset	= true,
855 };
856 
857 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
858 	.lanes			= 2,
859 
860 	.offsets		= &qmp_ufs_offsets,
861 
862 	.tbls = {
863 		.serdes		= sm8350_ufsphy_serdes,
864 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_serdes),
865 		.tx		= sm8350_ufsphy_tx,
866 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_tx),
867 		.rx		= sm8350_ufsphy_rx,
868 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_rx),
869 		.pcs		= sm8350_ufsphy_pcs,
870 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_pcs),
871 	},
872 	.tbls_hs_b = {
873 		.serdes		= sm8350_ufsphy_hs_b_serdes,
874 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
875 	},
876 	.tbls_hs_g4 = {
877 		.tx		= sm8350_ufsphy_g4_tx,
878 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_tx),
879 		.rx		= sm8350_ufsphy_g4_rx,
880 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_rx),
881 		.pcs		= sm8350_ufsphy_g4_pcs,
882 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
883 	},
884 	.clk_list		= sm8450_ufs_phy_clk_l,
885 	.num_clks		= ARRAY_SIZE(sm8450_ufs_phy_clk_l),
886 	.vreg_list		= qmp_phy_vreg_l,
887 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
888 	.regs			= ufsphy_v5_regs_layout,
889 };
890 
891 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
892 	.lanes			= 2,
893 
894 	.offsets		= &qmp_ufs_offsets,
895 
896 	.tbls = {
897 		.serdes		= sm8350_ufsphy_serdes,
898 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_serdes),
899 		.tx		= sm8350_ufsphy_tx,
900 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_tx),
901 		.rx		= sm8350_ufsphy_rx,
902 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_rx),
903 		.pcs		= sm8350_ufsphy_pcs,
904 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_pcs),
905 	},
906 	.tbls_hs_b = {
907 		.serdes		= sm8350_ufsphy_hs_b_serdes,
908 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
909 	},
910 	.tbls_hs_g4 = {
911 		.tx		= sm8350_ufsphy_g4_tx,
912 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_tx),
913 		.rx		= sm8350_ufsphy_g4_rx,
914 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_rx),
915 		.pcs		= sm8350_ufsphy_g4_pcs,
916 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
917 	},
918 	.clk_list		= sdm845_ufs_phy_clk_l,
919 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
920 	.vreg_list		= qmp_phy_vreg_l,
921 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
922 	.regs			= ufsphy_v5_regs_layout,
923 };
924 
925 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
926 	.lanes			= 2,
927 
928 	.offsets		= &qmp_ufs_offsets,
929 
930 	.tbls = {
931 		.serdes		= sdm845_ufsphy_serdes,
932 		.serdes_num	= ARRAY_SIZE(sdm845_ufsphy_serdes),
933 		.tx		= sdm845_ufsphy_tx,
934 		.tx_num		= ARRAY_SIZE(sdm845_ufsphy_tx),
935 		.rx		= sdm845_ufsphy_rx,
936 		.rx_num		= ARRAY_SIZE(sdm845_ufsphy_rx),
937 		.pcs		= sdm845_ufsphy_pcs,
938 		.pcs_num	= ARRAY_SIZE(sdm845_ufsphy_pcs),
939 	},
940 	.tbls_hs_b = {
941 		.serdes		= sdm845_ufsphy_hs_b_serdes,
942 		.serdes_num	= ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
943 	},
944 	.clk_list		= sdm845_ufs_phy_clk_l,
945 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
946 	.vreg_list		= qmp_phy_vreg_l,
947 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
948 	.regs			= ufsphy_v3_regs_layout,
949 
950 	.no_pcs_sw_reset	= true,
951 };
952 
953 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
954 	.lanes			= 1,
955 
956 	.offsets		= &qmp_ufs_offsets,
957 
958 	.tbls = {
959 		.serdes		= sm6115_ufsphy_serdes,
960 		.serdes_num	= ARRAY_SIZE(sm6115_ufsphy_serdes),
961 		.tx		= sm6115_ufsphy_tx,
962 		.tx_num		= ARRAY_SIZE(sm6115_ufsphy_tx),
963 		.rx		= sm6115_ufsphy_rx,
964 		.rx_num		= ARRAY_SIZE(sm6115_ufsphy_rx),
965 		.pcs		= sm6115_ufsphy_pcs,
966 		.pcs_num	= ARRAY_SIZE(sm6115_ufsphy_pcs),
967 	},
968 	.tbls_hs_b = {
969 		.serdes		= sm6115_ufsphy_hs_b_serdes,
970 		.serdes_num	= ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
971 	},
972 	.clk_list		= sdm845_ufs_phy_clk_l,
973 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
974 	.vreg_list		= qmp_phy_vreg_l,
975 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
976 	.regs			= ufsphy_v2_regs_layout,
977 
978 	.no_pcs_sw_reset	= true,
979 };
980 
981 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
982 	.lanes			= 1,
983 
984 	.offsets		= &qmp_ufs_offsets,
985 
986 	.tbls = {
987 		.serdes		= sdm845_ufsphy_serdes,
988 		.serdes_num	= ARRAY_SIZE(sdm845_ufsphy_serdes),
989 		.tx		= sdm845_ufsphy_tx,
990 		.tx_num		= ARRAY_SIZE(sdm845_ufsphy_tx),
991 		.rx		= sm7150_ufsphy_rx,
992 		.rx_num		= ARRAY_SIZE(sm7150_ufsphy_rx),
993 		.pcs		= sm7150_ufsphy_pcs,
994 		.pcs_num	= ARRAY_SIZE(sm7150_ufsphy_pcs),
995 	},
996 	.tbls_hs_b = {
997 		.serdes		= sdm845_ufsphy_hs_b_serdes,
998 		.serdes_num	= ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
999 	},
1000 	.clk_list		= sdm845_ufs_phy_clk_l,
1001 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1002 	.vreg_list		= qmp_phy_vreg_l,
1003 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1004 	.regs			= ufsphy_v3_regs_layout,
1005 
1006 	.no_pcs_sw_reset	= true,
1007 };
1008 
1009 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1010 	.lanes			= 2,
1011 
1012 	.offsets		= &qmp_ufs_offsets,
1013 
1014 	.tbls = {
1015 		.serdes		= sm8150_ufsphy_serdes,
1016 		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_serdes),
1017 		.tx		= sm8150_ufsphy_tx,
1018 		.tx_num		= ARRAY_SIZE(sm8150_ufsphy_tx),
1019 		.rx		= sm8150_ufsphy_rx,
1020 		.rx_num		= ARRAY_SIZE(sm8150_ufsphy_rx),
1021 		.pcs		= sm8150_ufsphy_pcs,
1022 		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_pcs),
1023 	},
1024 	.tbls_hs_b = {
1025 		.serdes		= sm8150_ufsphy_hs_b_serdes,
1026 		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1027 	},
1028 	.tbls_hs_g4 = {
1029 		.tx		= sm8150_ufsphy_hs_g4_tx,
1030 		.tx_num		= ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
1031 		.rx		= sm8150_ufsphy_hs_g4_rx,
1032 		.rx_num		= ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
1033 		.pcs		= sm8150_ufsphy_hs_g4_pcs,
1034 		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1035 	},
1036 	.clk_list		= sdm845_ufs_phy_clk_l,
1037 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1038 	.vreg_list		= qmp_phy_vreg_l,
1039 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1040 	.regs			= ufsphy_v4_regs_layout,
1041 };
1042 
1043 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
1044 	.lanes			= 2,
1045 
1046 	.offsets		= &qmp_ufs_offsets,
1047 
1048 	.tbls = {
1049 		.serdes		= sm8150_ufsphy_serdes,
1050 		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_serdes),
1051 		.tx		= sm8150_ufsphy_tx,
1052 		.tx_num		= ARRAY_SIZE(sm8150_ufsphy_tx),
1053 		.rx		= sm8150_ufsphy_rx,
1054 		.rx_num		= ARRAY_SIZE(sm8150_ufsphy_rx),
1055 		.pcs		= sm8150_ufsphy_pcs,
1056 		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_pcs),
1057 	},
1058 	.tbls_hs_b = {
1059 		.serdes		= sm8150_ufsphy_hs_b_serdes,
1060 		.serdes_num	= ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1061 	},
1062 	.tbls_hs_g4 = {
1063 		.tx		= sm8250_ufsphy_hs_g4_tx,
1064 		.tx_num		= ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1065 		.rx		= sm8250_ufsphy_hs_g4_rx,
1066 		.rx_num		= ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
1067 		.pcs		= sm8150_ufsphy_hs_g4_pcs,
1068 		.pcs_num	= ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1069 	},
1070 	.clk_list		= sdm845_ufs_phy_clk_l,
1071 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1072 	.vreg_list		= qmp_phy_vreg_l,
1073 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1074 	.regs			= ufsphy_v4_regs_layout,
1075 };
1076 
1077 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
1078 	.lanes			= 2,
1079 
1080 	.offsets		= &qmp_ufs_offsets,
1081 
1082 	.tbls = {
1083 		.serdes		= sm8350_ufsphy_serdes,
1084 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_serdes),
1085 		.tx		= sm8350_ufsphy_tx,
1086 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_tx),
1087 		.rx		= sm8350_ufsphy_rx,
1088 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_rx),
1089 		.pcs		= sm8350_ufsphy_pcs,
1090 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_pcs),
1091 	},
1092 	.tbls_hs_b = {
1093 		.serdes		= sm8350_ufsphy_hs_b_serdes,
1094 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1095 	},
1096 	.tbls_hs_g4 = {
1097 		.tx		= sm8350_ufsphy_g4_tx,
1098 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1099 		.rx		= sm8350_ufsphy_g4_rx,
1100 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1101 		.pcs		= sm8350_ufsphy_g4_pcs,
1102 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1103 	},
1104 	.clk_list		= sdm845_ufs_phy_clk_l,
1105 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1106 	.vreg_list		= qmp_phy_vreg_l,
1107 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1108 	.regs			= ufsphy_v5_regs_layout,
1109 };
1110 
1111 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
1112 	.lanes			= 2,
1113 
1114 	.offsets		= &qmp_ufs_offsets,
1115 
1116 	.tbls = {
1117 		.serdes		= sm8350_ufsphy_serdes,
1118 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_serdes),
1119 		.tx		= sm8350_ufsphy_tx,
1120 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_tx),
1121 		.rx		= sm8350_ufsphy_rx,
1122 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_rx),
1123 		.pcs		= sm8350_ufsphy_pcs,
1124 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_pcs),
1125 	},
1126 	.tbls_hs_b = {
1127 		.serdes		= sm8350_ufsphy_hs_b_serdes,
1128 		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1129 	},
1130 	.tbls_hs_g4 = {
1131 		.tx		= sm8350_ufsphy_g4_tx,
1132 		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1133 		.rx		= sm8350_ufsphy_g4_rx,
1134 		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1135 		.pcs		= sm8350_ufsphy_g4_pcs,
1136 		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1137 	},
1138 	.clk_list		= sm8450_ufs_phy_clk_l,
1139 	.num_clks		= ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1140 	.vreg_list		= qmp_phy_vreg_l,
1141 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1142 	.regs			= ufsphy_v5_regs_layout,
1143 };
1144 
1145 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
1146 	.lanes			= 2,
1147 
1148 	.offsets		= &qmp_ufs_offsets_v6,
1149 
1150 	.tbls = {
1151 		.serdes		= sm8550_ufsphy_serdes,
1152 		.serdes_num	= ARRAY_SIZE(sm8550_ufsphy_serdes),
1153 		.tx		= sm8550_ufsphy_tx,
1154 		.tx_num		= ARRAY_SIZE(sm8550_ufsphy_tx),
1155 		.rx		= sm8550_ufsphy_rx,
1156 		.rx_num		= ARRAY_SIZE(sm8550_ufsphy_rx),
1157 		.pcs		= sm8550_ufsphy_pcs,
1158 		.pcs_num	= ARRAY_SIZE(sm8550_ufsphy_pcs),
1159 	},
1160 	.clk_list		= sdm845_ufs_phy_clk_l,
1161 	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1162 	.vreg_list		= qmp_phy_vreg_l,
1163 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1164 	.regs			= ufsphy_v6_regs_layout,
1165 };
1166 
qmp_ufs_configure_lane(void __iomem * base,const struct qmp_phy_init_tbl tbl[],int num,u8 lane_mask)1167 static void qmp_ufs_configure_lane(void __iomem *base,
1168 					const struct qmp_phy_init_tbl tbl[],
1169 					int num,
1170 					u8 lane_mask)
1171 {
1172 	int i;
1173 	const struct qmp_phy_init_tbl *t = tbl;
1174 
1175 	if (!t)
1176 		return;
1177 
1178 	for (i = 0; i < num; i++, t++) {
1179 		if (!(t->lane_mask & lane_mask))
1180 			continue;
1181 
1182 		writel(t->val, base + t->offset);
1183 	}
1184 }
1185 
qmp_ufs_configure(void __iomem * base,const struct qmp_phy_init_tbl tbl[],int num)1186 static void qmp_ufs_configure(void __iomem *base,
1187 				   const struct qmp_phy_init_tbl tbl[],
1188 				   int num)
1189 {
1190 	qmp_ufs_configure_lane(base, tbl, num, 0xff);
1191 }
1192 
qmp_ufs_serdes_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1193 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1194 {
1195 	void __iomem *serdes = qmp->serdes;
1196 
1197 	qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
1198 }
1199 
qmp_ufs_lanes_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1200 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1201 {
1202 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1203 	void __iomem *tx = qmp->tx;
1204 	void __iomem *rx = qmp->rx;
1205 
1206 	qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
1207 	qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1208 
1209 	if (cfg->lanes >= 2) {
1210 		qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
1211 		qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
1212 	}
1213 }
1214 
qmp_ufs_pcs_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1215 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1216 {
1217 	void __iomem *pcs = qmp->pcs;
1218 
1219 	qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
1220 }
1221 
qmp_ufs_init_registers(struct qmp_ufs * qmp,const struct qmp_phy_cfg * cfg)1222 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1223 {
1224 	qmp_ufs_serdes_init(qmp, &cfg->tbls);
1225 	if (qmp->mode == PHY_MODE_UFS_HS_B)
1226 		qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
1227 	qmp_ufs_lanes_init(qmp, &cfg->tbls);
1228 	if (qmp->submode == UFS_HS_G4)
1229 		qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
1230 	qmp_ufs_pcs_init(qmp, &cfg->tbls);
1231 	if (qmp->submode == UFS_HS_G4)
1232 		qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
1233 }
1234 
qmp_ufs_com_init(struct qmp_ufs * qmp)1235 static int qmp_ufs_com_init(struct qmp_ufs *qmp)
1236 {
1237 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1238 	void __iomem *pcs = qmp->pcs;
1239 	int ret;
1240 
1241 	ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1242 	if (ret) {
1243 		dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1244 		return ret;
1245 	}
1246 
1247 	ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1248 	if (ret)
1249 		goto err_disable_regulators;
1250 
1251 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1252 
1253 	return 0;
1254 
1255 err_disable_regulators:
1256 	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1257 
1258 	return ret;
1259 }
1260 
qmp_ufs_com_exit(struct qmp_ufs * qmp)1261 static int qmp_ufs_com_exit(struct qmp_ufs *qmp)
1262 {
1263 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1264 
1265 	reset_control_assert(qmp->ufs_reset);
1266 
1267 	clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1268 
1269 	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1270 
1271 	return 0;
1272 }
1273 
qmp_ufs_init(struct phy * phy)1274 static int qmp_ufs_init(struct phy *phy)
1275 {
1276 	struct qmp_ufs *qmp = phy_get_drvdata(phy);
1277 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1278 	int ret;
1279 	dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1280 
1281 	if (cfg->no_pcs_sw_reset) {
1282 		/*
1283 		 * Get UFS reset, which is delayed until now to avoid a
1284 		 * circular dependency where UFS needs its PHY, but the PHY
1285 		 * needs this UFS reset.
1286 		 */
1287 		if (!qmp->ufs_reset) {
1288 			qmp->ufs_reset =
1289 				devm_reset_control_get_exclusive(qmp->dev,
1290 								 "ufsphy");
1291 
1292 			if (IS_ERR(qmp->ufs_reset)) {
1293 				ret = PTR_ERR(qmp->ufs_reset);
1294 				dev_err(qmp->dev,
1295 					"failed to get UFS reset: %d\n",
1296 					ret);
1297 
1298 				qmp->ufs_reset = NULL;
1299 				return ret;
1300 			}
1301 		}
1302 
1303 		ret = reset_control_assert(qmp->ufs_reset);
1304 		if (ret)
1305 			return ret;
1306 	}
1307 
1308 	ret = qmp_ufs_com_init(qmp);
1309 	if (ret)
1310 		return ret;
1311 
1312 	return 0;
1313 }
1314 
qmp_ufs_power_on(struct phy * phy)1315 static int qmp_ufs_power_on(struct phy *phy)
1316 {
1317 	struct qmp_ufs *qmp = phy_get_drvdata(phy);
1318 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1319 	void __iomem *pcs = qmp->pcs;
1320 	void __iomem *status;
1321 	unsigned int val;
1322 	int ret;
1323 
1324 	qmp_ufs_init_registers(qmp, cfg);
1325 
1326 	ret = reset_control_deassert(qmp->ufs_reset);
1327 	if (ret)
1328 		return ret;
1329 
1330 	/* Pull PHY out of reset state */
1331 	if (!cfg->no_pcs_sw_reset)
1332 		qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1333 
1334 	/* start SerDes */
1335 	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1336 
1337 	status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1338 	ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
1339 				 PHY_INIT_COMPLETE_TIMEOUT);
1340 	if (ret) {
1341 		dev_err(qmp->dev, "phy initialization timed-out\n");
1342 		return ret;
1343 	}
1344 
1345 	return 0;
1346 }
1347 
qmp_ufs_power_off(struct phy * phy)1348 static int qmp_ufs_power_off(struct phy *phy)
1349 {
1350 	struct qmp_ufs *qmp = phy_get_drvdata(phy);
1351 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1352 
1353 	/* PHY reset */
1354 	if (!cfg->no_pcs_sw_reset)
1355 		qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1356 
1357 	/* stop SerDes */
1358 	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1359 
1360 	/* Put PHY into POWER DOWN state: active low */
1361 	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1362 			SW_PWRDN);
1363 
1364 	return 0;
1365 }
1366 
qmp_ufs_exit(struct phy * phy)1367 static int qmp_ufs_exit(struct phy *phy)
1368 {
1369 	struct qmp_ufs *qmp = phy_get_drvdata(phy);
1370 
1371 	qmp_ufs_com_exit(qmp);
1372 
1373 	return 0;
1374 }
1375 
qmp_ufs_enable(struct phy * phy)1376 static int qmp_ufs_enable(struct phy *phy)
1377 {
1378 	int ret;
1379 
1380 	ret = qmp_ufs_init(phy);
1381 	if (ret)
1382 		return ret;
1383 
1384 	ret = qmp_ufs_power_on(phy);
1385 	if (ret)
1386 		qmp_ufs_exit(phy);
1387 
1388 	return ret;
1389 }
1390 
qmp_ufs_disable(struct phy * phy)1391 static int qmp_ufs_disable(struct phy *phy)
1392 {
1393 	int ret;
1394 
1395 	ret = qmp_ufs_power_off(phy);
1396 	if (ret)
1397 		return ret;
1398 	return qmp_ufs_exit(phy);
1399 }
1400 
qmp_ufs_set_mode(struct phy * phy,enum phy_mode mode,int submode)1401 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1402 {
1403 	struct qmp_ufs *qmp = phy_get_drvdata(phy);
1404 
1405 	qmp->mode = mode;
1406 	qmp->submode = submode;
1407 
1408 	return 0;
1409 }
1410 
1411 static const struct phy_ops qcom_qmp_ufs_phy_ops = {
1412 	.power_on	= qmp_ufs_enable,
1413 	.power_off	= qmp_ufs_disable,
1414 	.set_mode	= qmp_ufs_set_mode,
1415 	.owner		= THIS_MODULE,
1416 };
1417 
qmp_ufs_vreg_init(struct qmp_ufs * qmp)1418 static int qmp_ufs_vreg_init(struct qmp_ufs *qmp)
1419 {
1420 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1421 	struct device *dev = qmp->dev;
1422 	int num = cfg->num_vregs;
1423 	int i;
1424 
1425 	qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1426 	if (!qmp->vregs)
1427 		return -ENOMEM;
1428 
1429 	for (i = 0; i < num; i++)
1430 		qmp->vregs[i].supply = cfg->vreg_list[i];
1431 
1432 	return devm_regulator_bulk_get(dev, num, qmp->vregs);
1433 }
1434 
qmp_ufs_clk_init(struct qmp_ufs * qmp)1435 static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
1436 {
1437 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1438 	struct device *dev = qmp->dev;
1439 	int num = cfg->num_clks;
1440 	int i;
1441 
1442 	qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1443 	if (!qmp->clks)
1444 		return -ENOMEM;
1445 
1446 	for (i = 0; i < num; i++)
1447 		qmp->clks[i].id = cfg->clk_list[i];
1448 
1449 	return devm_clk_bulk_get(dev, num, qmp->clks);
1450 }
1451 
qmp_ufs_clk_release_provider(void * res)1452 static void qmp_ufs_clk_release_provider(void *res)
1453 {
1454 	of_clk_del_provider(res);
1455 }
1456 
1457 #define UFS_SYMBOL_CLOCKS 3
1458 
qmp_ufs_register_clocks(struct qmp_ufs * qmp,struct device_node * np)1459 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
1460 {
1461 	struct clk_hw_onecell_data *clk_data;
1462 	struct clk_hw *hw;
1463 	char name[64];
1464 	int ret;
1465 
1466 	clk_data = devm_kzalloc(qmp->dev,
1467 				struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
1468 				GFP_KERNEL);
1469 	if (!clk_data)
1470 		return -ENOMEM;
1471 
1472 	clk_data->num = UFS_SYMBOL_CLOCKS;
1473 
1474 	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
1475 	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1476 	if (IS_ERR(hw))
1477 		return PTR_ERR(hw);
1478 
1479 	clk_data->hws[0] = hw;
1480 
1481 	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
1482 	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1483 	if (IS_ERR(hw))
1484 		return PTR_ERR(hw);
1485 
1486 	clk_data->hws[1] = hw;
1487 
1488 	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
1489 	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1490 	if (IS_ERR(hw))
1491 		return PTR_ERR(hw);
1492 
1493 	clk_data->hws[2] = hw;
1494 
1495 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
1496 	if (ret)
1497 		return ret;
1498 
1499 	/*
1500 	 * Roll a devm action because the clock provider can be a child node.
1501 	 */
1502 	return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
1503 }
1504 
qmp_ufs_parse_dt_legacy(struct qmp_ufs * qmp,struct device_node * np)1505 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
1506 {
1507 	struct platform_device *pdev = to_platform_device(qmp->dev);
1508 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1509 	struct device *dev = qmp->dev;
1510 
1511 	qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
1512 	if (IS_ERR(qmp->serdes))
1513 		return PTR_ERR(qmp->serdes);
1514 
1515 	/*
1516 	 * Get memory resources for the PHY:
1517 	 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1518 	 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1519 	 * For single lane PHYs: pcs_misc (optional) -> 3.
1520 	 */
1521 	qmp->tx = devm_of_iomap(dev, np, 0, NULL);
1522 	if (IS_ERR(qmp->tx))
1523 		return PTR_ERR(qmp->tx);
1524 
1525 	qmp->rx = devm_of_iomap(dev, np, 1, NULL);
1526 	if (IS_ERR(qmp->rx))
1527 		return PTR_ERR(qmp->rx);
1528 
1529 	qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
1530 	if (IS_ERR(qmp->pcs))
1531 		return PTR_ERR(qmp->pcs);
1532 
1533 	if (cfg->lanes >= 2) {
1534 		qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
1535 		if (IS_ERR(qmp->tx2))
1536 			return PTR_ERR(qmp->tx2);
1537 
1538 		qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
1539 		if (IS_ERR(qmp->rx2))
1540 			return PTR_ERR(qmp->rx2);
1541 
1542 		qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
1543 	} else {
1544 		qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
1545 	}
1546 
1547 	if (IS_ERR(qmp->pcs_misc))
1548 		dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1549 
1550 	return 0;
1551 }
1552 
qmp_ufs_parse_dt(struct qmp_ufs * qmp)1553 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp)
1554 {
1555 	struct platform_device *pdev = to_platform_device(qmp->dev);
1556 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1557 	const struct qmp_ufs_offsets *offs = cfg->offsets;
1558 	void __iomem *base;
1559 
1560 	if (!offs)
1561 		return -EINVAL;
1562 
1563 	base = devm_platform_ioremap_resource(pdev, 0);
1564 	if (IS_ERR(base))
1565 		return PTR_ERR(base);
1566 
1567 	qmp->serdes = base + offs->serdes;
1568 	qmp->pcs = base + offs->pcs;
1569 	qmp->tx = base + offs->tx;
1570 	qmp->rx = base + offs->rx;
1571 
1572 	if (cfg->lanes >= 2) {
1573 		qmp->tx2 = base + offs->tx2;
1574 		qmp->rx2 = base + offs->rx2;
1575 	}
1576 
1577 	return 0;
1578 }
1579 
qmp_ufs_probe(struct platform_device * pdev)1580 static int qmp_ufs_probe(struct platform_device *pdev)
1581 {
1582 	struct device *dev = &pdev->dev;
1583 	struct phy_provider *phy_provider;
1584 	struct device_node *np;
1585 	struct qmp_ufs *qmp;
1586 	int ret;
1587 
1588 	qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1589 	if (!qmp)
1590 		return -ENOMEM;
1591 
1592 	qmp->dev = dev;
1593 
1594 	qmp->cfg = of_device_get_match_data(dev);
1595 	if (!qmp->cfg)
1596 		return -EINVAL;
1597 
1598 	ret = qmp_ufs_clk_init(qmp);
1599 	if (ret)
1600 		return ret;
1601 
1602 	ret = qmp_ufs_vreg_init(qmp);
1603 	if (ret)
1604 		return ret;
1605 
1606 	/* Check for legacy binding with child node. */
1607 	np = of_get_next_available_child(dev->of_node, NULL);
1608 	if (np) {
1609 		ret = qmp_ufs_parse_dt_legacy(qmp, np);
1610 	} else {
1611 		np = of_node_get(dev->of_node);
1612 		ret = qmp_ufs_parse_dt(qmp);
1613 	}
1614 	if (ret)
1615 		goto err_node_put;
1616 
1617 	ret = qmp_ufs_register_clocks(qmp, np);
1618 	if (ret)
1619 		goto err_node_put;
1620 
1621 	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
1622 	if (IS_ERR(qmp->phy)) {
1623 		ret = PTR_ERR(qmp->phy);
1624 		dev_err(dev, "failed to create PHY: %d\n", ret);
1625 		goto err_node_put;
1626 	}
1627 
1628 	phy_set_drvdata(qmp->phy, qmp);
1629 
1630 	of_node_put(np);
1631 
1632 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1633 
1634 	return PTR_ERR_OR_ZERO(phy_provider);
1635 
1636 err_node_put:
1637 	of_node_put(np);
1638 	return ret;
1639 }
1640 
1641 static const struct of_device_id qmp_ufs_of_match_table[] = {
1642 	{
1643 		.compatible = "qcom,msm8996-qmp-ufs-phy",
1644 		.data = &msm8996_ufsphy_cfg,
1645 	}, {
1646 		.compatible = "qcom,msm8998-qmp-ufs-phy",
1647 		.data = &sdm845_ufsphy_cfg,
1648 	}, {
1649 		.compatible = "qcom,sa8775p-qmp-ufs-phy",
1650 		.data = &sa8775p_ufsphy_cfg,
1651 	}, {
1652 		.compatible = "qcom,sc8180x-qmp-ufs-phy",
1653 		.data = &sm8150_ufsphy_cfg,
1654 	}, {
1655 		.compatible = "qcom,sc8280xp-qmp-ufs-phy",
1656 		.data = &sc8280xp_ufsphy_cfg,
1657 	}, {
1658 		.compatible = "qcom,sdm845-qmp-ufs-phy",
1659 		.data = &sdm845_ufsphy_cfg,
1660 	}, {
1661 		.compatible = "qcom,sm6115-qmp-ufs-phy",
1662 		.data = &sm6115_ufsphy_cfg,
1663 	}, {
1664 		.compatible = "qcom,sm6125-qmp-ufs-phy",
1665 		.data = &sm6115_ufsphy_cfg,
1666 	}, {
1667 		.compatible = "qcom,sm6350-qmp-ufs-phy",
1668 		.data = &sdm845_ufsphy_cfg,
1669 	}, {
1670 		.compatible = "qcom,sm7150-qmp-ufs-phy",
1671 		.data = &sm7150_ufsphy_cfg,
1672 	}, {
1673 		.compatible = "qcom,sm8150-qmp-ufs-phy",
1674 		.data = &sm8150_ufsphy_cfg,
1675 	}, {
1676 		.compatible = "qcom,sm8250-qmp-ufs-phy",
1677 		.data = &sm8250_ufsphy_cfg,
1678 	}, {
1679 		.compatible = "qcom,sm8350-qmp-ufs-phy",
1680 		.data = &sm8350_ufsphy_cfg,
1681 	}, {
1682 		.compatible = "qcom,sm8450-qmp-ufs-phy",
1683 		.data = &sm8450_ufsphy_cfg,
1684 	}, {
1685 		.compatible = "qcom,sm8550-qmp-ufs-phy",
1686 		.data = &sm8550_ufsphy_cfg,
1687 	},
1688 	{ },
1689 };
1690 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
1691 
1692 static struct platform_driver qmp_ufs_driver = {
1693 	.probe		= qmp_ufs_probe,
1694 	.driver = {
1695 		.name	= "qcom-qmp-ufs-phy",
1696 		.of_match_table = qmp_ufs_of_match_table,
1697 	},
1698 };
1699 
1700 module_platform_driver(qmp_ufs_driver);
1701 
1702 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1703 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver");
1704 MODULE_LICENSE("GPL v2");
1705