1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Texas Instruments DS90UB913 video serializer
4 *
5 * Based on a driver from Luca Ceresoli <luca@lucaceresoli.net>
6 *
7 * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net>
8 * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/fwnode.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/i2c-atr.h>
18 #include <linux/i2c.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23
24 #include <media/i2c/ds90ub9xx.h>
25 #include <media/v4l2-fwnode.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/v4l2-subdev.h>
28
29 #define UB913_PAD_SINK 0
30 #define UB913_PAD_SOURCE 1
31
32 /*
33 * UB913 has 4 gpios, but gpios 3 and 4 are reserved for external oscillator
34 * mode. Thus we only support 2 gpios for now.
35 */
36 #define UB913_NUM_GPIOS 2
37
38 #define UB913_REG_RESET_CTL 0x01
39 #define UB913_REG_RESET_CTL_DIGITAL_RESET_1 BIT(1)
40 #define UB913_REG_RESET_CTL_DIGITAL_RESET_0 BIT(0)
41
42 #define UB913_REG_GENERAL_CFG 0x03
43 #define UB913_REG_GENERAL_CFG_CRC_ERR_RESET BIT(5)
44 #define UB913_REG_GENERAL_CFG_PCLK_RISING BIT(0)
45
46 #define UB913_REG_MODE_SEL 0x05
47 #define UB913_REG_MODE_SEL_MODE_OVERRIDE BIT(5)
48 #define UB913_REG_MODE_SEL_MODE_UP_TO_DATE BIT(4)
49 #define UB913_REG_MODE_SEL_MODE_MASK GENMASK(3, 0)
50
51 #define UB913_REG_CRC_ERRORS_LSB 0x0a
52 #define UB913_REG_CRC_ERRORS_MSB 0x0b
53
54 #define UB913_REG_GENERAL_STATUS 0x0c
55
56 #define UB913_REG_GPIO_CFG(n) (0x0d + (n))
57 #define UB913_REG_GPIO_CFG_ENABLE(n) BIT(0 + (n) * 4)
58 #define UB913_REG_GPIO_CFG_DIR_INPUT(n) BIT(1 + (n) * 4)
59 #define UB913_REG_GPIO_CFG_REMOTE_EN(n) BIT(2 + (n) * 4)
60 #define UB913_REG_GPIO_CFG_OUT_VAL(n) BIT(3 + (n) * 4)
61 #define UB913_REG_GPIO_CFG_MASK(n) (0xf << ((n) * 4))
62
63 #define UB913_REG_SCL_HIGH_TIME 0x11
64 #define UB913_REG_SCL_LOW_TIME 0x12
65
66 #define UB913_REG_PLL_OVR 0x35
67
68 struct ub913_data {
69 struct i2c_client *client;
70 struct regmap *regmap;
71 struct clk *clkin;
72
73 struct gpio_chip gpio_chip;
74
75 struct v4l2_subdev sd;
76 struct media_pad pads[2];
77
78 struct v4l2_async_notifier notifier;
79
80 struct v4l2_subdev *source_sd;
81 u16 source_sd_pad;
82
83 u64 enabled_source_streams;
84
85 struct clk_hw *clkout_clk_hw;
86
87 struct ds90ub9xx_platform_data *plat_data;
88
89 bool pclk_polarity_rising;
90 };
91
sd_to_ub913(struct v4l2_subdev * sd)92 static inline struct ub913_data *sd_to_ub913(struct v4l2_subdev *sd)
93 {
94 return container_of(sd, struct ub913_data, sd);
95 }
96
97 struct ub913_format_info {
98 u32 incode;
99 u32 outcode;
100 };
101
102 static const struct ub913_format_info ub913_formats[] = {
103 /* Only RAW10 with 8-bit payload is supported at the moment */
104 { .incode = MEDIA_BUS_FMT_YUYV8_2X8, .outcode = MEDIA_BUS_FMT_YUYV8_1X16 },
105 { .incode = MEDIA_BUS_FMT_UYVY8_2X8, .outcode = MEDIA_BUS_FMT_UYVY8_1X16 },
106 { .incode = MEDIA_BUS_FMT_VYUY8_2X8, .outcode = MEDIA_BUS_FMT_VYUY8_1X16 },
107 { .incode = MEDIA_BUS_FMT_YVYU8_2X8, .outcode = MEDIA_BUS_FMT_YVYU8_1X16 },
108 };
109
ub913_find_format(u32 incode)110 static const struct ub913_format_info *ub913_find_format(u32 incode)
111 {
112 unsigned int i;
113
114 for (i = 0; i < ARRAY_SIZE(ub913_formats); i++) {
115 if (ub913_formats[i].incode == incode)
116 return &ub913_formats[i];
117 }
118
119 return NULL;
120 }
121
ub913_read(const struct ub913_data * priv,u8 reg,u8 * val)122 static int ub913_read(const struct ub913_data *priv, u8 reg, u8 *val)
123 {
124 unsigned int v;
125 int ret;
126
127 ret = regmap_read(priv->regmap, reg, &v);
128 if (ret < 0) {
129 dev_err(&priv->client->dev,
130 "Cannot read register 0x%02x: %d!\n", reg, ret);
131 return ret;
132 }
133
134 *val = v;
135 return 0;
136 }
137
ub913_write(const struct ub913_data * priv,u8 reg,u8 val)138 static int ub913_write(const struct ub913_data *priv, u8 reg, u8 val)
139 {
140 int ret;
141
142 ret = regmap_write(priv->regmap, reg, val);
143 if (ret < 0)
144 dev_err(&priv->client->dev,
145 "Cannot write register 0x%02x: %d!\n", reg, ret);
146
147 return ret;
148 }
149
ub913_update_bits(const struct ub913_data * priv,u8 reg,u8 mask,u8 val)150 static int ub913_update_bits(const struct ub913_data *priv, u8 reg, u8 mask,
151 u8 val)
152 {
153 int ret;
154
155 ret = regmap_update_bits(priv->regmap, reg, mask, val);
156 if (ret < 0)
157 dev_err(&priv->client->dev,
158 "Cannot update register 0x%02x %d!\n", reg, ret);
159
160 return ret;
161 }
162
163 /*
164 * GPIO chip
165 */
ub913_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)166 static int ub913_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
167 {
168 return GPIO_LINE_DIRECTION_OUT;
169 }
170
ub913_gpio_direction_out(struct gpio_chip * gc,unsigned int offset,int value)171 static int ub913_gpio_direction_out(struct gpio_chip *gc, unsigned int offset,
172 int value)
173 {
174 struct ub913_data *priv = gpiochip_get_data(gc);
175 unsigned int reg_idx = offset / 2;
176 unsigned int field_idx = offset % 2;
177
178 return regmap_update_bits(priv->regmap, UB913_REG_GPIO_CFG(reg_idx),
179 UB913_REG_GPIO_CFG_MASK(field_idx),
180 UB913_REG_GPIO_CFG_ENABLE(field_idx) |
181 (value ? UB913_REG_GPIO_CFG_OUT_VAL(field_idx) :
182 0));
183 }
184
ub913_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)185 static void ub913_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
186 {
187 ub913_gpio_direction_out(gc, offset, value);
188 }
189
ub913_gpio_of_xlate(struct gpio_chip * gc,const struct of_phandle_args * gpiospec,u32 * flags)190 static int ub913_gpio_of_xlate(struct gpio_chip *gc,
191 const struct of_phandle_args *gpiospec,
192 u32 *flags)
193 {
194 if (flags)
195 *flags = gpiospec->args[1];
196
197 return gpiospec->args[0];
198 }
199
ub913_gpiochip_probe(struct ub913_data * priv)200 static int ub913_gpiochip_probe(struct ub913_data *priv)
201 {
202 struct device *dev = &priv->client->dev;
203 struct gpio_chip *gc = &priv->gpio_chip;
204 int ret;
205
206 /* Initialize GPIOs 0 and 1 to local control, tri-state */
207 ub913_write(priv, UB913_REG_GPIO_CFG(0), 0);
208
209 gc->label = dev_name(dev);
210 gc->parent = dev;
211 gc->owner = THIS_MODULE;
212 gc->base = -1;
213 gc->can_sleep = true;
214 gc->ngpio = UB913_NUM_GPIOS;
215 gc->get_direction = ub913_gpio_get_direction;
216 gc->direction_output = ub913_gpio_direction_out;
217 gc->set = ub913_gpio_set;
218 gc->of_xlate = ub913_gpio_of_xlate;
219 gc->of_gpio_n_cells = 2;
220
221 ret = gpiochip_add_data(gc, priv);
222 if (ret) {
223 dev_err(dev, "Failed to add GPIOs: %d\n", ret);
224 return ret;
225 }
226
227 return 0;
228 }
229
ub913_gpiochip_remove(struct ub913_data * priv)230 static void ub913_gpiochip_remove(struct ub913_data *priv)
231 {
232 gpiochip_remove(&priv->gpio_chip);
233 }
234
235 static const struct regmap_config ub913_regmap_config = {
236 .name = "ds90ub913",
237 .reg_bits = 8,
238 .val_bits = 8,
239 .reg_format_endian = REGMAP_ENDIAN_DEFAULT,
240 .val_format_endian = REGMAP_ENDIAN_DEFAULT,
241 };
242
243 /*
244 * V4L2
245 */
246
ub913_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)247 static int ub913_enable_streams(struct v4l2_subdev *sd,
248 struct v4l2_subdev_state *state, u32 pad,
249 u64 streams_mask)
250 {
251 struct ub913_data *priv = sd_to_ub913(sd);
252 u64 sink_streams;
253 int ret;
254
255 sink_streams = v4l2_subdev_state_xlate_streams(state, UB913_PAD_SOURCE,
256 UB913_PAD_SINK,
257 &streams_mask);
258
259 ret = v4l2_subdev_enable_streams(priv->source_sd, priv->source_sd_pad,
260 sink_streams);
261 if (ret)
262 return ret;
263
264 priv->enabled_source_streams |= streams_mask;
265
266 return 0;
267 }
268
ub913_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)269 static int ub913_disable_streams(struct v4l2_subdev *sd,
270 struct v4l2_subdev_state *state, u32 pad,
271 u64 streams_mask)
272 {
273 struct ub913_data *priv = sd_to_ub913(sd);
274 u64 sink_streams;
275 int ret;
276
277 sink_streams = v4l2_subdev_state_xlate_streams(state, UB913_PAD_SOURCE,
278 UB913_PAD_SINK,
279 &streams_mask);
280
281 ret = v4l2_subdev_disable_streams(priv->source_sd, priv->source_sd_pad,
282 sink_streams);
283 if (ret)
284 return ret;
285
286 priv->enabled_source_streams &= ~streams_mask;
287
288 return 0;
289 }
290
_ub913_set_routing(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_krouting * routing)291 static int _ub913_set_routing(struct v4l2_subdev *sd,
292 struct v4l2_subdev_state *state,
293 struct v4l2_subdev_krouting *routing)
294 {
295 static const struct v4l2_mbus_framefmt in_format = {
296 .width = 640,
297 .height = 480,
298 .code = MEDIA_BUS_FMT_UYVY8_2X8,
299 .field = V4L2_FIELD_NONE,
300 .colorspace = V4L2_COLORSPACE_SRGB,
301 .ycbcr_enc = V4L2_YCBCR_ENC_601,
302 .quantization = V4L2_QUANTIZATION_LIM_RANGE,
303 .xfer_func = V4L2_XFER_FUNC_SRGB,
304 };
305 static const struct v4l2_mbus_framefmt out_format = {
306 .width = 640,
307 .height = 480,
308 .code = MEDIA_BUS_FMT_UYVY8_1X16,
309 .field = V4L2_FIELD_NONE,
310 .colorspace = V4L2_COLORSPACE_SRGB,
311 .ycbcr_enc = V4L2_YCBCR_ENC_601,
312 .quantization = V4L2_QUANTIZATION_LIM_RANGE,
313 .xfer_func = V4L2_XFER_FUNC_SRGB,
314 };
315 struct v4l2_subdev_stream_configs *stream_configs;
316 unsigned int i;
317 int ret;
318
319 /*
320 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
321 * frame desc is made dynamically allocated.
322 */
323
324 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
325 return -EINVAL;
326
327 ret = v4l2_subdev_routing_validate(sd, routing,
328 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);
329 if (ret)
330 return ret;
331
332 ret = v4l2_subdev_set_routing(sd, state, routing);
333 if (ret)
334 return ret;
335
336 stream_configs = &state->stream_configs;
337
338 for (i = 0; i < stream_configs->num_configs; i++) {
339 if (stream_configs->configs[i].pad == UB913_PAD_SINK)
340 stream_configs->configs[i].fmt = in_format;
341 else
342 stream_configs->configs[i].fmt = out_format;
343 }
344
345 return 0;
346 }
347
ub913_set_routing(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,enum v4l2_subdev_format_whence which,struct v4l2_subdev_krouting * routing)348 static int ub913_set_routing(struct v4l2_subdev *sd,
349 struct v4l2_subdev_state *state,
350 enum v4l2_subdev_format_whence which,
351 struct v4l2_subdev_krouting *routing)
352 {
353 struct ub913_data *priv = sd_to_ub913(sd);
354
355 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams)
356 return -EBUSY;
357
358 return _ub913_set_routing(sd, state, routing);
359 }
360
ub913_get_frame_desc(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_frame_desc * fd)361 static int ub913_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
362 struct v4l2_mbus_frame_desc *fd)
363 {
364 struct ub913_data *priv = sd_to_ub913(sd);
365 const struct v4l2_subdev_krouting *routing;
366 struct v4l2_mbus_frame_desc source_fd;
367 struct v4l2_subdev_route *route;
368 struct v4l2_subdev_state *state;
369 int ret;
370
371 if (pad != UB913_PAD_SOURCE)
372 return -EINVAL;
373
374 ret = v4l2_subdev_call(priv->source_sd, pad, get_frame_desc,
375 priv->source_sd_pad, &source_fd);
376 if (ret)
377 return ret;
378
379 memset(fd, 0, sizeof(*fd));
380
381 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL;
382
383 state = v4l2_subdev_lock_and_get_active_state(sd);
384
385 routing = &state->routing;
386
387 for_each_active_route(routing, route) {
388 unsigned int i;
389
390 if (route->source_pad != pad)
391 continue;
392
393 for (i = 0; i < source_fd.num_entries; i++) {
394 if (source_fd.entry[i].stream == route->sink_stream)
395 break;
396 }
397
398 if (i == source_fd.num_entries) {
399 dev_err(&priv->client->dev,
400 "Failed to find stream from source frame desc\n");
401 ret = -EPIPE;
402 goto out_unlock;
403 }
404
405 fd->entry[fd->num_entries].stream = route->source_stream;
406 fd->entry[fd->num_entries].flags = source_fd.entry[i].flags;
407 fd->entry[fd->num_entries].length = source_fd.entry[i].length;
408 fd->entry[fd->num_entries].pixelcode =
409 source_fd.entry[i].pixelcode;
410
411 fd->num_entries++;
412 }
413
414 out_unlock:
415 v4l2_subdev_unlock_state(state);
416
417 return ret;
418 }
419
ub913_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * format)420 static int ub913_set_fmt(struct v4l2_subdev *sd,
421 struct v4l2_subdev_state *state,
422 struct v4l2_subdev_format *format)
423 {
424 struct ub913_data *priv = sd_to_ub913(sd);
425 struct v4l2_mbus_framefmt *fmt;
426 const struct ub913_format_info *finfo;
427
428 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
429 priv->enabled_source_streams)
430 return -EBUSY;
431
432 /* Source format is fully defined by the sink format, so not settable */
433 if (format->pad == UB913_PAD_SOURCE)
434 return v4l2_subdev_get_fmt(sd, state, format);
435
436 finfo = ub913_find_format(format->format.code);
437 if (!finfo) {
438 finfo = &ub913_formats[0];
439 format->format.code = finfo->incode;
440 }
441
442 /* Set sink format */
443 fmt = v4l2_subdev_state_get_stream_format(state, format->pad,
444 format->stream);
445 if (!fmt)
446 return -EINVAL;
447
448 *fmt = format->format;
449
450 /* Propagate to source format, and adjust the mbus code */
451 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
452 format->stream);
453 if (!fmt)
454 return -EINVAL;
455
456 format->format.code = finfo->outcode;
457
458 *fmt = format->format;
459
460 return 0;
461 }
462
ub913_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)463 static int ub913_init_cfg(struct v4l2_subdev *sd,
464 struct v4l2_subdev_state *state)
465 {
466 struct v4l2_subdev_route routes[] = {
467 {
468 .sink_pad = UB913_PAD_SINK,
469 .sink_stream = 0,
470 .source_pad = UB913_PAD_SOURCE,
471 .source_stream = 0,
472 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
473 },
474 };
475
476 struct v4l2_subdev_krouting routing = {
477 .num_routes = ARRAY_SIZE(routes),
478 .routes = routes,
479 };
480
481 return _ub913_set_routing(sd, state, &routing);
482 }
483
ub913_log_status(struct v4l2_subdev * sd)484 static int ub913_log_status(struct v4l2_subdev *sd)
485 {
486 struct ub913_data *priv = sd_to_ub913(sd);
487 struct device *dev = &priv->client->dev;
488 u8 v = 0, v1 = 0, v2 = 0;
489
490 ub913_read(priv, UB913_REG_MODE_SEL, &v);
491 dev_info(dev, "MODE_SEL %#02x\n", v);
492
493 ub913_read(priv, UB913_REG_CRC_ERRORS_LSB, &v1);
494 ub913_read(priv, UB913_REG_CRC_ERRORS_MSB, &v2);
495 dev_info(dev, "CRC errors %u\n", v1 | (v2 << 8));
496
497 /* clear CRC errors */
498 ub913_read(priv, UB913_REG_GENERAL_CFG, &v);
499 ub913_write(priv, UB913_REG_GENERAL_CFG,
500 v | UB913_REG_GENERAL_CFG_CRC_ERR_RESET);
501 ub913_write(priv, UB913_REG_GENERAL_CFG, v);
502
503 ub913_read(priv, UB913_REG_GENERAL_STATUS, &v);
504 dev_info(dev, "GENERAL_STATUS %#02x\n", v);
505
506 ub913_read(priv, UB913_REG_PLL_OVR, &v);
507 dev_info(dev, "PLL_OVR %#02x\n", v);
508
509 return 0;
510 }
511
512 static const struct v4l2_subdev_core_ops ub913_subdev_core_ops = {
513 .log_status = ub913_log_status,
514 };
515
516 static const struct v4l2_subdev_pad_ops ub913_pad_ops = {
517 .enable_streams = ub913_enable_streams,
518 .disable_streams = ub913_disable_streams,
519 .set_routing = ub913_set_routing,
520 .get_frame_desc = ub913_get_frame_desc,
521 .get_fmt = v4l2_subdev_get_fmt,
522 .set_fmt = ub913_set_fmt,
523 .init_cfg = ub913_init_cfg,
524 };
525
526 static const struct v4l2_subdev_ops ub913_subdev_ops = {
527 .core = &ub913_subdev_core_ops,
528 .pad = &ub913_pad_ops,
529 };
530
531 static const struct media_entity_operations ub913_entity_ops = {
532 .link_validate = v4l2_subdev_link_validate,
533 };
534
ub913_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * source_subdev,struct v4l2_async_connection * asd)535 static int ub913_notify_bound(struct v4l2_async_notifier *notifier,
536 struct v4l2_subdev *source_subdev,
537 struct v4l2_async_connection *asd)
538 {
539 struct ub913_data *priv = sd_to_ub913(notifier->sd);
540 struct device *dev = &priv->client->dev;
541 int ret;
542
543 ret = media_entity_get_fwnode_pad(&source_subdev->entity,
544 source_subdev->fwnode,
545 MEDIA_PAD_FL_SOURCE);
546 if (ret < 0) {
547 dev_err(dev, "Failed to find pad for %s\n",
548 source_subdev->name);
549 return ret;
550 }
551
552 priv->source_sd = source_subdev;
553 priv->source_sd_pad = ret;
554
555 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad,
556 &priv->sd.entity, UB913_PAD_SINK,
557 MEDIA_LNK_FL_ENABLED |
558 MEDIA_LNK_FL_IMMUTABLE);
559 if (ret) {
560 dev_err(dev, "Unable to link %s:%u -> %s:0\n",
561 source_subdev->name, priv->source_sd_pad,
562 priv->sd.name);
563 return ret;
564 }
565
566 return 0;
567 }
568
569 static const struct v4l2_async_notifier_operations ub913_notify_ops = {
570 .bound = ub913_notify_bound,
571 };
572
ub913_v4l2_notifier_register(struct ub913_data * priv)573 static int ub913_v4l2_notifier_register(struct ub913_data *priv)
574 {
575 struct device *dev = &priv->client->dev;
576 struct v4l2_async_connection *asd;
577 struct fwnode_handle *ep_fwnode;
578 int ret;
579
580 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
581 UB913_PAD_SINK, 0, 0);
582 if (!ep_fwnode) {
583 dev_err(dev, "No graph endpoint\n");
584 return -ENODEV;
585 }
586
587 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
588
589 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode,
590 struct v4l2_async_connection);
591
592 fwnode_handle_put(ep_fwnode);
593
594 if (IS_ERR(asd)) {
595 dev_err(dev, "Failed to add subdev: %ld", PTR_ERR(asd));
596 v4l2_async_nf_cleanup(&priv->notifier);
597 return PTR_ERR(asd);
598 }
599
600 priv->notifier.ops = &ub913_notify_ops;
601
602 ret = v4l2_async_nf_register(&priv->notifier);
603 if (ret) {
604 dev_err(dev, "Failed to register subdev_notifier");
605 v4l2_async_nf_cleanup(&priv->notifier);
606 return ret;
607 }
608
609 return 0;
610 }
611
ub913_v4l2_nf_unregister(struct ub913_data * priv)612 static void ub913_v4l2_nf_unregister(struct ub913_data *priv)
613 {
614 v4l2_async_nf_unregister(&priv->notifier);
615 v4l2_async_nf_cleanup(&priv->notifier);
616 }
617
ub913_register_clkout(struct ub913_data * priv)618 static int ub913_register_clkout(struct ub913_data *priv)
619 {
620 struct device *dev = &priv->client->dev;
621 const char *name;
622 int ret;
623
624 name = kasprintf(GFP_KERNEL, "ds90ub913.%s.clk_out", dev_name(dev));
625 if (!name)
626 return -ENOMEM;
627
628 priv->clkout_clk_hw = devm_clk_hw_register_fixed_factor(dev, name,
629 __clk_get_name(priv->clkin), 0, 1, 2);
630
631 kfree(name);
632
633 if (IS_ERR(priv->clkout_clk_hw))
634 return dev_err_probe(dev, PTR_ERR(priv->clkout_clk_hw),
635 "Cannot register clkout hw\n");
636
637 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
638 priv->clkout_clk_hw);
639 if (ret)
640 return dev_err_probe(dev, ret,
641 "Cannot add OF clock provider\n");
642
643 return 0;
644 }
645
ub913_i2c_master_init(struct ub913_data * priv)646 static int ub913_i2c_master_init(struct ub913_data *priv)
647 {
648 /* i2c fast mode */
649 u32 scl_high = 600 + 300; /* high period + rise time, ns */
650 u32 scl_low = 1300 + 300; /* low period + fall time, ns */
651 unsigned long ref;
652 int ret;
653
654 ref = clk_get_rate(priv->clkin) / 2;
655
656 scl_high = div64_u64((u64)scl_high * ref, 1000000000);
657 scl_low = div64_u64((u64)scl_low * ref, 1000000000);
658
659 ret = ub913_write(priv, UB913_REG_SCL_HIGH_TIME, scl_high);
660 if (ret)
661 return ret;
662
663 ret = ub913_write(priv, UB913_REG_SCL_LOW_TIME, scl_low);
664 if (ret)
665 return ret;
666
667 return 0;
668 }
669
ub913_add_i2c_adapter(struct ub913_data * priv)670 static int ub913_add_i2c_adapter(struct ub913_data *priv)
671 {
672 struct device *dev = &priv->client->dev;
673 struct fwnode_handle *i2c_handle;
674 int ret;
675
676 i2c_handle = device_get_named_child_node(dev, "i2c");
677 if (!i2c_handle)
678 return 0;
679
680 ret = i2c_atr_add_adapter(priv->plat_data->atr, priv->plat_data->port,
681 dev, i2c_handle);
682
683 fwnode_handle_put(i2c_handle);
684
685 if (ret)
686 return ret;
687
688 return 0;
689 }
690
ub913_parse_dt(struct ub913_data * priv)691 static int ub913_parse_dt(struct ub913_data *priv)
692 {
693 struct device *dev = &priv->client->dev;
694 struct v4l2_fwnode_endpoint vep = {
695 .bus_type = V4L2_MBUS_PARALLEL,
696 };
697 struct fwnode_handle *ep_fwnode;
698 int ret;
699
700 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
701 UB913_PAD_SINK, 0, 0);
702 if (!ep_fwnode)
703 return dev_err_probe(dev, -ENOENT, "No sink endpoint\n");
704
705 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);
706
707 fwnode_handle_put(ep_fwnode);
708
709 if (ret)
710 return dev_err_probe(dev, ret,
711 "failed to parse sink endpoint data\n");
712
713 if (vep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
714 priv->pclk_polarity_rising = true;
715 else if (vep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
716 priv->pclk_polarity_rising = false;
717 else
718 return dev_err_probe(dev, -EINVAL,
719 "bad value for 'pclk-sample'\n");
720
721 return 0;
722 }
723
ub913_hw_init(struct ub913_data * priv)724 static int ub913_hw_init(struct ub913_data *priv)
725 {
726 struct device *dev = &priv->client->dev;
727 bool mode_override;
728 u8 mode;
729 int ret;
730 u8 v;
731
732 ret = ub913_read(priv, UB913_REG_MODE_SEL, &v);
733 if (ret)
734 return ret;
735
736 if (!(v & UB913_REG_MODE_SEL_MODE_UP_TO_DATE))
737 return dev_err_probe(dev, -ENODEV,
738 "Mode value not stabilized\n");
739
740 mode_override = v & UB913_REG_MODE_SEL_MODE_OVERRIDE;
741 mode = v & UB913_REG_MODE_SEL_MODE_MASK;
742
743 dev_dbg(dev, "mode from %s: %#x\n",
744 mode_override ? "reg" : "deserializer", mode);
745
746 ret = ub913_i2c_master_init(priv);
747 if (ret)
748 return dev_err_probe(dev, ret, "i2c master init failed\n");
749
750 ret = ub913_update_bits(priv, UB913_REG_GENERAL_CFG,
751 UB913_REG_GENERAL_CFG_PCLK_RISING,
752 FIELD_PREP(UB913_REG_GENERAL_CFG_PCLK_RISING,
753 priv->pclk_polarity_rising));
754
755 if (ret)
756 return ret;
757
758 return 0;
759 }
760
ub913_subdev_init(struct ub913_data * priv)761 static int ub913_subdev_init(struct ub913_data *priv)
762 {
763 struct device *dev = &priv->client->dev;
764 int ret;
765
766 v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub913_subdev_ops);
767 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;
768 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
769 priv->sd.entity.ops = &ub913_entity_ops;
770
771 priv->pads[0].flags = MEDIA_PAD_FL_SINK;
772 priv->pads[1].flags = MEDIA_PAD_FL_SOURCE;
773
774 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads);
775 if (ret)
776 return dev_err_probe(dev, ret, "Failed to init pads\n");
777
778 ret = v4l2_subdev_init_finalize(&priv->sd);
779 if (ret)
780 goto err_entity_cleanup;
781
782 ret = ub913_v4l2_notifier_register(priv);
783 if (ret) {
784 dev_err_probe(dev, ret,
785 "v4l2 subdev notifier register failed\n");
786 goto err_subdev_cleanup;
787 }
788
789 ret = v4l2_async_register_subdev(&priv->sd);
790 if (ret) {
791 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n");
792 goto err_unreg_notif;
793 }
794
795 return 0;
796
797 err_unreg_notif:
798 ub913_v4l2_nf_unregister(priv);
799 err_subdev_cleanup:
800 v4l2_subdev_cleanup(&priv->sd);
801 err_entity_cleanup:
802 media_entity_cleanup(&priv->sd.entity);
803
804 return ret;
805 }
806
ub913_subdev_uninit(struct ub913_data * priv)807 static void ub913_subdev_uninit(struct ub913_data *priv)
808 {
809 v4l2_async_unregister_subdev(&priv->sd);
810 ub913_v4l2_nf_unregister(priv);
811 v4l2_subdev_cleanup(&priv->sd);
812 media_entity_cleanup(&priv->sd.entity);
813 }
814
ub913_probe(struct i2c_client * client)815 static int ub913_probe(struct i2c_client *client)
816 {
817 struct device *dev = &client->dev;
818 struct ub913_data *priv;
819 int ret;
820
821 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
822 if (!priv)
823 return -ENOMEM;
824
825 priv->client = client;
826
827 priv->plat_data = dev_get_platdata(&client->dev);
828 if (!priv->plat_data)
829 return dev_err_probe(dev, -ENODEV, "Platform data missing\n");
830
831 priv->regmap = devm_regmap_init_i2c(client, &ub913_regmap_config);
832 if (IS_ERR(priv->regmap))
833 return dev_err_probe(dev, PTR_ERR(priv->regmap),
834 "Failed to init regmap\n");
835
836 /*
837 * ub913 can also work without ext clock, but that is not supported by
838 * the driver yet.
839 */
840 priv->clkin = devm_clk_get(dev, "clkin");
841 if (IS_ERR(priv->clkin))
842 return dev_err_probe(dev, PTR_ERR(priv->clkin),
843 "Cannot get CLKIN\n");
844
845 ret = ub913_parse_dt(priv);
846 if (ret)
847 return ret;
848
849 ret = ub913_hw_init(priv);
850 if (ret)
851 return ret;
852
853 ret = ub913_gpiochip_probe(priv);
854 if (ret)
855 return dev_err_probe(dev, ret, "Failed to init gpiochip\n");
856
857 ret = ub913_register_clkout(priv);
858 if (ret) {
859 dev_err_probe(dev, ret, "Failed to register clkout\n");
860 goto err_gpiochip_remove;
861 }
862
863 ret = ub913_subdev_init(priv);
864 if (ret)
865 goto err_gpiochip_remove;
866
867 ret = ub913_add_i2c_adapter(priv);
868 if (ret) {
869 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n");
870 goto err_subdev_uninit;
871 }
872
873 return 0;
874
875 err_subdev_uninit:
876 ub913_subdev_uninit(priv);
877 err_gpiochip_remove:
878 ub913_gpiochip_remove(priv);
879
880 return ret;
881 }
882
ub913_remove(struct i2c_client * client)883 static void ub913_remove(struct i2c_client *client)
884 {
885 struct v4l2_subdev *sd = i2c_get_clientdata(client);
886 struct ub913_data *priv = sd_to_ub913(sd);
887
888 i2c_atr_del_adapter(priv->plat_data->atr, priv->plat_data->port);
889
890 ub913_subdev_uninit(priv);
891
892 ub913_gpiochip_remove(priv);
893 }
894
895 static const struct i2c_device_id ub913_id[] = { { "ds90ub913a-q1", 0 }, {} };
896 MODULE_DEVICE_TABLE(i2c, ub913_id);
897
898 static const struct of_device_id ub913_dt_ids[] = {
899 { .compatible = "ti,ds90ub913a-q1" },
900 {}
901 };
902 MODULE_DEVICE_TABLE(of, ub913_dt_ids);
903
904 static struct i2c_driver ds90ub913_driver = {
905 .probe = ub913_probe,
906 .remove = ub913_remove,
907 .id_table = ub913_id,
908 .driver = {
909 .name = "ds90ub913a",
910 .of_match_table = ub913_dt_ids,
911 },
912 };
913 module_i2c_driver(ds90ub913_driver);
914
915 MODULE_LICENSE("GPL");
916 MODULE_DESCRIPTION("Texas Instruments DS90UB913 FPD-Link III Serializer Driver");
917 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
918 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>");
919 MODULE_IMPORT_NS(I2C_ATR);
920