1 /*
2 * Allwinner R40/A40i/T3 System on Chip emulation
3 *
4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qemu/units.h"
25 #include "hw/boards.h"
26 #include "hw/qdev-core.h"
27 #include "hw/sysbus.h"
28 #include "hw/char/serial-mm.h"
29 #include "hw/misc/unimp.h"
30 #include "hw/usb/hcd-ehci.h"
31 #include "hw/loader.h"
32 #include "system/system.h"
33 #include "hw/arm/allwinner-r40.h"
34 #include "hw/misc/allwinner-r40-dramc.h"
35 #include "target/arm/cpu-qom.h"
36 #include "target/arm/gtimer.h"
37
38 /* Memory map */
39 const hwaddr allwinner_r40_memmap[] = {
40 [AW_R40_DEV_SRAM_A1] = 0x00000000,
41 [AW_R40_DEV_SRAM_A2] = 0x00004000,
42 [AW_R40_DEV_SRAM_A3] = 0x00008000,
43 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
44 [AW_R40_DEV_SRAMC] = 0x01c00000,
45 [AW_R40_DEV_EMAC] = 0x01c0b000,
46 [AW_R40_DEV_MMC0] = 0x01c0f000,
47 [AW_R40_DEV_MMC1] = 0x01c10000,
48 [AW_R40_DEV_MMC2] = 0x01c11000,
49 [AW_R40_DEV_MMC3] = 0x01c12000,
50 [AW_R40_DEV_AHCI] = 0x01c18000,
51 [AW_R40_DEV_EHCI1] = 0x01c19000,
52 [AW_R40_DEV_OHCI1] = 0x01c19400,
53 [AW_R40_DEV_EHCI2] = 0x01c1c000,
54 [AW_R40_DEV_OHCI2] = 0x01c1c400,
55 [AW_R40_DEV_CCU] = 0x01c20000,
56 [AW_R40_DEV_PIT] = 0x01c20c00,
57 [AW_R40_DEV_WDT] = 0x01c20c90,
58 [AW_R40_DEV_UART0] = 0x01c28000,
59 [AW_R40_DEV_UART1] = 0x01c28400,
60 [AW_R40_DEV_UART2] = 0x01c28800,
61 [AW_R40_DEV_UART3] = 0x01c28c00,
62 [AW_R40_DEV_UART4] = 0x01c29000,
63 [AW_R40_DEV_UART5] = 0x01c29400,
64 [AW_R40_DEV_UART6] = 0x01c29800,
65 [AW_R40_DEV_UART7] = 0x01c29c00,
66 [AW_R40_DEV_TWI0] = 0x01c2ac00,
67 [AW_R40_DEV_GMAC] = 0x01c50000,
68 [AW_R40_DEV_DRAMCOM] = 0x01c62000,
69 [AW_R40_DEV_DRAMCTL] = 0x01c63000,
70 [AW_R40_DEV_DRAMPHY] = 0x01c65000,
71 [AW_R40_DEV_GIC_DIST] = 0x01c81000,
72 [AW_R40_DEV_GIC_CPU] = 0x01c82000,
73 [AW_R40_DEV_GIC_HYP] = 0x01c84000,
74 [AW_R40_DEV_GIC_VCPU] = 0x01c86000,
75 [AW_R40_DEV_SDRAM] = 0x40000000
76 };
77
78 /* List of unimplemented devices */
79 struct AwR40Unimplemented {
80 const char *device_name;
81 hwaddr base;
82 hwaddr size;
83 };
84
85 static struct AwR40Unimplemented r40_unimplemented[] = {
86 { "d-engine", 0x01000000, 4 * MiB },
87 { "d-inter", 0x01400000, 128 * KiB },
88 { "dma", 0x01c02000, 4 * KiB },
89 { "nfdc", 0x01c03000, 4 * KiB },
90 { "ts", 0x01c04000, 4 * KiB },
91 { "spi0", 0x01c05000, 4 * KiB },
92 { "spi1", 0x01c06000, 4 * KiB },
93 { "cs0", 0x01c09000, 4 * KiB },
94 { "keymem", 0x01c0a000, 4 * KiB },
95 { "usb0-otg", 0x01c13000, 4 * KiB },
96 { "usb0-host", 0x01c14000, 4 * KiB },
97 { "crypto", 0x01c15000, 4 * KiB },
98 { "spi2", 0x01c17000, 4 * KiB },
99 { "usb1-phy", 0x01c19800, 2 * KiB },
100 { "sid", 0x01c1b000, 4 * KiB },
101 { "usb2-phy", 0x01c1c800, 2 * KiB },
102 { "cs1", 0x01c1d000, 4 * KiB },
103 { "spi3", 0x01c1f000, 4 * KiB },
104 { "rtc", 0x01c20400, 1 * KiB },
105 { "pio", 0x01c20800, 1 * KiB },
106 { "owa", 0x01c21000, 1 * KiB },
107 { "ac97", 0x01c21400, 1 * KiB },
108 { "cir0", 0x01c21800, 1 * KiB },
109 { "cir1", 0x01c21c00, 1 * KiB },
110 { "pcm0", 0x01c22000, 1 * KiB },
111 { "pcm1", 0x01c22400, 1 * KiB },
112 { "pcm2", 0x01c22800, 1 * KiB },
113 { "audio", 0x01c22c00, 1 * KiB },
114 { "keypad", 0x01c23000, 1 * KiB },
115 { "pwm", 0x01c23400, 1 * KiB },
116 { "keyadc", 0x01c24400, 1 * KiB },
117 { "ths", 0x01c24c00, 1 * KiB },
118 { "rtp", 0x01c25000, 1 * KiB },
119 { "pmu", 0x01c25400, 1 * KiB },
120 { "cpu-cfg", 0x01c25c00, 1 * KiB },
121 { "uart0", 0x01c28000, 1 * KiB },
122 { "uart1", 0x01c28400, 1 * KiB },
123 { "uart2", 0x01c28800, 1 * KiB },
124 { "uart3", 0x01c28c00, 1 * KiB },
125 { "uart4", 0x01c29000, 1 * KiB },
126 { "uart5", 0x01c29400, 1 * KiB },
127 { "uart6", 0x01c29800, 1 * KiB },
128 { "uart7", 0x01c29c00, 1 * KiB },
129 { "ps20", 0x01c2a000, 1 * KiB },
130 { "ps21", 0x01c2a400, 1 * KiB },
131 { "twi1", 0x01c2b000, 1 * KiB },
132 { "twi2", 0x01c2b400, 1 * KiB },
133 { "twi3", 0x01c2b800, 1 * KiB },
134 { "twi4", 0x01c2c000, 1 * KiB },
135 { "scr", 0x01c2c400, 1 * KiB },
136 { "tvd-top", 0x01c30000, 4 * KiB },
137 { "tvd0", 0x01c31000, 4 * KiB },
138 { "tvd1", 0x01c32000, 4 * KiB },
139 { "tvd2", 0x01c33000, 4 * KiB },
140 { "tvd3", 0x01c34000, 4 * KiB },
141 { "gpu", 0x01c40000, 64 * KiB },
142 { "hstmr", 0x01c60000, 4 * KiB },
143 { "tcon-top", 0x01c70000, 4 * KiB },
144 { "lcd0", 0x01c71000, 4 * KiB },
145 { "lcd1", 0x01c72000, 4 * KiB },
146 { "tv0", 0x01c73000, 4 * KiB },
147 { "tv1", 0x01c74000, 4 * KiB },
148 { "tve-top", 0x01c90000, 16 * KiB },
149 { "tve0", 0x01c94000, 16 * KiB },
150 { "tve1", 0x01c98000, 16 * KiB },
151 { "mipi_dsi", 0x01ca0000, 4 * KiB },
152 { "mipi_dphy", 0x01ca1000, 4 * KiB },
153 { "ve", 0x01d00000, 1024 * KiB },
154 { "mp", 0x01e80000, 128 * KiB },
155 { "hdmi", 0x01ee0000, 128 * KiB },
156 { "prcm", 0x01f01400, 1 * KiB },
157 { "debug", 0x3f500000, 64 * KiB },
158 { "cpubist", 0x3f501000, 4 * KiB },
159 { "dcu", 0x3fff0000, 64 * KiB },
160 { "hstmr", 0x01c60000, 4 * KiB },
161 { "brom", 0xffff0000, 36 * KiB }
162 };
163
164 /* Per Processor Interrupts */
165 enum {
166 AW_R40_GIC_PPI_MAINT = 9,
167 AW_R40_GIC_PPI_HYPTIMER = 10,
168 AW_R40_GIC_PPI_VIRTTIMER = 11,
169 AW_R40_GIC_PPI_SECTIMER = 13,
170 AW_R40_GIC_PPI_PHYSTIMER = 14
171 };
172
173 /* Shared Processor Interrupts */
174 enum {
175 AW_R40_GIC_SPI_UART0 = 1,
176 AW_R40_GIC_SPI_UART1 = 2,
177 AW_R40_GIC_SPI_UART2 = 3,
178 AW_R40_GIC_SPI_UART3 = 4,
179 AW_R40_GIC_SPI_TWI0 = 7,
180 AW_R40_GIC_SPI_UART4 = 17,
181 AW_R40_GIC_SPI_UART5 = 18,
182 AW_R40_GIC_SPI_UART6 = 19,
183 AW_R40_GIC_SPI_UART7 = 20,
184 AW_R40_GIC_SPI_TIMER0 = 22,
185 AW_R40_GIC_SPI_TIMER1 = 23,
186 AW_R40_GIC_SPI_MMC0 = 32,
187 AW_R40_GIC_SPI_MMC1 = 33,
188 AW_R40_GIC_SPI_MMC2 = 34,
189 AW_R40_GIC_SPI_MMC3 = 35,
190 AW_R40_GIC_SPI_EMAC = 55,
191 AW_R40_GIC_SPI_AHCI = 56,
192 AW_R40_GIC_SPI_OHCI1 = 64,
193 AW_R40_GIC_SPI_OHCI2 = 65,
194 AW_R40_GIC_SPI_EHCI1 = 76,
195 AW_R40_GIC_SPI_EHCI2 = 78,
196 AW_R40_GIC_SPI_GMAC = 85,
197 };
198
199 /* Allwinner R40 general constants */
200 enum {
201 AW_R40_GIC_NUM_SPI = 128
202 };
203
204 #define BOOT0_MAGIC "eGON.BT0"
205
206 /* The low 8-bits of the 'boot_media' field in the SPL header */
207 #define SUNXI_BOOTED_FROM_MMC0 0
208 #define SUNXI_BOOTED_FROM_NAND 1
209 #define SUNXI_BOOTED_FROM_MMC2 2
210 #define SUNXI_BOOTED_FROM_SPI 3
211
212 struct boot_file_head {
213 uint32_t b_instruction;
214 uint8_t magic[8];
215 uint32_t check_sum;
216 uint32_t length;
217 uint32_t pub_head_size;
218 uint32_t fel_script_address;
219 uint32_t fel_uEnv_length;
220 uint32_t dt_name_offset;
221 uint32_t dram_size;
222 uint32_t boot_media;
223 uint32_t string_pool[13];
224 };
225
allwinner_r40_bootrom_setup(AwR40State * s,BlockBackend * blk,int unit)226 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit)
227 {
228 const int64_t rom_size = 32 * KiB;
229 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
230 struct boot_file_head *head = (struct boot_file_head *)buffer;
231
232 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
233 error_report("%s: failed to read BlockBackend data", __func__);
234 exit(1);
235 }
236
237 /* we only check the magic string here. */
238 if (memcmp(head->magic, BOOT0_MAGIC, sizeof(head->magic))) {
239 return false;
240 }
241
242 /*
243 * Simulate the behavior of the bootROM, it will change the boot_media
244 * flag to indicate where the chip is booting from. R40 can boot from
245 * mmc0 or mmc2, the default value of boot_media is zero
246 * (SUNXI_BOOTED_FROM_MMC0), let's fix this flag when it is booting from
247 * the others.
248 */
249 if (unit == 2) {
250 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC2);
251 } else {
252 head->boot_media = cpu_to_le32(SUNXI_BOOTED_FROM_MMC0);
253 }
254
255 rom_add_blob("allwinner-r40.bootrom", buffer, rom_size,
256 rom_size, s->memmap[AW_R40_DEV_SRAM_A1],
257 NULL, NULL, NULL, NULL, false);
258 return true;
259 }
260
allwinner_r40_init(Object * obj)261 static void allwinner_r40_init(Object *obj)
262 {
263 static const char *mmc_names[AW_R40_NUM_MMCS] = {
264 "mmc0", "mmc1", "mmc2", "mmc3"
265 };
266 AwR40State *s = AW_R40(obj);
267
268 s->memmap = allwinner_r40_memmap;
269
270 for (int i = 0; i < AW_R40_NUM_CPUS; i++) {
271 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
272 ARM_CPU_TYPE_NAME("cortex-a7"));
273 }
274
275 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
276
277 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
278 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
279 "clk0-freq");
280 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
281 "clk1-freq");
282
283 object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
284
285 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU);
286
287 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
288 object_initialize_child(obj, mmc_names[i], &s->mmc[i],
289 TYPE_AW_SDHOST_SUN50I_A64);
290 }
291
292 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
293
294 for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
295 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
296 TYPE_PLATFORM_EHCI);
297 object_initialize_child(obj, "ohci[*]", &s->ohci[i],
298 TYPE_SYSBUS_OHCI);
299 }
300
301 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
302
303 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
304 object_initialize_child(obj, "gmac", &s->gmac, TYPE_AW_SUN8I_EMAC);
305 object_property_add_alias(obj, "gmac-phy-addr",
306 OBJECT(&s->gmac), "phy-addr");
307
308 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_R40_DRAMC);
309 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
310 "ram-addr");
311 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
312 "ram-size");
313
314 object_initialize_child(obj, "sramc", &s->sramc, TYPE_AW_SRAMC_SUN8I_R40);
315 }
316
allwinner_r40_realize(DeviceState * dev,Error ** errp)317 static void allwinner_r40_realize(DeviceState *dev, Error **errp)
318 {
319 AwR40State *s = AW_R40(dev);
320
321 /* CPUs */
322 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
323
324 /*
325 * Disable secondary CPUs. Guest EL3 firmware will start
326 * them via CPU reset control registers.
327 */
328 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
329 i > 0);
330
331 /* All exception levels required */
332 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
333 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
334
335 /* Mark realized */
336 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
337 }
338
339 /* Generic Interrupt Controller */
340 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI +
341 GIC_INTERNAL);
342 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
343 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS);
344 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
345 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
346 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
347
348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]);
349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]);
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]);
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]);
352
353 /*
354 * Wire the outputs from each CPU's generic timer and the GICv2
355 * maintenance interrupt signal to the appropriate GIC PPI inputs,
356 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
357 */
358 for (unsigned i = 0; i < AW_R40_NUM_CPUS; i++) {
359 DeviceState *cpudev = DEVICE(&s->cpus[i]);
360 int ppibase = AW_R40_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
361 int irq;
362 /*
363 * Mapping from the output timer irq lines from the CPU to the
364 * GIC PPI inputs used for this board.
365 */
366 const int timer_irq[] = {
367 [GTIMER_PHYS] = AW_R40_GIC_PPI_PHYSTIMER,
368 [GTIMER_VIRT] = AW_R40_GIC_PPI_VIRTTIMER,
369 [GTIMER_HYP] = AW_R40_GIC_PPI_HYPTIMER,
370 [GTIMER_SEC] = AW_R40_GIC_PPI_SECTIMER,
371 };
372
373 /* Connect CPU timer outputs to GIC PPI inputs */
374 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
375 qdev_connect_gpio_out(cpudev, irq,
376 qdev_get_gpio_in(DEVICE(&s->gic),
377 ppibase + timer_irq[irq]));
378 }
379
380 /* Connect GIC outputs to CPU interrupt inputs */
381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
382 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_R40_NUM_CPUS,
384 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_R40_NUM_CPUS),
386 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
387 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_R40_NUM_CPUS),
388 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
389
390 /* GIC maintenance signal */
391 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_R40_NUM_CPUS),
392 qdev_get_gpio_in(DEVICE(&s->gic),
393 ppibase + AW_R40_GIC_PPI_MAINT));
394 }
395
396 /* Timer */
397 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]);
399 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
400 qdev_get_gpio_in(DEVICE(&s->gic),
401 AW_R40_GIC_SPI_TIMER0));
402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
403 qdev_get_gpio_in(DEVICE(&s->gic),
404 AW_R40_GIC_SPI_TIMER1));
405
406 /* SRAM */
407 sysbus_realize(SYS_BUS_DEVICE(&s->sramc), &error_fatal);
408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sramc), 0, s->memmap[AW_R40_DEV_SRAMC]);
409
410 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
411 16 * KiB, &error_abort);
412 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
413 16 * KiB, &error_abort);
414 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3",
415 13 * KiB, &error_abort);
416 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4",
417 3 * KiB, &error_abort);
418 memory_region_add_subregion(get_system_memory(),
419 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1);
420 memory_region_add_subregion(get_system_memory(),
421 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2);
422 memory_region_add_subregion(get_system_memory(),
423 s->memmap[AW_R40_DEV_SRAM_A3], &s->sram_a3);
424 memory_region_add_subregion(get_system_memory(),
425 s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4);
426
427 /* Clock Control Unit */
428 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
430
431 /* SATA / AHCI */
432 sysbus_realize(SYS_BUS_DEVICE(&s->sata), &error_fatal);
433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0,
434 allwinner_r40_memmap[AW_R40_DEV_AHCI]);
435 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0,
436 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_AHCI));
437
438 /* USB */
439 for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
440 g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
441
442 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true,
443 &error_fatal);
444 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
445 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
446 allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2
447 : AW_R40_DEV_EHCI1]);
448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
449 qdev_get_gpio_in(DEVICE(&s->gic),
450 i ? AW_R40_GIC_SPI_EHCI2
451 : AW_R40_GIC_SPI_EHCI1));
452
453 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
454 &error_fatal);
455 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
456 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
457 allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2
458 : AW_R40_DEV_OHCI1]);
459 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
460 qdev_get_gpio_in(DEVICE(&s->gic),
461 i ? AW_R40_GIC_SPI_OHCI2
462 : AW_R40_GIC_SPI_OHCI1));
463 }
464
465 /* SD/MMC */
466 for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
467 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),
468 AW_R40_GIC_SPI_MMC0 + i);
469 const hwaddr addr = s->memmap[AW_R40_DEV_MMC0 + i];
470
471 object_property_set_link(OBJECT(&s->mmc[i]), "dma-memory",
472 OBJECT(get_system_memory()), &error_fatal);
473 sysbus_realize(SYS_BUS_DEVICE(&s->mmc[i]), &error_fatal);
474 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc[i]), 0, addr);
475 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc[i]), 0, irq);
476 }
477
478 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
479 for (int i = 0; i < AW_R40_NUM_UARTS; i++) {
480 static const int uart_irqs[AW_R40_NUM_UARTS] = {
481 AW_R40_GIC_SPI_UART0,
482 AW_R40_GIC_SPI_UART1,
483 AW_R40_GIC_SPI_UART2,
484 AW_R40_GIC_SPI_UART3,
485 AW_R40_GIC_SPI_UART4,
486 AW_R40_GIC_SPI_UART5,
487 AW_R40_GIC_SPI_UART6,
488 AW_R40_GIC_SPI_UART7,
489 };
490 const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i];
491
492 serial_mm_init(get_system_memory(), addr, 2,
493 qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
494 115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
495 }
496
497 /* I2C */
498 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
499 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0]);
500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
501 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0));
502
503 /* DRAMC */
504 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
505 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,
506 s->memmap[AW_R40_DEV_DRAMCOM]);
507 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,
508 s->memmap[AW_R40_DEV_DRAMCTL]);
509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,
510 s->memmap[AW_R40_DEV_DRAMPHY]);
511
512 /* GMAC */
513 qemu_configure_nic_device(DEVICE(&s->gmac), true, "gmac");
514 object_property_set_link(OBJECT(&s->gmac), "dma-memory",
515 OBJECT(get_system_memory()), &error_fatal);
516 sysbus_realize(SYS_BUS_DEVICE(&s->gmac), &error_fatal);
517 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gmac), 0, s->memmap[AW_R40_DEV_GMAC]);
518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gmac), 0,
519 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_GMAC));
520
521 /* EMAC */
522 qemu_configure_nic_device(DEVICE(&s->emac), true, "emac");
523 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
524 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_R40_DEV_EMAC]);
525 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
526 qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC));
527
528 /* WDT */
529 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
530 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
531 allwinner_r40_memmap[AW_R40_DEV_WDT], 1);
532
533 /* Unimplemented devices */
534 for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
535 create_unimplemented_device(r40_unimplemented[i].device_name,
536 r40_unimplemented[i].base,
537 r40_unimplemented[i].size);
538 }
539 }
540
allwinner_r40_class_init(ObjectClass * oc,const void * data)541 static void allwinner_r40_class_init(ObjectClass *oc, const void *data)
542 {
543 DeviceClass *dc = DEVICE_CLASS(oc);
544
545 dc->realize = allwinner_r40_realize;
546 /* Reason: uses serial_hd() in realize function */
547 dc->user_creatable = false;
548 }
549
550 static const TypeInfo allwinner_r40_type_info = {
551 .name = TYPE_AW_R40,
552 .parent = TYPE_DEVICE,
553 .instance_size = sizeof(AwR40State),
554 .instance_init = allwinner_r40_init,
555 .class_init = allwinner_r40_class_init,
556 };
557
allwinner_r40_register_types(void)558 static void allwinner_r40_register_types(void)
559 {
560 type_register_static(&allwinner_r40_type_info);
561 }
562
563 type_init(allwinner_r40_register_types)
564