1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
3
4 #include <linux/gpio/machine.h>
5 #include <linux/gpio/driver.h>
6 #include <linux/gpio/property.h>
7 #include <linux/clk-provider.h>
8 #include <linux/clkdev.h>
9 #include <linux/i2c.h>
10 #include <linux/pci.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/pcs/pcs-xpcs.h>
14 #include <linux/phylink.h>
15
16 #include "../libwx/wx_type.h"
17 #include "../libwx/wx_lib.h"
18 #include "../libwx/wx_hw.h"
19 #include "txgbe_type.h"
20 #include "txgbe_phy.h"
21 #include "txgbe_hw.h"
22
txgbe_swnodes_register(struct txgbe * txgbe)23 static int txgbe_swnodes_register(struct txgbe *txgbe)
24 {
25 struct txgbe_nodes *nodes = &txgbe->nodes;
26 struct pci_dev *pdev = txgbe->wx->pdev;
27 struct software_node *swnodes;
28 u32 id;
29
30 id = pci_dev_id(pdev);
31
32 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id);
33 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id);
34 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id);
35 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id);
36
37 swnodes = nodes->swnodes;
38
39 /* GPIO 0: tx fault
40 * GPIO 1: tx disable
41 * GPIO 2: sfp module absent
42 * GPIO 3: rx signal lost
43 * GPIO 4: rate select, 1G(0) 10G(1)
44 * GPIO 5: rate select, 1G(0) 10G(1)
45 */
46 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default");
47 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props);
48 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH);
49 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH);
50 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW);
51 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH);
52 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH);
53 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH);
54
55 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c");
56 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model");
57 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ);
58 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props);
59 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]);
60
61 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp");
62 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref);
63 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref);
64 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref);
65 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref);
66 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref);
67 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref);
68 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref);
69 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props);
70 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]);
71
72 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status");
73 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref);
74 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props);
75
76 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO];
77 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C];
78 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP];
79 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK];
80
81 return software_node_register_node_group(nodes->group);
82 }
83
txgbe_pcs_read(struct mii_bus * bus,int addr,int devnum,int regnum)84 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum)
85 {
86 struct wx *wx = bus->priv;
87 u32 offset, val;
88
89 if (addr)
90 return -EOPNOTSUPP;
91
92 offset = devnum << 16 | regnum;
93
94 /* Set the LAN port indicator to IDA_ADDR */
95 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
96
97 /* Read the data from IDA_DATA register */
98 val = rd32(wx, TXGBE_XPCS_IDA_DATA);
99
100 return (u16)val;
101 }
102
txgbe_pcs_write(struct mii_bus * bus,int addr,int devnum,int regnum,u16 val)103 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val)
104 {
105 struct wx *wx = bus->priv;
106 u32 offset;
107
108 if (addr)
109 return -EOPNOTSUPP;
110
111 offset = devnum << 16 | regnum;
112
113 /* Set the LAN port indicator to IDA_ADDR */
114 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
115
116 /* Write the data to IDA_DATA register */
117 wr32(wx, TXGBE_XPCS_IDA_DATA, val);
118
119 return 0;
120 }
121
txgbe_mdio_pcs_init(struct txgbe * txgbe)122 static int txgbe_mdio_pcs_init(struct txgbe *txgbe)
123 {
124 struct mii_bus *mii_bus;
125 struct dw_xpcs *xpcs;
126 struct pci_dev *pdev;
127 struct wx *wx;
128 int ret = 0;
129
130 wx = txgbe->wx;
131 pdev = wx->pdev;
132
133 mii_bus = devm_mdiobus_alloc(&pdev->dev);
134 if (!mii_bus)
135 return -ENOMEM;
136
137 mii_bus->name = "txgbe_pcs_mdio_bus";
138 mii_bus->read_c45 = &txgbe_pcs_read;
139 mii_bus->write_c45 = &txgbe_pcs_write;
140 mii_bus->parent = &pdev->dev;
141 mii_bus->phy_mask = ~0;
142 mii_bus->priv = wx;
143 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x",
144 pci_dev_id(pdev));
145
146 ret = devm_mdiobus_register(&pdev->dev, mii_bus);
147 if (ret)
148 return ret;
149
150 xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER);
151 if (IS_ERR(xpcs))
152 return PTR_ERR(xpcs);
153
154 txgbe->xpcs = xpcs;
155
156 return 0;
157 }
158
txgbe_phylink_mac_select(struct phylink_config * config,phy_interface_t interface)159 static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config,
160 phy_interface_t interface)
161 {
162 struct txgbe *txgbe = netdev_to_txgbe(to_net_dev(config->dev));
163
164 if (interface == PHY_INTERFACE_MODE_10GBASER)
165 return &txgbe->xpcs->pcs;
166
167 return NULL;
168 }
169
txgbe_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)170 static void txgbe_mac_config(struct phylink_config *config, unsigned int mode,
171 const struct phylink_link_state *state)
172 {
173 }
174
txgbe_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)175 static void txgbe_mac_link_down(struct phylink_config *config,
176 unsigned int mode, phy_interface_t interface)
177 {
178 struct wx *wx = netdev_priv(to_net_dev(config->dev));
179
180 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
181 }
182
txgbe_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)183 static void txgbe_mac_link_up(struct phylink_config *config,
184 struct phy_device *phy,
185 unsigned int mode, phy_interface_t interface,
186 int speed, int duplex,
187 bool tx_pause, bool rx_pause)
188 {
189 struct wx *wx = netdev_priv(to_net_dev(config->dev));
190 u32 txcfg, wdg;
191
192 txcfg = rd32(wx, WX_MAC_TX_CFG);
193 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK;
194
195 switch (speed) {
196 case SPEED_10000:
197 txcfg |= WX_MAC_TX_CFG_SPEED_10G;
198 break;
199 case SPEED_1000:
200 case SPEED_100:
201 case SPEED_10:
202 txcfg |= WX_MAC_TX_CFG_SPEED_1G;
203 break;
204 default:
205 break;
206 }
207
208 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE);
209
210 /* Re configure MAC Rx */
211 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
212 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
213 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT);
214 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg);
215 }
216
txgbe_mac_prepare(struct phylink_config * config,unsigned int mode,phy_interface_t interface)217 static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode,
218 phy_interface_t interface)
219 {
220 struct wx *wx = netdev_priv(to_net_dev(config->dev));
221
222 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
223 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0);
224
225 return txgbe_disable_sec_tx_path(wx);
226 }
227
txgbe_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)228 static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode,
229 phy_interface_t interface)
230 {
231 struct wx *wx = netdev_priv(to_net_dev(config->dev));
232
233 txgbe_enable_sec_tx_path(wx);
234 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
235
236 return 0;
237 }
238
239 static const struct phylink_mac_ops txgbe_mac_ops = {
240 .mac_select_pcs = txgbe_phylink_mac_select,
241 .mac_prepare = txgbe_mac_prepare,
242 .mac_finish = txgbe_mac_finish,
243 .mac_config = txgbe_mac_config,
244 .mac_link_down = txgbe_mac_link_down,
245 .mac_link_up = txgbe_mac_link_up,
246 };
247
txgbe_phylink_init(struct txgbe * txgbe)248 static int txgbe_phylink_init(struct txgbe *txgbe)
249 {
250 struct fwnode_handle *fwnode = NULL;
251 struct phylink_config *config;
252 struct wx *wx = txgbe->wx;
253 phy_interface_t phy_mode;
254 struct phylink *phylink;
255
256 config = devm_kzalloc(&wx->pdev->dev, sizeof(*config), GFP_KERNEL);
257 if (!config)
258 return -ENOMEM;
259
260 config->dev = &wx->netdev->dev;
261 config->type = PHYLINK_NETDEV;
262 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD |
263 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
264
265 if (wx->media_type == sp_media_copper) {
266 phy_mode = PHY_INTERFACE_MODE_XAUI;
267 __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces);
268 } else {
269 phy_mode = PHY_INTERFACE_MODE_10GBASER;
270 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]);
271 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
272 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
273 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
274 }
275
276 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops);
277 if (IS_ERR(phylink))
278 return PTR_ERR(phylink);
279
280 if (wx->phydev) {
281 int ret;
282
283 ret = phylink_connect_phy(phylink, wx->phydev);
284 if (ret) {
285 phylink_destroy(phylink);
286 return ret;
287 }
288 }
289
290 txgbe->phylink = phylink;
291
292 return 0;
293 }
294
txgbe_gpio_get(struct gpio_chip * chip,unsigned int offset)295 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset)
296 {
297 struct wx *wx = gpiochip_get_data(chip);
298 int val;
299
300 val = rd32m(wx, WX_GPIO_EXT, BIT(offset));
301
302 return !!(val & BIT(offset));
303 }
304
txgbe_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)305 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
306 {
307 struct wx *wx = gpiochip_get_data(chip);
308 u32 val;
309
310 val = rd32(wx, WX_GPIO_DDR);
311 if (BIT(offset) & val)
312 return GPIO_LINE_DIRECTION_OUT;
313
314 return GPIO_LINE_DIRECTION_IN;
315 }
316
txgbe_gpio_direction_in(struct gpio_chip * chip,unsigned int offset)317 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
318 {
319 struct wx *wx = gpiochip_get_data(chip);
320 unsigned long flags;
321
322 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
323 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0);
324 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
325
326 return 0;
327 }
328
txgbe_gpio_direction_out(struct gpio_chip * chip,unsigned int offset,int val)329 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
330 int val)
331 {
332 struct wx *wx = gpiochip_get_data(chip);
333 unsigned long flags;
334 u32 set;
335
336 set = val ? BIT(offset) : 0;
337
338 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
339 wr32m(wx, WX_GPIO_DR, BIT(offset), set);
340 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));
341 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
342
343 return 0;
344 }
345
txgbe_gpio_irq_ack(struct irq_data * d)346 static void txgbe_gpio_irq_ack(struct irq_data *d)
347 {
348 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
349 irq_hw_number_t hwirq = irqd_to_hwirq(d);
350 struct wx *wx = gpiochip_get_data(gc);
351 unsigned long flags;
352
353 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
354 wr32(wx, WX_GPIO_EOI, BIT(hwirq));
355 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
356 }
357
txgbe_gpio_irq_mask(struct irq_data * d)358 static void txgbe_gpio_irq_mask(struct irq_data *d)
359 {
360 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
361 irq_hw_number_t hwirq = irqd_to_hwirq(d);
362 struct wx *wx = gpiochip_get_data(gc);
363 unsigned long flags;
364
365 gpiochip_disable_irq(gc, hwirq);
366
367 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
368 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq));
369 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
370 }
371
txgbe_gpio_irq_unmask(struct irq_data * d)372 static void txgbe_gpio_irq_unmask(struct irq_data *d)
373 {
374 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
375 irq_hw_number_t hwirq = irqd_to_hwirq(d);
376 struct wx *wx = gpiochip_get_data(gc);
377 unsigned long flags;
378
379 gpiochip_enable_irq(gc, hwirq);
380
381 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
382 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0);
383 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
384 }
385
txgbe_toggle_trigger(struct gpio_chip * gc,unsigned int offset)386 static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset)
387 {
388 struct wx *wx = gpiochip_get_data(gc);
389 u32 pol, val;
390
391 pol = rd32(wx, WX_GPIO_POLARITY);
392 val = rd32(wx, WX_GPIO_EXT);
393
394 if (val & BIT(offset))
395 pol &= ~BIT(offset);
396 else
397 pol |= BIT(offset);
398
399 wr32(wx, WX_GPIO_POLARITY, pol);
400 }
401
txgbe_gpio_set_type(struct irq_data * d,unsigned int type)402 static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type)
403 {
404 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
405 irq_hw_number_t hwirq = irqd_to_hwirq(d);
406 struct wx *wx = gpiochip_get_data(gc);
407 u32 level, polarity, mask;
408 unsigned long flags;
409
410 mask = BIT(hwirq);
411
412 if (type & IRQ_TYPE_LEVEL_MASK) {
413 level = 0;
414 irq_set_handler_locked(d, handle_level_irq);
415 } else {
416 level = mask;
417 irq_set_handler_locked(d, handle_edge_irq);
418 }
419
420 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
421 polarity = mask;
422 else
423 polarity = 0;
424
425 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
426
427 wr32m(wx, WX_GPIO_INTEN, mask, mask);
428 wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level);
429 if (type == IRQ_TYPE_EDGE_BOTH)
430 txgbe_toggle_trigger(gc, hwirq);
431 else
432 wr32m(wx, WX_GPIO_POLARITY, mask, polarity);
433
434 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
435
436 return 0;
437 }
438
439 static const struct irq_chip txgbe_gpio_irq_chip = {
440 .name = "txgbe_gpio_irq",
441 .irq_ack = txgbe_gpio_irq_ack,
442 .irq_mask = txgbe_gpio_irq_mask,
443 .irq_unmask = txgbe_gpio_irq_unmask,
444 .irq_set_type = txgbe_gpio_set_type,
445 .flags = IRQCHIP_IMMUTABLE,
446 GPIOCHIP_IRQ_RESOURCE_HELPERS,
447 };
448
txgbe_irq_handler(struct irq_desc * desc)449 static void txgbe_irq_handler(struct irq_desc *desc)
450 {
451 struct irq_chip *chip = irq_desc_get_chip(desc);
452 struct wx *wx = irq_desc_get_handler_data(desc);
453 struct txgbe *txgbe = wx->priv;
454 irq_hw_number_t hwirq;
455 unsigned long gpioirq;
456 struct gpio_chip *gc;
457 unsigned long flags;
458 u32 eicr;
459
460 eicr = wx_misc_isb(wx, WX_ISB_MISC);
461
462 chained_irq_enter(chip, desc);
463
464 gpioirq = rd32(wx, WX_GPIO_INTSTATUS);
465
466 gc = txgbe->gpio;
467 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) {
468 int gpio = irq_find_mapping(gc->irq.domain, hwirq);
469 u32 irq_type = irq_get_trigger_type(gpio);
470
471 generic_handle_domain_irq(gc->irq.domain, hwirq);
472
473 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
474 raw_spin_lock_irqsave(&wx->gpio_lock, flags);
475 txgbe_toggle_trigger(gc, hwirq);
476 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
477 }
478 }
479
480 chained_irq_exit(chip, desc);
481
482 if (eicr & (TXGBE_PX_MISC_ETH_LK | TXGBE_PX_MISC_ETH_LKDN |
483 TXGBE_PX_MISC_ETH_AN)) {
484 u32 reg = rd32(wx, TXGBE_CFG_PORT_ST);
485
486 phylink_mac_change(txgbe->phylink, !!(reg & TXGBE_CFG_PORT_ST_LINK_UP));
487 }
488
489 /* unmask interrupt */
490 wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
491 }
492
txgbe_gpio_init(struct txgbe * txgbe)493 static int txgbe_gpio_init(struct txgbe *txgbe)
494 {
495 struct gpio_irq_chip *girq;
496 struct gpio_chip *gc;
497 struct device *dev;
498 struct wx *wx;
499 int ret;
500
501 wx = txgbe->wx;
502 dev = &wx->pdev->dev;
503
504 raw_spin_lock_init(&wx->gpio_lock);
505
506 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
507 if (!gc)
508 return -ENOMEM;
509
510 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x",
511 pci_dev_id(wx->pdev));
512 if (!gc->label)
513 return -ENOMEM;
514
515 gc->base = -1;
516 gc->ngpio = 6;
517 gc->owner = THIS_MODULE;
518 gc->parent = dev;
519 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]);
520 gc->get = txgbe_gpio_get;
521 gc->get_direction = txgbe_gpio_get_direction;
522 gc->direction_input = txgbe_gpio_direction_in;
523 gc->direction_output = txgbe_gpio_direction_out;
524
525 girq = &gc->irq;
526 gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip);
527 girq->parent_handler = txgbe_irq_handler;
528 girq->parent_handler_data = wx;
529 girq->num_parents = 1;
530 girq->parents = devm_kcalloc(dev, girq->num_parents,
531 sizeof(*girq->parents), GFP_KERNEL);
532 if (!girq->parents)
533 return -ENOMEM;
534 girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector;
535 girq->default_type = IRQ_TYPE_NONE;
536 girq->handler = handle_bad_irq;
537
538 ret = devm_gpiochip_add_data(dev, gc, wx);
539 if (ret)
540 return ret;
541
542 txgbe->gpio = gc;
543
544 return 0;
545 }
546
txgbe_clock_register(struct txgbe * txgbe)547 static int txgbe_clock_register(struct txgbe *txgbe)
548 {
549 struct pci_dev *pdev = txgbe->wx->pdev;
550 struct clk_lookup *clock;
551 char clk_name[32];
552 struct clk *clk;
553
554 snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d",
555 pci_dev_id(pdev));
556
557 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000);
558 if (IS_ERR(clk))
559 return PTR_ERR(clk);
560
561 clock = clkdev_create(clk, NULL, clk_name);
562 if (!clock) {
563 clk_unregister(clk);
564 return -ENOMEM;
565 }
566
567 txgbe->clk = clk;
568 txgbe->clock = clock;
569
570 return 0;
571 }
572
txgbe_i2c_read(void * context,unsigned int reg,unsigned int * val)573 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val)
574 {
575 struct wx *wx = context;
576
577 *val = rd32(wx, reg + TXGBE_I2C_BASE);
578
579 return 0;
580 }
581
txgbe_i2c_write(void * context,unsigned int reg,unsigned int val)582 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val)
583 {
584 struct wx *wx = context;
585
586 wr32(wx, reg + TXGBE_I2C_BASE, val);
587
588 return 0;
589 }
590
591 static const struct regmap_config i2c_regmap_config = {
592 .reg_bits = 32,
593 .val_bits = 32,
594 .reg_read = txgbe_i2c_read,
595 .reg_write = txgbe_i2c_write,
596 .fast_io = true,
597 };
598
txgbe_i2c_register(struct txgbe * txgbe)599 static int txgbe_i2c_register(struct txgbe *txgbe)
600 {
601 struct platform_device_info info = {};
602 struct platform_device *i2c_dev;
603 struct regmap *i2c_regmap;
604 struct pci_dev *pdev;
605 struct wx *wx;
606
607 wx = txgbe->wx;
608 pdev = wx->pdev;
609 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config);
610 if (IS_ERR(i2c_regmap)) {
611 wx_err(wx, "failed to init I2C regmap\n");
612 return PTR_ERR(i2c_regmap);
613 }
614
615 info.parent = &pdev->dev;
616 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]);
617 info.name = "i2c_designware";
618 info.id = pci_dev_id(pdev);
619
620 info.res = &DEFINE_RES_IRQ(pdev->irq);
621 info.num_res = 1;
622 i2c_dev = platform_device_register_full(&info);
623 if (IS_ERR(i2c_dev))
624 return PTR_ERR(i2c_dev);
625
626 txgbe->i2c_dev = i2c_dev;
627
628 return 0;
629 }
630
txgbe_sfp_register(struct txgbe * txgbe)631 static int txgbe_sfp_register(struct txgbe *txgbe)
632 {
633 struct pci_dev *pdev = txgbe->wx->pdev;
634 struct platform_device_info info = {};
635 struct platform_device *sfp_dev;
636
637 info.parent = &pdev->dev;
638 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]);
639 info.name = "sfp";
640 info.id = pci_dev_id(pdev);
641 sfp_dev = platform_device_register_full(&info);
642 if (IS_ERR(sfp_dev))
643 return PTR_ERR(sfp_dev);
644
645 txgbe->sfp_dev = sfp_dev;
646
647 return 0;
648 }
649
txgbe_phy_read(struct mii_bus * bus,int phy_addr,int devnum,int regnum)650 static int txgbe_phy_read(struct mii_bus *bus, int phy_addr,
651 int devnum, int regnum)
652 {
653 struct wx *wx = bus->priv;
654 u32 val, command;
655 int ret;
656
657 /* setup and write the address cycle command */
658 command = WX_MSCA_RA(regnum) |
659 WX_MSCA_PA(phy_addr) |
660 WX_MSCA_DA(devnum);
661 wr32(wx, WX_MSCA, command);
662
663 command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY;
664 wr32(wx, WX_MSCC, command);
665
666 /* wait to complete */
667 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
668 100000, false, wx, WX_MSCC);
669 if (ret) {
670 wx_err(wx, "Mdio read c45 command did not complete.\n");
671 return ret;
672 }
673
674 return (u16)rd32(wx, WX_MSCC);
675 }
676
txgbe_phy_write(struct mii_bus * bus,int phy_addr,int devnum,int regnum,u16 value)677 static int txgbe_phy_write(struct mii_bus *bus, int phy_addr,
678 int devnum, int regnum, u16 value)
679 {
680 struct wx *wx = bus->priv;
681 int ret, command;
682 u16 val;
683
684 /* setup and write the address cycle command */
685 command = WX_MSCA_RA(regnum) |
686 WX_MSCA_PA(phy_addr) |
687 WX_MSCA_DA(devnum);
688 wr32(wx, WX_MSCA, command);
689
690 command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY;
691 wr32(wx, WX_MSCC, command);
692
693 /* wait to complete */
694 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,
695 100000, false, wx, WX_MSCC);
696 if (ret)
697 wx_err(wx, "Mdio write c45 command did not complete.\n");
698
699 return ret;
700 }
701
txgbe_ext_phy_init(struct txgbe * txgbe)702 static int txgbe_ext_phy_init(struct txgbe *txgbe)
703 {
704 struct phy_device *phydev;
705 struct mii_bus *mii_bus;
706 struct pci_dev *pdev;
707 struct wx *wx;
708 int ret = 0;
709
710 wx = txgbe->wx;
711 pdev = wx->pdev;
712
713 mii_bus = devm_mdiobus_alloc(&pdev->dev);
714 if (!mii_bus)
715 return -ENOMEM;
716
717 mii_bus->name = "txgbe_mii_bus";
718 mii_bus->read_c45 = &txgbe_phy_read;
719 mii_bus->write_c45 = &txgbe_phy_write;
720 mii_bus->parent = &pdev->dev;
721 mii_bus->phy_mask = GENMASK(31, 1);
722 mii_bus->priv = wx;
723 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x",
724 (pdev->bus->number << 8) | pdev->devfn);
725
726 ret = devm_mdiobus_register(&pdev->dev, mii_bus);
727 if (ret) {
728 wx_err(wx, "failed to register MDIO bus: %d\n", ret);
729 return ret;
730 }
731
732 phydev = phy_find_first(mii_bus);
733 if (!phydev) {
734 wx_err(wx, "no PHY found\n");
735 return -ENODEV;
736 }
737
738 phy_attached_info(phydev);
739
740 wx->link = 0;
741 wx->speed = 0;
742 wx->duplex = 0;
743 wx->phydev = phydev;
744
745 ret = txgbe_phylink_init(txgbe);
746 if (ret) {
747 wx_err(wx, "failed to init phylink: %d\n", ret);
748 return ret;
749 }
750
751 return 0;
752 }
753
txgbe_init_phy(struct txgbe * txgbe)754 int txgbe_init_phy(struct txgbe *txgbe)
755 {
756 int ret;
757
758 if (txgbe->wx->media_type == sp_media_copper)
759 return txgbe_ext_phy_init(txgbe);
760
761 ret = txgbe_swnodes_register(txgbe);
762 if (ret) {
763 wx_err(txgbe->wx, "failed to register software nodes\n");
764 return ret;
765 }
766
767 ret = txgbe_mdio_pcs_init(txgbe);
768 if (ret) {
769 wx_err(txgbe->wx, "failed to init mdio pcs: %d\n", ret);
770 goto err_unregister_swnode;
771 }
772
773 ret = txgbe_phylink_init(txgbe);
774 if (ret) {
775 wx_err(txgbe->wx, "failed to init phylink\n");
776 goto err_destroy_xpcs;
777 }
778
779 ret = txgbe_gpio_init(txgbe);
780 if (ret) {
781 wx_err(txgbe->wx, "failed to init gpio\n");
782 goto err_destroy_phylink;
783 }
784
785 ret = txgbe_clock_register(txgbe);
786 if (ret) {
787 wx_err(txgbe->wx, "failed to register clock: %d\n", ret);
788 goto err_destroy_phylink;
789 }
790
791 ret = txgbe_i2c_register(txgbe);
792 if (ret) {
793 wx_err(txgbe->wx, "failed to init i2c interface: %d\n", ret);
794 goto err_unregister_clk;
795 }
796
797 ret = txgbe_sfp_register(txgbe);
798 if (ret) {
799 wx_err(txgbe->wx, "failed to register sfp\n");
800 goto err_unregister_i2c;
801 }
802
803 return 0;
804
805 err_unregister_i2c:
806 platform_device_unregister(txgbe->i2c_dev);
807 err_unregister_clk:
808 clkdev_drop(txgbe->clock);
809 clk_unregister(txgbe->clk);
810 err_destroy_phylink:
811 phylink_destroy(txgbe->phylink);
812 err_destroy_xpcs:
813 xpcs_destroy(txgbe->xpcs);
814 err_unregister_swnode:
815 software_node_unregister_node_group(txgbe->nodes.group);
816
817 return ret;
818 }
819
txgbe_remove_phy(struct txgbe * txgbe)820 void txgbe_remove_phy(struct txgbe *txgbe)
821 {
822 if (txgbe->wx->media_type == sp_media_copper) {
823 phylink_disconnect_phy(txgbe->phylink);
824 phylink_destroy(txgbe->phylink);
825 return;
826 }
827
828 platform_device_unregister(txgbe->sfp_dev);
829 platform_device_unregister(txgbe->i2c_dev);
830 clkdev_drop(txgbe->clock);
831 clk_unregister(txgbe->clk);
832 phylink_destroy(txgbe->phylink);
833 xpcs_destroy(txgbe->xpcs);
834 software_node_unregister_node_group(txgbe->nodes.group);
835 }
836