1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom BCM63xx SPI controller support 4 * 5 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 6 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/spi/spi.h> 17 #include <linux/completion.h> 18 #include <linux/err.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/reset.h> 22 23 /* BCM 6338/6348 SPI core */ 24 #define SPI_6348_RSET_SIZE 64 25 #define SPI_6348_CMD 0x00 /* 16-bits register */ 26 #define SPI_6348_INT_STATUS 0x02 27 #define SPI_6348_INT_MASK_ST 0x03 28 #define SPI_6348_INT_MASK 0x04 29 #define SPI_6348_ST 0x05 30 #define SPI_6348_CLK_CFG 0x06 31 #define SPI_6348_FILL_BYTE 0x07 32 #define SPI_6348_MSG_TAIL 0x09 33 #define SPI_6348_RX_TAIL 0x0b 34 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ 35 #define SPI_6348_MSG_CTL_WIDTH 8 36 #define SPI_6348_MSG_DATA 0x41 37 #define SPI_6348_MSG_DATA_SIZE 0x3f 38 #define SPI_6348_RX_DATA 0x80 39 #define SPI_6348_RX_DATA_SIZE 0x3f 40 41 /* BCM 3368/6358/6262/6368 SPI core */ 42 #define SPI_6358_RSET_SIZE 1804 43 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 44 #define SPI_6358_MSG_CTL_WIDTH 16 45 #define SPI_6358_MSG_DATA 0x02 46 #define SPI_6358_MSG_DATA_SIZE 0x21e 47 #define SPI_6358_RX_DATA 0x400 48 #define SPI_6358_RX_DATA_SIZE 0x220 49 #define SPI_6358_CMD 0x700 /* 16-bits register */ 50 #define SPI_6358_INT_STATUS 0x702 51 #define SPI_6358_INT_MASK_ST 0x703 52 #define SPI_6358_INT_MASK 0x704 53 #define SPI_6358_ST 0x705 54 #define SPI_6358_CLK_CFG 0x706 55 #define SPI_6358_FILL_BYTE 0x707 56 #define SPI_6358_MSG_TAIL 0x709 57 #define SPI_6358_RX_TAIL 0x70B 58 59 /* Shared SPI definitions */ 60 61 /* Message configuration */ 62 #define SPI_FD_RW 0x00 63 #define SPI_HD_W 0x01 64 #define SPI_HD_R 0x02 65 #define SPI_BYTE_CNT_SHIFT 0 66 #define SPI_6348_MSG_TYPE_SHIFT 6 67 #define SPI_6358_MSG_TYPE_SHIFT 14 68 69 /* Command */ 70 #define SPI_CMD_NOOP 0x00 71 #define SPI_CMD_SOFT_RESET 0x01 72 #define SPI_CMD_HARD_RESET 0x02 73 #define SPI_CMD_START_IMMEDIATE 0x03 74 #define SPI_CMD_COMMAND_SHIFT 0 75 #define SPI_CMD_COMMAND_MASK 0x000f 76 #define SPI_CMD_DEVICE_ID_SHIFT 4 77 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 78 #define SPI_CMD_ONE_BYTE_SHIFT 11 79 #define SPI_CMD_ONE_WIRE_SHIFT 12 80 #define SPI_DEV_ID_0 0 81 #define SPI_DEV_ID_1 1 82 #define SPI_DEV_ID_2 2 83 #define SPI_DEV_ID_3 3 84 85 /* Interrupt mask */ 86 #define SPI_INTR_CMD_DONE 0x01 87 #define SPI_INTR_RX_OVERFLOW 0x02 88 #define SPI_INTR_TX_UNDERFLOW 0x04 89 #define SPI_INTR_TX_OVERFLOW 0x08 90 #define SPI_INTR_RX_UNDERFLOW 0x10 91 #define SPI_INTR_CLEAR_ALL 0x1f 92 93 /* Status */ 94 #define SPI_RX_EMPTY 0x02 95 #define SPI_CMD_BUSY 0x04 96 #define SPI_SERIAL_BUSY 0x08 97 98 /* Clock configuration */ 99 #define SPI_CLK_20MHZ 0x00 100 #define SPI_CLK_0_391MHZ 0x01 101 #define SPI_CLK_0_781MHZ 0x02 /* default */ 102 #define SPI_CLK_1_563MHZ 0x03 103 #define SPI_CLK_3_125MHZ 0x04 104 #define SPI_CLK_6_250MHZ 0x05 105 #define SPI_CLK_12_50MHZ 0x06 106 #define SPI_CLK_MASK 0x07 107 #define SPI_SSOFFTIME_MASK 0x38 108 #define SPI_SSOFFTIME_SHIFT 3 109 #define SPI_BYTE_SWAP 0x80 110 111 enum bcm63xx_regs_spi { 112 SPI_CMD, 113 SPI_INT_STATUS, 114 SPI_INT_MASK_ST, 115 SPI_INT_MASK, 116 SPI_ST, 117 SPI_CLK_CFG, 118 SPI_FILL_BYTE, 119 SPI_MSG_TAIL, 120 SPI_RX_TAIL, 121 SPI_MSG_CTL, 122 SPI_MSG_DATA, 123 SPI_RX_DATA, 124 SPI_MSG_TYPE_SHIFT, 125 SPI_MSG_CTL_WIDTH, 126 SPI_MSG_DATA_SIZE, 127 }; 128 129 #define BCM63XX_SPI_MAX_PREPEND 7 130 131 #define BCM63XX_SPI_MAX_CS 8 132 #define BCM63XX_SPI_BUS_NUM 0 133 134 struct bcm63xx_spi { 135 struct completion done; 136 137 void __iomem *regs; 138 int irq; 139 140 /* Platform data */ 141 const unsigned long *reg_offsets; 142 unsigned int fifo_size; 143 unsigned int msg_type_shift; 144 unsigned int msg_ctl_width; 145 146 /* data iomem */ 147 u8 __iomem *tx_io; 148 const u8 __iomem *rx_io; 149 150 struct clk *clk; 151 struct platform_device *pdev; 152 }; 153 bcm_spi_readb(struct bcm63xx_spi * bs,unsigned int offset)154 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, 155 unsigned int offset) 156 { 157 return readb(bs->regs + bs->reg_offsets[offset]); 158 } 159 bcm_spi_writeb(struct bcm63xx_spi * bs,u8 value,unsigned int offset)160 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, 161 u8 value, unsigned int offset) 162 { 163 writeb(value, bs->regs + bs->reg_offsets[offset]); 164 } 165 bcm_spi_writew(struct bcm63xx_spi * bs,u16 value,unsigned int offset)166 static inline void bcm_spi_writew(struct bcm63xx_spi *bs, 167 u16 value, unsigned int offset) 168 { 169 #ifdef CONFIG_CPU_BIG_ENDIAN 170 iowrite16be(value, bs->regs + bs->reg_offsets[offset]); 171 #else 172 writew(value, bs->regs + bs->reg_offsets[offset]); 173 #endif 174 } 175 176 static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { 177 { 20000000, SPI_CLK_20MHZ }, 178 { 12500000, SPI_CLK_12_50MHZ }, 179 { 6250000, SPI_CLK_6_250MHZ }, 180 { 3125000, SPI_CLK_3_125MHZ }, 181 { 1563000, SPI_CLK_1_563MHZ }, 182 { 781000, SPI_CLK_0_781MHZ }, 183 { 391000, SPI_CLK_0_391MHZ } 184 }; 185 bcm63xx_spi_setup_transfer(struct spi_device * spi,struct spi_transfer * t)186 static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 187 struct spi_transfer *t) 188 { 189 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller); 190 u8 clk_cfg, reg; 191 int i; 192 193 /* Default to lowest clock configuration */ 194 clk_cfg = SPI_CLK_0_391MHZ; 195 196 /* Find the closest clock configuration */ 197 for (i = 0; i < SPI_CLK_MASK; i++) { 198 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { 199 clk_cfg = bcm63xx_spi_freq_table[i][1]; 200 break; 201 } 202 } 203 204 /* clear existing clock configuration bits of the register */ 205 reg = bcm_spi_readb(bs, SPI_CLK_CFG); 206 reg &= ~SPI_CLK_MASK; 207 reg |= clk_cfg; 208 209 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 210 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 211 clk_cfg, t->speed_hz); 212 } 213 214 /* the spi->mode bits understood by this driver: */ 215 #define MODEBITS (SPI_CPOL | SPI_CPHA) 216 bcm63xx_txrx_bufs(struct spi_device * spi,struct spi_transfer * first,unsigned int num_transfers)217 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, 218 unsigned int num_transfers) 219 { 220 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller); 221 u16 msg_ctl; 222 u16 cmd; 223 unsigned int i, timeout = 0, prepend_len = 0, len = 0; 224 struct spi_transfer *t = first; 225 bool do_rx = false; 226 bool do_tx = false; 227 228 /* Disable the CMD_DONE interrupt */ 229 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 230 231 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 232 t->tx_buf, t->rx_buf, t->len); 233 234 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) 235 prepend_len = t->len; 236 237 /* prepare the buffer */ 238 for (i = 0; i < num_transfers; i++) { 239 if (t->tx_buf) { 240 do_tx = true; 241 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); 242 243 /* don't prepend more than one tx */ 244 if (t != first) 245 prepend_len = 0; 246 } 247 248 if (t->rx_buf) { 249 do_rx = true; 250 /* prepend is half-duplex write only */ 251 if (t == first) 252 prepend_len = 0; 253 } 254 255 len += t->len; 256 257 t = list_entry(t->transfer_list.next, struct spi_transfer, 258 transfer_list); 259 } 260 261 reinit_completion(&bs->done); 262 263 /* Fill in the Message control register */ 264 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 265 266 if (do_rx && do_tx && prepend_len == 0) 267 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); 268 else if (do_rx) 269 msg_ctl |= (SPI_HD_R << bs->msg_type_shift); 270 else if (do_tx) 271 msg_ctl |= (SPI_HD_W << bs->msg_type_shift); 272 273 switch (bs->msg_ctl_width) { 274 case 8: 275 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); 276 break; 277 case 16: 278 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); 279 break; 280 } 281 282 /* Issue the transfer */ 283 cmd = SPI_CMD_START_IMMEDIATE; 284 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 285 cmd |= (spi_get_chipselect(spi, 0) << SPI_CMD_DEVICE_ID_SHIFT); 286 bcm_spi_writew(bs, cmd, SPI_CMD); 287 288 /* Enable the CMD_DONE interrupt */ 289 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 290 291 timeout = wait_for_completion_timeout(&bs->done, HZ); 292 if (!timeout) 293 return -ETIMEDOUT; 294 295 if (!do_rx) 296 return 0; 297 298 len = 0; 299 t = first; 300 /* Read out all the data */ 301 for (i = 0; i < num_transfers; i++) { 302 if (t->rx_buf) 303 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); 304 305 if (t != first || prepend_len == 0) 306 len += t->len; 307 308 t = list_entry(t->transfer_list.next, struct spi_transfer, 309 transfer_list); 310 } 311 312 return 0; 313 } 314 bcm63xx_spi_transfer_one(struct spi_controller * host,struct spi_message * m)315 static int bcm63xx_spi_transfer_one(struct spi_controller *host, 316 struct spi_message *m) 317 { 318 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 319 struct spi_transfer *t, *first = NULL; 320 struct spi_device *spi = m->spi; 321 int status = 0; 322 unsigned int n_transfers = 0, total_len = 0; 323 bool can_use_prepend = false; 324 325 /* 326 * This SPI controller does not support keeping CS active after a 327 * transfer. 328 * Work around this by merging as many transfers we can into one big 329 * full-duplex transfers. 330 */ 331 list_for_each_entry(t, &m->transfers, transfer_list) { 332 if (!first) 333 first = t; 334 335 n_transfers++; 336 total_len += t->len; 337 338 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && 339 first->len <= BCM63XX_SPI_MAX_PREPEND) 340 can_use_prepend = true; 341 else if (can_use_prepend && t->tx_buf) 342 can_use_prepend = false; 343 344 /* we can only transfer one fifo worth of data */ 345 if ((can_use_prepend && 346 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || 347 (!can_use_prepend && total_len > bs->fifo_size)) { 348 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", 349 total_len, bs->fifo_size); 350 status = -EINVAL; 351 goto exit; 352 } 353 354 /* all combined transfers have to have the same speed */ 355 if (t->speed_hz != first->speed_hz) { 356 dev_err(&spi->dev, "unable to change speed between transfers\n"); 357 status = -EINVAL; 358 goto exit; 359 } 360 361 /* CS will be deasserted directly after transfer */ 362 if (t->delay.value) { 363 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); 364 status = -EINVAL; 365 goto exit; 366 } 367 368 if (t->cs_change || 369 list_is_last(&t->transfer_list, &m->transfers)) { 370 /* configure adapter for a new transfer */ 371 bcm63xx_spi_setup_transfer(spi, first); 372 373 /* send the data */ 374 status = bcm63xx_txrx_bufs(spi, first, n_transfers); 375 if (status) 376 goto exit; 377 378 m->actual_length += total_len; 379 380 first = NULL; 381 n_transfers = 0; 382 total_len = 0; 383 can_use_prepend = false; 384 } 385 } 386 exit: 387 m->status = status; 388 spi_finalize_current_message(host); 389 390 return 0; 391 } 392 393 /* This driver supports single host mode only. Hence 394 * CMD_DONE is the only interrupt we care about 395 */ bcm63xx_spi_interrupt(int irq,void * dev_id)396 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) 397 { 398 struct spi_controller *host = (struct spi_controller *)dev_id; 399 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 400 u8 intr; 401 402 /* Read interupts and clear them immediately */ 403 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 404 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 405 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 406 407 /* A transfer completed */ 408 if (intr & SPI_INTR_CMD_DONE) 409 complete(&bs->done); 410 411 return IRQ_HANDLED; 412 } 413 bcm63xx_spi_max_length(struct spi_device * spi)414 static size_t bcm63xx_spi_max_length(struct spi_device *spi) 415 { 416 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller); 417 418 return bs->fifo_size; 419 } 420 421 static const unsigned long bcm6348_spi_reg_offsets[] = { 422 [SPI_CMD] = SPI_6348_CMD, 423 [SPI_INT_STATUS] = SPI_6348_INT_STATUS, 424 [SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST, 425 [SPI_INT_MASK] = SPI_6348_INT_MASK, 426 [SPI_ST] = SPI_6348_ST, 427 [SPI_CLK_CFG] = SPI_6348_CLK_CFG, 428 [SPI_FILL_BYTE] = SPI_6348_FILL_BYTE, 429 [SPI_MSG_TAIL] = SPI_6348_MSG_TAIL, 430 [SPI_RX_TAIL] = SPI_6348_RX_TAIL, 431 [SPI_MSG_CTL] = SPI_6348_MSG_CTL, 432 [SPI_MSG_DATA] = SPI_6348_MSG_DATA, 433 [SPI_RX_DATA] = SPI_6348_RX_DATA, 434 [SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT, 435 [SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH, 436 [SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE, 437 }; 438 439 static const unsigned long bcm6358_spi_reg_offsets[] = { 440 [SPI_CMD] = SPI_6358_CMD, 441 [SPI_INT_STATUS] = SPI_6358_INT_STATUS, 442 [SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST, 443 [SPI_INT_MASK] = SPI_6358_INT_MASK, 444 [SPI_ST] = SPI_6358_ST, 445 [SPI_CLK_CFG] = SPI_6358_CLK_CFG, 446 [SPI_FILL_BYTE] = SPI_6358_FILL_BYTE, 447 [SPI_MSG_TAIL] = SPI_6358_MSG_TAIL, 448 [SPI_RX_TAIL] = SPI_6358_RX_TAIL, 449 [SPI_MSG_CTL] = SPI_6358_MSG_CTL, 450 [SPI_MSG_DATA] = SPI_6358_MSG_DATA, 451 [SPI_RX_DATA] = SPI_6358_RX_DATA, 452 [SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT, 453 [SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH, 454 [SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE, 455 }; 456 457 static const struct platform_device_id bcm63xx_spi_dev_match[] = { 458 { 459 .name = "bcm6348-spi", 460 .driver_data = (unsigned long)bcm6348_spi_reg_offsets, 461 }, 462 { 463 .name = "bcm6358-spi", 464 .driver_data = (unsigned long)bcm6358_spi_reg_offsets, 465 }, 466 { 467 }, 468 }; 469 MODULE_DEVICE_TABLE(platform, bcm63xx_spi_dev_match); 470 471 static const struct of_device_id bcm63xx_spi_of_match[] = { 472 { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets }, 473 { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets }, 474 { }, 475 }; 476 MODULE_DEVICE_TABLE(of, bcm63xx_spi_of_match); 477 bcm63xx_spi_probe(struct platform_device * pdev)478 static int bcm63xx_spi_probe(struct platform_device *pdev) 479 { 480 struct resource *r; 481 const unsigned long *bcm63xx_spireg; 482 struct device *dev = &pdev->dev; 483 int irq, bus_num; 484 struct spi_controller *host; 485 struct clk *clk; 486 struct bcm63xx_spi *bs; 487 int ret; 488 u32 num_cs = BCM63XX_SPI_MAX_CS; 489 struct reset_control *reset; 490 491 if (dev->of_node) { 492 const struct of_device_id *match; 493 494 match = of_match_node(bcm63xx_spi_of_match, dev->of_node); 495 if (!match) 496 return -EINVAL; 497 bcm63xx_spireg = match->data; 498 499 of_property_read_u32(dev->of_node, "num-cs", &num_cs); 500 if (num_cs > BCM63XX_SPI_MAX_CS) { 501 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", 502 num_cs); 503 num_cs = BCM63XX_SPI_MAX_CS; 504 } 505 506 bus_num = -1; 507 } else if (pdev->id_entry->driver_data) { 508 const struct platform_device_id *match = pdev->id_entry; 509 510 bcm63xx_spireg = (const unsigned long *)match->driver_data; 511 bus_num = BCM63XX_SPI_BUS_NUM; 512 } else { 513 return -EINVAL; 514 } 515 516 irq = platform_get_irq(pdev, 0); 517 if (irq < 0) 518 return irq; 519 520 clk = devm_clk_get(dev, "spi"); 521 if (IS_ERR(clk)) { 522 dev_err(dev, "no clock for device\n"); 523 return PTR_ERR(clk); 524 } 525 526 reset = devm_reset_control_get_optional_exclusive(dev, NULL); 527 if (IS_ERR(reset)) 528 return PTR_ERR(reset); 529 530 host = spi_alloc_host(dev, sizeof(*bs)); 531 if (!host) { 532 dev_err(dev, "out of memory\n"); 533 return -ENOMEM; 534 } 535 536 bs = spi_controller_get_devdata(host); 537 init_completion(&bs->done); 538 539 platform_set_drvdata(pdev, host); 540 bs->pdev = pdev; 541 542 bs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 543 if (IS_ERR(bs->regs)) { 544 ret = PTR_ERR(bs->regs); 545 goto out_err; 546 } 547 548 bs->irq = irq; 549 bs->clk = clk; 550 bs->reg_offsets = bcm63xx_spireg; 551 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE]; 552 553 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, 554 pdev->name, host); 555 if (ret) { 556 dev_err(dev, "unable to request irq\n"); 557 goto out_err; 558 } 559 560 host->dev.of_node = dev->of_node; 561 host->bus_num = bus_num; 562 host->num_chipselect = num_cs; 563 host->transfer_one_message = bcm63xx_spi_transfer_one; 564 host->mode_bits = MODEBITS; 565 host->bits_per_word_mask = SPI_BPW_MASK(8); 566 host->max_transfer_size = bcm63xx_spi_max_length; 567 host->max_message_size = bcm63xx_spi_max_length; 568 host->auto_runtime_pm = true; 569 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; 570 bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH]; 571 bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]); 572 bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]); 573 574 /* Initialize hardware */ 575 ret = clk_prepare_enable(bs->clk); 576 if (ret) 577 goto out_err; 578 579 ret = reset_control_reset(reset); 580 if (ret) { 581 dev_err(dev, "unable to reset device: %d\n", ret); 582 goto out_clk_disable; 583 } 584 585 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 586 587 ret = devm_pm_runtime_enable(&pdev->dev); 588 if (ret) 589 goto out_clk_disable; 590 591 /* register and we are done */ 592 ret = devm_spi_register_controller(dev, host); 593 if (ret) { 594 dev_err(dev, "spi register failed\n"); 595 goto out_clk_disable; 596 } 597 598 dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n", 599 r, irq, bs->fifo_size); 600 601 return 0; 602 603 out_clk_disable: 604 clk_disable_unprepare(clk); 605 out_err: 606 spi_controller_put(host); 607 return ret; 608 } 609 bcm63xx_spi_remove(struct platform_device * pdev)610 static void bcm63xx_spi_remove(struct platform_device *pdev) 611 { 612 struct spi_controller *host = platform_get_drvdata(pdev); 613 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 614 615 /* reset spi block */ 616 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 617 618 /* HW shutdown */ 619 clk_disable_unprepare(bs->clk); 620 } 621 bcm63xx_spi_suspend(struct device * dev)622 static int bcm63xx_spi_suspend(struct device *dev) 623 { 624 struct spi_controller *host = dev_get_drvdata(dev); 625 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 626 627 spi_controller_suspend(host); 628 629 clk_disable_unprepare(bs->clk); 630 631 return 0; 632 } 633 bcm63xx_spi_resume(struct device * dev)634 static int bcm63xx_spi_resume(struct device *dev) 635 { 636 struct spi_controller *host = dev_get_drvdata(dev); 637 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 638 int ret; 639 640 ret = clk_prepare_enable(bs->clk); 641 if (ret) 642 return ret; 643 644 spi_controller_resume(host); 645 646 return 0; 647 } 648 649 static DEFINE_SIMPLE_DEV_PM_OPS(bcm63xx_spi_pm_ops, bcm63xx_spi_suspend, bcm63xx_spi_resume); 650 651 static struct platform_driver bcm63xx_spi_driver = { 652 .driver = { 653 .name = "bcm63xx-spi", 654 .pm = &bcm63xx_spi_pm_ops, 655 .of_match_table = bcm63xx_spi_of_match, 656 }, 657 .id_table = bcm63xx_spi_dev_match, 658 .probe = bcm63xx_spi_probe, 659 .remove_new = bcm63xx_spi_remove, 660 }; 661 662 module_platform_driver(bcm63xx_spi_driver); 663 664 MODULE_ALIAS("platform:bcm63xx_spi"); 665 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 666 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); 667 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); 668 MODULE_LICENSE("GPL"); 669