xref: /openbmc/linux/sound/soc/codecs/wcd934x.c (revision 798590cc)
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3 
4 #include <linux/clk.h>
5 #include <linux/clk-provider.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel.h>
8 #include <linux/mfd/wcd934x/registers.h>
9 #include <linux/mfd/wcd934x/wcd934x.h>
10 #include <linux/module.h>
11 #include <linux/mutex.h>
12 #include <linux/of_clk.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18 #include <linux/slimbus.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/soc-dapm.h>
22 #include <sound/tlv.h>
23 #include "wcd-clsh-v2.h"
24 #include "wcd-mbhc-v2.h"
25 
26 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
27 			    SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
28 			    SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
29 /* Fractional Rates */
30 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
31 				 SNDRV_PCM_RATE_176400)
32 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
33 				    SNDRV_PCM_FMTBIT_S24_LE)
34 
35 /* slave port water mark level
36  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
37  */
38 #define SLAVE_PORT_WATER_MARK_6BYTES	0
39 #define SLAVE_PORT_WATER_MARK_9BYTES	1
40 #define SLAVE_PORT_WATER_MARK_12BYTES	2
41 #define SLAVE_PORT_WATER_MARK_15BYTES	3
42 #define SLAVE_PORT_WATER_MARK_SHIFT	1
43 #define SLAVE_PORT_ENABLE		1
44 #define SLAVE_PORT_DISABLE		0
45 #define WCD934X_SLIM_WATER_MARK_VAL \
46 	((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
47 	 (SLAVE_PORT_ENABLE))
48 
49 #define WCD934X_SLIM_NUM_PORT_REG	3
50 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
51 #define WCD934X_SLIM_IRQ_OVERFLOW	BIT(0)
52 #define WCD934X_SLIM_IRQ_UNDERFLOW	BIT(1)
53 #define WCD934X_SLIM_IRQ_PORT_CLOSED	BIT(2)
54 
55 #define WCD934X_MCLK_CLK_12P288MHZ	12288000
56 #define WCD934X_MCLK_CLK_9P6MHZ		9600000
57 
58 /* Only valid for 9.6 MHz mclk */
59 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
60 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
61 
62 /* Only valid for 12.288 MHz mclk */
63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
64 
65 #define WCD934X_DMIC_CLK_DIV_2		0x0
66 #define WCD934X_DMIC_CLK_DIV_3		0x1
67 #define WCD934X_DMIC_CLK_DIV_4		0x2
68 #define WCD934X_DMIC_CLK_DIV_6		0x3
69 #define WCD934X_DMIC_CLK_DIV_8		0x4
70 #define WCD934X_DMIC_CLK_DIV_16		0x5
71 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
72 
73 #define TX_HPF_CUT_OFF_FREQ_MASK	0x60
74 #define CF_MIN_3DB_4HZ			0x0
75 #define CF_MIN_3DB_75HZ			0x1
76 #define CF_MIN_3DB_150HZ		0x2
77 
78 #define WCD934X_RX_START		16
79 #define WCD934X_NUM_INTERPOLATORS	9
80 #define WCD934X_RX_PATH_CTL_OFFSET	20
81 #define WCD934X_MAX_VALID_ADC_MUX	13
82 #define WCD934X_INVALID_ADC_MUX		9
83 
84 #define WCD934X_SLIM_RX_CH(p) \
85 	{.port = p + WCD934X_RX_START, .shift = p,}
86 
87 #define WCD934X_SLIM_TX_CH(p) \
88 	{.port = p, .shift = p,}
89 
90 /* Feature masks to distinguish codec version */
91 #define DSD_DISABLED_MASK   0
92 #define SLNQ_DISABLED_MASK  1
93 
94 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
95 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
96 
97 /* As fine version info cannot be retrieved before wcd probe.
98  * Define three coarse versions for possible future use before wcd probe.
99  */
100 #define WCD_VERSION_WCD9340_1_0     0x400
101 #define WCD_VERSION_WCD9341_1_0     0x410
102 #define WCD_VERSION_WCD9340_1_1     0x401
103 #define WCD_VERSION_WCD9341_1_1     0x411
104 #define WCD934X_AMIC_PWR_LEVEL_LP	0
105 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT	1
106 #define WCD934X_AMIC_PWR_LEVEL_HP	2
107 #define WCD934X_AMIC_PWR_LEVEL_HYBRID	3
108 #define WCD934X_AMIC_PWR_LVL_MASK	0x60
109 #define WCD934X_AMIC_PWR_LVL_SHIFT	0x5
110 
111 #define WCD934X_DEC_PWR_LVL_MASK	0x06
112 #define WCD934X_DEC_PWR_LVL_LP		0x02
113 #define WCD934X_DEC_PWR_LVL_HP		0x04
114 #define WCD934X_DEC_PWR_LVL_DF		0x00
115 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
116 
117 #define WCD934X_DEF_MICBIAS_MV	1800
118 #define WCD934X_MAX_MICBIAS_MV	2850
119 
120 #define WCD_IIR_FILTER_SIZE	(sizeof(u32) * BAND_MAX)
121 
122 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
123 { \
124 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
125 	.info = wcd934x_iir_filter_info, \
126 	.get = wcd934x_get_iir_band_audio_mixer, \
127 	.put = wcd934x_put_iir_band_audio_mixer, \
128 	.private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
129 		.iir_idx = iidx, \
130 		.band_idx = bidx, \
131 		.bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
132 	} \
133 }
134 
135 /* Z value defined in milliohm */
136 #define WCD934X_ZDET_VAL_32             32000
137 #define WCD934X_ZDET_VAL_400            400000
138 #define WCD934X_ZDET_VAL_1200           1200000
139 #define WCD934X_ZDET_VAL_100K           100000000
140 /* Z floating defined in ohms */
141 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
142 
143 #define WCD934X_ZDET_NUM_MEASUREMENTS   900
144 #define WCD934X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
145 #define WCD934X_MBHC_GET_X1(x)          (x & 0x3FFF)
146 /* Z value compared in milliOhm */
147 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
148 #define WCD934X_MBHC_ZDET_CONST         (86 * 16384)
149 #define WCD934X_MBHC_MOISTURE_RREF      R_24_KOHM
150 #define WCD934X_MBHC_MAX_BUTTONS	(8)
151 #define WCD_MBHC_HS_V_MAX           1600
152 
153 #define WCD934X_INTERPOLATOR_PATH(id)			\
154 	{"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},	\
155 	{"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},	\
156 	{"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},	\
157 	{"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},	\
158 	{"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},	\
159 	{"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},	\
160 	{"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},	\
161 	{"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},	\
162 	{"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"},	\
163 	{"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"},	\
164 	{"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},	\
165 	{"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},	\
166 	{"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},	\
167 	{"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},	\
168 	{"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},	\
169 	{"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},	\
170 	{"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},	\
171 	{"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},	\
172 	{"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"},	\
173 	{"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"},	\
174 	{"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},	\
175 	{"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},	\
176 	{"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},	\
177 	{"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},	\
178 	{"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},	\
179 	{"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},	\
180 	{"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},	\
181 	{"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},	\
182 	{"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"},		\
183 	{"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"},		\
184 	{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
185 	{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
186 	{"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
187 	{"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},	\
188 	{"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},	\
189 	{"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},	\
190 	{"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},	\
191 	{"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},	\
192 	{"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},	\
193 	{"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},	\
194 	{"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},	\
195 	{"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
196 	{"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
197 	{"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"},	\
198 	{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"},	\
199 	{"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"},	\
200 	{"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"},	\
201 	{"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"},	\
202 	{"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
203 
204 #define WCD934X_INTERPOLATOR_MIX2(id)			\
205 	{"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
206 	{"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
207 
208 #define WCD934X_SLIM_RX_AIF_PATH(id)	\
209 	{"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"},	\
210 	{"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"},	\
211 	{"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"},	\
212 	{"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"},   \
213 	{"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
214 
215 #define WCD934X_ADC_MUX(id) \
216 	{"ADC MUX" #id, "DMIC", "DMIC MUX" #id },	\
217 	{"ADC MUX" #id, "AMIC", "AMIC MUX" #id },	\
218 	{"DMIC MUX" #id, "DMIC0", "DMIC0"},		\
219 	{"DMIC MUX" #id, "DMIC1", "DMIC1"},		\
220 	{"DMIC MUX" #id, "DMIC2", "DMIC2"},		\
221 	{"DMIC MUX" #id, "DMIC3", "DMIC3"},		\
222 	{"DMIC MUX" #id, "DMIC4", "DMIC4"},		\
223 	{"DMIC MUX" #id, "DMIC5", "DMIC5"},		\
224 	{"AMIC MUX" #id, "ADC1", "ADC1"},		\
225 	{"AMIC MUX" #id, "ADC2", "ADC2"},		\
226 	{"AMIC MUX" #id, "ADC3", "ADC3"},		\
227 	{"AMIC MUX" #id, "ADC4", "ADC4"}
228 
229 #define WCD934X_IIR_INP_MUX(id) \
230 	{"IIR" #id, NULL, "IIR" #id " INP0 MUX"},	\
231 	{"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"},	\
232 	{"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"},	\
233 	{"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"},	\
234 	{"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"},	\
235 	{"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"},	\
236 	{"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"},	\
237 	{"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"},	\
238 	{"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"},	\
239 	{"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"},	\
240 	{"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"},	\
241 	{"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"},	\
242 	{"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"},	\
243 	{"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"},	\
244 	{"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"},	\
245 	{"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"},	\
246 	{"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"},	\
247 	{"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"},	\
248 	{"IIR" #id, NULL, "IIR" #id " INP1 MUX"},	\
249 	{"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"},	\
250 	{"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"},	\
251 	{"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"},	\
252 	{"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"},	\
253 	{"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"},	\
254 	{"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"},	\
255 	{"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"},	\
256 	{"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"},	\
257 	{"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"},	\
258 	{"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"},	\
259 	{"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"},	\
260 	{"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"},	\
261 	{"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"},	\
262 	{"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"},	\
263 	{"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"},	\
264 	{"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"},	\
265 	{"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"},	\
266 	{"IIR" #id, NULL, "IIR" #id " INP2 MUX"},	\
267 	{"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"},	\
268 	{"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"},	\
269 	{"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"},	\
270 	{"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"},	\
271 	{"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"},	\
272 	{"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"},	\
273 	{"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"},	\
274 	{"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"},	\
275 	{"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"},	\
276 	{"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"},	\
277 	{"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"},	\
278 	{"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"},	\
279 	{"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"},	\
280 	{"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"},	\
281 	{"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"},	\
282 	{"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"},	\
283 	{"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"},	\
284 	{"IIR" #id, NULL, "IIR" #id " INP3 MUX"},	\
285 	{"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"},	\
286 	{"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"},	\
287 	{"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"},	\
288 	{"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"},	\
289 	{"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"},	\
290 	{"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"},	\
291 	{"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"},	\
292 	{"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"},	\
293 	{"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"},	\
294 	{"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"},	\
295 	{"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"},	\
296 	{"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"},	\
297 	{"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"},	\
298 	{"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"},	\
299 	{"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"},	\
300 	{"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"},	\
301 	{"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
302 
303 #define WCD934X_SLIM_TX_AIF_PATH(id)	\
304 	{"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },	\
305 	{"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },	\
306 	{"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },	\
307 	{"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
308 
309 #define WCD934X_MAX_MICBIAS	MIC_BIAS_4
310 
311 enum {
312 	SIDO_SOURCE_INTERNAL,
313 	SIDO_SOURCE_RCO_BG,
314 };
315 
316 enum {
317 	INTERP_EAR = 0,
318 	INTERP_HPHL,
319 	INTERP_HPHR,
320 	INTERP_LO1,
321 	INTERP_LO2,
322 	INTERP_LO3_NA, /* LO3 not avalible in Tavil */
323 	INTERP_LO4_NA,
324 	INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
325 	INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
326 	INTERP_MAX,
327 };
328 
329 enum {
330 	WCD934X_RX0 = 0,
331 	WCD934X_RX1,
332 	WCD934X_RX2,
333 	WCD934X_RX3,
334 	WCD934X_RX4,
335 	WCD934X_RX5,
336 	WCD934X_RX6,
337 	WCD934X_RX7,
338 	WCD934X_RX8,
339 	WCD934X_RX9,
340 	WCD934X_RX10,
341 	WCD934X_RX11,
342 	WCD934X_RX12,
343 	WCD934X_RX_MAX,
344 };
345 
346 enum {
347 	WCD934X_TX0 = 0,
348 	WCD934X_TX1,
349 	WCD934X_TX2,
350 	WCD934X_TX3,
351 	WCD934X_TX4,
352 	WCD934X_TX5,
353 	WCD934X_TX6,
354 	WCD934X_TX7,
355 	WCD934X_TX8,
356 	WCD934X_TX9,
357 	WCD934X_TX10,
358 	WCD934X_TX11,
359 	WCD934X_TX12,
360 	WCD934X_TX13,
361 	WCD934X_TX14,
362 	WCD934X_TX15,
363 	WCD934X_TX_MAX,
364 };
365 
366 struct wcd934x_slim_ch {
367 	u32 ch_num;
368 	u16 port;
369 	u16 shift;
370 	struct list_head list;
371 };
372 
373 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
374 	WCD934X_SLIM_TX_CH(0),
375 	WCD934X_SLIM_TX_CH(1),
376 	WCD934X_SLIM_TX_CH(2),
377 	WCD934X_SLIM_TX_CH(3),
378 	WCD934X_SLIM_TX_CH(4),
379 	WCD934X_SLIM_TX_CH(5),
380 	WCD934X_SLIM_TX_CH(6),
381 	WCD934X_SLIM_TX_CH(7),
382 	WCD934X_SLIM_TX_CH(8),
383 	WCD934X_SLIM_TX_CH(9),
384 	WCD934X_SLIM_TX_CH(10),
385 	WCD934X_SLIM_TX_CH(11),
386 	WCD934X_SLIM_TX_CH(12),
387 	WCD934X_SLIM_TX_CH(13),
388 	WCD934X_SLIM_TX_CH(14),
389 	WCD934X_SLIM_TX_CH(15),
390 };
391 
392 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
393 	WCD934X_SLIM_RX_CH(0),	 /* 16 */
394 	WCD934X_SLIM_RX_CH(1),	 /* 17 */
395 	WCD934X_SLIM_RX_CH(2),
396 	WCD934X_SLIM_RX_CH(3),
397 	WCD934X_SLIM_RX_CH(4),
398 	WCD934X_SLIM_RX_CH(5),
399 	WCD934X_SLIM_RX_CH(6),
400 	WCD934X_SLIM_RX_CH(7),
401 	WCD934X_SLIM_RX_CH(8),
402 	WCD934X_SLIM_RX_CH(9),
403 	WCD934X_SLIM_RX_CH(10),
404 	WCD934X_SLIM_RX_CH(11),
405 	WCD934X_SLIM_RX_CH(12),
406 };
407 
408 /* Codec supports 2 IIR filters */
409 enum {
410 	IIR0 = 0,
411 	IIR1,
412 	IIR_MAX,
413 };
414 
415 /* Each IIR has 5 Filter Stages */
416 enum {
417 	BAND1 = 0,
418 	BAND2,
419 	BAND3,
420 	BAND4,
421 	BAND5,
422 	BAND_MAX,
423 };
424 
425 enum {
426 	COMPANDER_1, /* HPH_L */
427 	COMPANDER_2, /* HPH_R */
428 	COMPANDER_3, /* LO1_DIFF */
429 	COMPANDER_4, /* LO2_DIFF */
430 	COMPANDER_5, /* LO3_SE - not used in Tavil */
431 	COMPANDER_6, /* LO4_SE - not used in Tavil */
432 	COMPANDER_7, /* SWR SPK CH1 */
433 	COMPANDER_8, /* SWR SPK CH2 */
434 	COMPANDER_MAX,
435 };
436 
437 enum {
438 	AIF1_PB = 0,
439 	AIF1_CAP,
440 	AIF2_PB,
441 	AIF2_CAP,
442 	AIF3_PB,
443 	AIF3_CAP,
444 	AIF4_PB,
445 	AIF4_VIFEED,
446 	AIF4_MAD_TX,
447 	NUM_CODEC_DAIS,
448 };
449 
450 enum {
451 	INTn_1_INP_SEL_ZERO = 0,
452 	INTn_1_INP_SEL_DEC0,
453 	INTn_1_INP_SEL_DEC1,
454 	INTn_1_INP_SEL_IIR0,
455 	INTn_1_INP_SEL_IIR1,
456 	INTn_1_INP_SEL_RX0,
457 	INTn_1_INP_SEL_RX1,
458 	INTn_1_INP_SEL_RX2,
459 	INTn_1_INP_SEL_RX3,
460 	INTn_1_INP_SEL_RX4,
461 	INTn_1_INP_SEL_RX5,
462 	INTn_1_INP_SEL_RX6,
463 	INTn_1_INP_SEL_RX7,
464 };
465 
466 enum {
467 	INTn_2_INP_SEL_ZERO = 0,
468 	INTn_2_INP_SEL_RX0,
469 	INTn_2_INP_SEL_RX1,
470 	INTn_2_INP_SEL_RX2,
471 	INTn_2_INP_SEL_RX3,
472 	INTn_2_INP_SEL_RX4,
473 	INTn_2_INP_SEL_RX5,
474 	INTn_2_INP_SEL_RX6,
475 	INTn_2_INP_SEL_RX7,
476 	INTn_2_INP_SEL_PROXIMITY,
477 };
478 
479 enum {
480 	INTERP_MAIN_PATH,
481 	INTERP_MIX_PATH,
482 };
483 
484 struct interp_sample_rate {
485 	int sample_rate;
486 	int rate_val;
487 };
488 
489 static struct interp_sample_rate sr_val_tbl[] = {
490 	{8000, 0x0},
491 	{16000, 0x1},
492 	{32000, 0x3},
493 	{48000, 0x4},
494 	{96000, 0x5},
495 	{192000, 0x6},
496 	{384000, 0x7},
497 	{44100, 0x9},
498 	{88200, 0xA},
499 	{176400, 0xB},
500 	{352800, 0xC},
501 };
502 
503 struct wcd934x_mbhc_zdet_param {
504 	u16 ldo_ctl;
505 	u16 noff;
506 	u16 nshift;
507 	u16 btn5;
508 	u16 btn6;
509 	u16 btn7;
510 };
511 
512 struct wcd_slim_codec_dai_data {
513 	struct list_head slim_ch_list;
514 	struct slim_stream_config sconfig;
515 	struct slim_stream_runtime *sruntime;
516 };
517 
518 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
519 	{
520 		.name = "WCD9335-IFC-DEV",
521 		.range_min =  0x0,
522 		.range_max = 0xffff,
523 		.selector_reg = 0x800,
524 		.selector_mask = 0xfff,
525 		.selector_shift = 0,
526 		.window_start = 0x800,
527 		.window_len = 0x400,
528 	},
529 };
530 
531 static struct regmap_config wcd934x_ifc_regmap_config = {
532 	.reg_bits = 16,
533 	.val_bits = 8,
534 	.max_register = 0xffff,
535 	.ranges = wcd934x_ifc_ranges,
536 	.num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
537 };
538 
539 struct wcd934x_codec {
540 	struct device *dev;
541 	struct clk_hw hw;
542 	struct clk *extclk;
543 	struct regmap *regmap;
544 	struct regmap *if_regmap;
545 	struct slim_device *sdev;
546 	struct slim_device *sidev;
547 	struct wcd_clsh_ctrl *clsh_ctrl;
548 	struct snd_soc_component *component;
549 	struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
550 	struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
551 	struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
552 	int rate;
553 	u32 version;
554 	u32 hph_mode;
555 	int num_rx_port;
556 	int num_tx_port;
557 	u32 tx_port_value[WCD934X_TX_MAX];
558 	u32 rx_port_value[WCD934X_RX_MAX];
559 	int sido_input_src;
560 	int dmic_0_1_clk_cnt;
561 	int dmic_2_3_clk_cnt;
562 	int dmic_4_5_clk_cnt;
563 	int dmic_sample_rate;
564 	int comp_enabled[COMPANDER_MAX];
565 	int sysclk_users;
566 	struct mutex sysclk_mutex;
567 	/* mbhc module */
568 	struct wcd_mbhc *mbhc;
569 	struct wcd_mbhc_config mbhc_cfg;
570 	struct wcd_mbhc_intr intr_ids;
571 	bool mbhc_started;
572 	struct mutex micb_lock;
573 	u32 micb_ref[WCD934X_MAX_MICBIAS];
574 	u32 pullup_ref[WCD934X_MAX_MICBIAS];
575 	u32 micb1_mv;
576 	u32 micb2_mv;
577 	u32 micb3_mv;
578 	u32 micb4_mv;
579 };
580 
581 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
582 
583 struct wcd_iir_filter_ctl {
584 	unsigned int iir_idx;
585 	unsigned int band_idx;
586 	struct soc_bytes_ext bytes_ext;
587 };
588 
589 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
590 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
591 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
592 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
593 
594 /* Cutoff frequency for high pass filter */
595 static const char * const cf_text[] = {
596 	"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
597 };
598 
599 static const char * const rx_cf_text[] = {
600 	"CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
601 	"CF_NEG_3DB_0P48HZ"
602 };
603 
604 static const char * const rx_hph_mode_mux_text[] = {
605 	"Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
606 	"Class-H Hi-Fi Low Power"
607 };
608 
609 static const char *const slim_rx_mux_text[] = {
610 	"ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
611 };
612 
613 static const char * const rx_int0_7_mix_mux_text[] = {
614 	"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
615 	"RX6", "RX7", "PROXIMITY"
616 };
617 
618 static const char * const rx_int_mix_mux_text[] = {
619 	"ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
620 	"RX6", "RX7"
621 };
622 
623 static const char * const rx_prim_mix_text[] = {
624 	"ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
625 	"RX3", "RX4", "RX5", "RX6", "RX7"
626 };
627 
628 static const char * const rx_sidetone_mix_text[] = {
629 	"ZERO", "SRC0", "SRC1", "SRC_SUM"
630 };
631 
632 static const char * const iir_inp_mux_text[] = {
633 	"ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
634 	"DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
635 };
636 
637 static const char * const rx_int_dem_inp_mux_text[] = {
638 	"NORMAL_DSM_OUT", "CLSH_DSM_OUT",
639 };
640 
641 static const char * const rx_int0_1_interp_mux_text[] = {
642 	"ZERO", "RX INT0_1 MIX1",
643 };
644 
645 static const char * const rx_int1_1_interp_mux_text[] = {
646 	"ZERO", "RX INT1_1 MIX1",
647 };
648 
649 static const char * const rx_int2_1_interp_mux_text[] = {
650 	"ZERO", "RX INT2_1 MIX1",
651 };
652 
653 static const char * const rx_int3_1_interp_mux_text[] = {
654 	"ZERO", "RX INT3_1 MIX1",
655 };
656 
657 static const char * const rx_int4_1_interp_mux_text[] = {
658 	"ZERO", "RX INT4_1 MIX1",
659 };
660 
661 static const char * const rx_int7_1_interp_mux_text[] = {
662 	"ZERO", "RX INT7_1 MIX1",
663 };
664 
665 static const char * const rx_int8_1_interp_mux_text[] = {
666 	"ZERO", "RX INT8_1 MIX1",
667 };
668 
669 static const char * const rx_int0_2_interp_mux_text[] = {
670 	"ZERO", "RX INT0_2 MUX",
671 };
672 
673 static const char * const rx_int1_2_interp_mux_text[] = {
674 	"ZERO", "RX INT1_2 MUX",
675 };
676 
677 static const char * const rx_int2_2_interp_mux_text[] = {
678 	"ZERO", "RX INT2_2 MUX",
679 };
680 
681 static const char * const rx_int3_2_interp_mux_text[] = {
682 	"ZERO", "RX INT3_2 MUX",
683 };
684 
685 static const char * const rx_int4_2_interp_mux_text[] = {
686 	"ZERO", "RX INT4_2 MUX",
687 };
688 
689 static const char * const rx_int7_2_interp_mux_text[] = {
690 	"ZERO", "RX INT7_2 MUX",
691 };
692 
693 static const char * const rx_int8_2_interp_mux_text[] = {
694 	"ZERO", "RX INT8_2 MUX",
695 };
696 
697 static const char * const dmic_mux_text[] = {
698 	"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
699 };
700 
701 static const char * const amic_mux_text[] = {
702 	"ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
703 };
704 
705 static const char * const amic4_5_sel_text[] = {
706 	"AMIC4", "AMIC5"
707 };
708 
709 static const char * const adc_mux_text[] = {
710 	"DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
711 };
712 
713 static const char * const cdc_if_tx0_mux_text[] = {
714 	"ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
715 };
716 
717 static const char * const cdc_if_tx1_mux_text[] = {
718 	"ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
719 };
720 
721 static const char * const cdc_if_tx2_mux_text[] = {
722 	"ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
723 };
724 
725 static const char * const cdc_if_tx3_mux_text[] = {
726 	"ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
727 };
728 
729 static const char * const cdc_if_tx4_mux_text[] = {
730 	"ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
731 };
732 
733 static const char * const cdc_if_tx5_mux_text[] = {
734 	"ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
735 };
736 
737 static const char * const cdc_if_tx6_mux_text[] = {
738 	"ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
739 };
740 
741 static const char * const cdc_if_tx7_mux_text[] = {
742 	"ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
743 };
744 
745 static const char * const cdc_if_tx8_mux_text[] = {
746 	"ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
747 };
748 
749 static const char * const cdc_if_tx9_mux_text[] = {
750 	"ZERO", "DEC7", "DEC7_192"
751 };
752 
753 static const char * const cdc_if_tx10_mux_text[] = {
754 	"ZERO", "DEC6", "DEC6_192"
755 };
756 
757 static const char * const cdc_if_tx11_mux_text[] = {
758 	"DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
759 };
760 
761 static const char * const cdc_if_tx11_inp1_mux_text[] = {
762 	"ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
763 	"DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
764 };
765 
766 static const char * const cdc_if_tx13_mux_text[] = {
767 	"CDC_DEC_5", "MAD_BRDCST"
768 };
769 
770 static const char * const cdc_if_tx13_inp1_mux_text[] = {
771 	"ZERO", "DEC5", "DEC5_192"
772 };
773 
774 static const struct soc_enum cf_dec0_enum =
775 	SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
776 
777 static const struct soc_enum cf_dec1_enum =
778 	SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
779 
780 static const struct soc_enum cf_dec2_enum =
781 	SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
782 
783 static const struct soc_enum cf_dec3_enum =
784 	SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
785 
786 static const struct soc_enum cf_dec4_enum =
787 	SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
788 
789 static const struct soc_enum cf_dec5_enum =
790 	SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
791 
792 static const struct soc_enum cf_dec6_enum =
793 	SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
794 
795 static const struct soc_enum cf_dec7_enum =
796 	SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
797 
798 static const struct soc_enum cf_dec8_enum =
799 	SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
800 
801 static const struct soc_enum cf_int0_1_enum =
802 	SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
803 
804 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
805 		     rx_cf_text);
806 
807 static const struct soc_enum cf_int1_1_enum =
808 	SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
809 
810 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
811 		     rx_cf_text);
812 
813 static const struct soc_enum cf_int2_1_enum =
814 	SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
815 
816 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
817 		     rx_cf_text);
818 
819 static const struct soc_enum cf_int3_1_enum =
820 	SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
821 
822 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
823 			    rx_cf_text);
824 
825 static const struct soc_enum cf_int4_1_enum =
826 	SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
827 
828 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
829 			    rx_cf_text);
830 
831 static const struct soc_enum cf_int7_1_enum =
832 	SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
833 
834 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
835 			    rx_cf_text);
836 
837 static const struct soc_enum cf_int8_1_enum =
838 	SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
839 
840 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
841 			    rx_cf_text);
842 
843 static const struct soc_enum rx_hph_mode_mux_enum =
844 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
845 			    rx_hph_mode_mux_text);
846 
847 static const struct soc_enum slim_rx_mux_enum =
848 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
849 
850 static const struct soc_enum rx_int0_2_mux_chain_enum =
851 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
852 			rx_int0_7_mix_mux_text);
853 
854 static const struct soc_enum rx_int1_2_mux_chain_enum =
855 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
856 			rx_int_mix_mux_text);
857 
858 static const struct soc_enum rx_int2_2_mux_chain_enum =
859 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
860 			rx_int_mix_mux_text);
861 
862 static const struct soc_enum rx_int3_2_mux_chain_enum =
863 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
864 			rx_int_mix_mux_text);
865 
866 static const struct soc_enum rx_int4_2_mux_chain_enum =
867 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
868 			rx_int_mix_mux_text);
869 
870 static const struct soc_enum rx_int7_2_mux_chain_enum =
871 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
872 			rx_int0_7_mix_mux_text);
873 
874 static const struct soc_enum rx_int8_2_mux_chain_enum =
875 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
876 			rx_int_mix_mux_text);
877 
878 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
879 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
880 			rx_prim_mix_text);
881 
882 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
883 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
884 			rx_prim_mix_text);
885 
886 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
887 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
888 			rx_prim_mix_text);
889 
890 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
891 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
892 			rx_prim_mix_text);
893 
894 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
895 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
896 			rx_prim_mix_text);
897 
898 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
899 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
900 			rx_prim_mix_text);
901 
902 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
903 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
904 			rx_prim_mix_text);
905 
906 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
907 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
908 			rx_prim_mix_text);
909 
910 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
911 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
912 			rx_prim_mix_text);
913 
914 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
915 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
916 			rx_prim_mix_text);
917 
918 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
919 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
920 			rx_prim_mix_text);
921 
922 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
923 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
924 			rx_prim_mix_text);
925 
926 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
927 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
928 			rx_prim_mix_text);
929 
930 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
931 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
932 			rx_prim_mix_text);
933 
934 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
935 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
936 			rx_prim_mix_text);
937 
938 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
939 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
940 			rx_prim_mix_text);
941 
942 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
943 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
944 			rx_prim_mix_text);
945 
946 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
947 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
948 			rx_prim_mix_text);
949 
950 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
951 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
952 			rx_prim_mix_text);
953 
954 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
955 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
956 			rx_prim_mix_text);
957 
958 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
959 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
960 			rx_prim_mix_text);
961 
962 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
963 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
964 			rx_sidetone_mix_text);
965 
966 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
967 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
968 			rx_sidetone_mix_text);
969 
970 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
971 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
972 			rx_sidetone_mix_text);
973 
974 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
975 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
976 			rx_sidetone_mix_text);
977 
978 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
979 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
980 			rx_sidetone_mix_text);
981 
982 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
983 	SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
984 			rx_sidetone_mix_text);
985 
986 static const struct soc_enum iir0_inp0_mux_enum =
987 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
988 			0, 18, iir_inp_mux_text);
989 
990 static const struct soc_enum iir0_inp1_mux_enum =
991 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
992 			0, 18, iir_inp_mux_text);
993 
994 static const struct soc_enum iir0_inp2_mux_enum =
995 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
996 			0, 18, iir_inp_mux_text);
997 
998 static const struct soc_enum iir0_inp3_mux_enum =
999 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
1000 			0, 18, iir_inp_mux_text);
1001 
1002 static const struct soc_enum iir1_inp0_mux_enum =
1003 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
1004 			0, 18, iir_inp_mux_text);
1005 
1006 static const struct soc_enum iir1_inp1_mux_enum =
1007 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
1008 			0, 18, iir_inp_mux_text);
1009 
1010 static const struct soc_enum iir1_inp2_mux_enum =
1011 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
1012 			0, 18, iir_inp_mux_text);
1013 
1014 static const struct soc_enum iir1_inp3_mux_enum =
1015 	SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
1016 			0, 18, iir_inp_mux_text);
1017 
1018 static const struct soc_enum rx_int0_dem_inp_mux_enum =
1019 	SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
1020 			ARRAY_SIZE(rx_int_dem_inp_mux_text),
1021 			rx_int_dem_inp_mux_text);
1022 
1023 static const struct soc_enum rx_int1_dem_inp_mux_enum =
1024 	SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
1025 			ARRAY_SIZE(rx_int_dem_inp_mux_text),
1026 			rx_int_dem_inp_mux_text);
1027 
1028 static const struct soc_enum rx_int2_dem_inp_mux_enum =
1029 	SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
1030 			ARRAY_SIZE(rx_int_dem_inp_mux_text),
1031 			rx_int_dem_inp_mux_text);
1032 
1033 static const struct soc_enum tx_adc_mux0_enum =
1034 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1035 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1036 static const struct soc_enum tx_adc_mux1_enum =
1037 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1038 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1039 static const struct soc_enum tx_adc_mux2_enum =
1040 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1041 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1042 static const struct soc_enum tx_adc_mux3_enum =
1043 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1044 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1045 static const struct soc_enum tx_adc_mux4_enum =
1046 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1047 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1048 static const struct soc_enum tx_adc_mux5_enum =
1049 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1050 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1051 static const struct soc_enum tx_adc_mux6_enum =
1052 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1053 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1054 static const struct soc_enum tx_adc_mux7_enum =
1055 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1056 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1057 static const struct soc_enum tx_adc_mux8_enum =
1058 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1059 			ARRAY_SIZE(adc_mux_text), adc_mux_text);
1060 
1061 static const struct soc_enum rx_int0_1_interp_mux_enum =
1062 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2,
1063 			rx_int0_1_interp_mux_text);
1064 
1065 static const struct soc_enum rx_int1_1_interp_mux_enum =
1066 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2,
1067 			rx_int1_1_interp_mux_text);
1068 
1069 static const struct soc_enum rx_int2_1_interp_mux_enum =
1070 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2,
1071 			rx_int2_1_interp_mux_text);
1072 
1073 static const struct soc_enum rx_int3_1_interp_mux_enum =
1074 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int3_1_interp_mux_text);
1075 
1076 static const struct soc_enum rx_int4_1_interp_mux_enum =
1077 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int4_1_interp_mux_text);
1078 
1079 static const struct soc_enum rx_int7_1_interp_mux_enum =
1080 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int7_1_interp_mux_text);
1081 
1082 static const struct soc_enum rx_int8_1_interp_mux_enum =
1083 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int8_1_interp_mux_text);
1084 
1085 static const struct soc_enum rx_int0_2_interp_mux_enum =
1086 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int0_2_interp_mux_text);
1087 
1088 static const struct soc_enum rx_int1_2_interp_mux_enum =
1089 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int1_2_interp_mux_text);
1090 
1091 static const struct soc_enum rx_int2_2_interp_mux_enum =
1092 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int2_2_interp_mux_text);
1093 
1094 static const struct soc_enum rx_int3_2_interp_mux_enum =
1095 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int3_2_interp_mux_text);
1096 
1097 static const struct soc_enum rx_int4_2_interp_mux_enum =
1098 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int4_2_interp_mux_text);
1099 
1100 static const struct soc_enum rx_int7_2_interp_mux_enum =
1101 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int7_2_interp_mux_text);
1102 
1103 static const struct soc_enum rx_int8_2_interp_mux_enum =
1104 	SOC_ENUM_SINGLE(SND_SOC_NOPM,	0, 2, rx_int8_2_interp_mux_text);
1105 
1106 static const struct soc_enum tx_dmic_mux0_enum =
1107 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1108 			dmic_mux_text);
1109 
1110 static const struct soc_enum tx_dmic_mux1_enum =
1111 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1112 			dmic_mux_text);
1113 
1114 static const struct soc_enum tx_dmic_mux2_enum =
1115 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1116 			dmic_mux_text);
1117 
1118 static const struct soc_enum tx_dmic_mux3_enum =
1119 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1120 			dmic_mux_text);
1121 
1122 static const struct soc_enum tx_dmic_mux4_enum =
1123 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1124 			dmic_mux_text);
1125 
1126 static const struct soc_enum tx_dmic_mux5_enum =
1127 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1128 			dmic_mux_text);
1129 
1130 static const struct soc_enum tx_dmic_mux6_enum =
1131 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1132 			dmic_mux_text);
1133 
1134 static const struct soc_enum tx_dmic_mux7_enum =
1135 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1136 			dmic_mux_text);
1137 
1138 static const struct soc_enum tx_dmic_mux8_enum =
1139 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1140 			dmic_mux_text);
1141 
1142 static const struct soc_enum tx_amic_mux0_enum =
1143 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1144 			amic_mux_text);
1145 static const struct soc_enum tx_amic_mux1_enum =
1146 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1147 			amic_mux_text);
1148 static const struct soc_enum tx_amic_mux2_enum =
1149 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1150 			amic_mux_text);
1151 static const struct soc_enum tx_amic_mux3_enum =
1152 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1153 			amic_mux_text);
1154 static const struct soc_enum tx_amic_mux4_enum =
1155 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1156 			amic_mux_text);
1157 static const struct soc_enum tx_amic_mux5_enum =
1158 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1159 			amic_mux_text);
1160 static const struct soc_enum tx_amic_mux6_enum =
1161 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1162 			amic_mux_text);
1163 static const struct soc_enum tx_amic_mux7_enum =
1164 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1165 			amic_mux_text);
1166 static const struct soc_enum tx_amic_mux8_enum =
1167 	SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1168 			amic_mux_text);
1169 
1170 static const struct soc_enum tx_amic4_5_enum =
1171 	SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1172 
1173 static const struct soc_enum cdc_if_tx0_mux_enum =
1174 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1175 			ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1176 static const struct soc_enum cdc_if_tx1_mux_enum =
1177 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1178 			ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1179 static const struct soc_enum cdc_if_tx2_mux_enum =
1180 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1181 			ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1182 static const struct soc_enum cdc_if_tx3_mux_enum =
1183 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1184 			ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1185 static const struct soc_enum cdc_if_tx4_mux_enum =
1186 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1187 			ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1188 static const struct soc_enum cdc_if_tx5_mux_enum =
1189 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1190 			ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1191 static const struct soc_enum cdc_if_tx6_mux_enum =
1192 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1193 			ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1194 static const struct soc_enum cdc_if_tx7_mux_enum =
1195 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1196 			ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1197 static const struct soc_enum cdc_if_tx8_mux_enum =
1198 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1199 			ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1200 static const struct soc_enum cdc_if_tx9_mux_enum =
1201 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1202 			ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1203 static const struct soc_enum cdc_if_tx10_mux_enum =
1204 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1205 			ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1206 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1207 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1208 			ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1209 			cdc_if_tx11_inp1_mux_text);
1210 static const struct soc_enum cdc_if_tx11_mux_enum =
1211 	SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1212 			ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1213 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1214 	SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1215 			ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1216 			cdc_if_tx13_inp1_mux_text);
1217 static const struct soc_enum cdc_if_tx13_mux_enum =
1218 	SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1219 			ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1220 
1221 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
1222 	WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80),
1223 	WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40),
1224 	WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20),
1225 	WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
1226 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08),
1227 	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0),
1228 	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04),
1229 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10),
1230 	WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08),
1231 	WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01),
1232 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06),
1233 	WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80),
1234 	WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
1235 	WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03),
1236 	WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03),
1237 	WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08),
1238 	WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1239 	WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20),
1240 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80),
1241 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40),
1242 	WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10),
1243 	WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07),
1244 	WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70),
1245 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF),
1246 	WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0),
1247 	WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF),
1248 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40),
1249 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80),
1250 	WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0),
1251 	WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1252 	WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02),
1253 	WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01),
1254 	WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70),
1255 	WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20),
1256 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40),
1257 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10),
1258 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01),
1259 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01),
1260 	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04),
1261 	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08),
1262 	WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08),
1263 	WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40),
1264 	WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80),
1265 	WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF),
1266 	WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F),
1267 	WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10),
1268 	WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04),
1269 	WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02),
1270 };
1271 
wcd934x_set_sido_input_src(struct wcd934x_codec * wcd,int sido_src)1272 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1273 {
1274 	if (sido_src == wcd->sido_input_src)
1275 		return 0;
1276 
1277 	if (sido_src == SIDO_SOURCE_RCO_BG) {
1278 		regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1279 				   WCD934X_ANA_RCO_BG_EN_MASK,
1280 				   WCD934X_ANA_RCO_BG_ENABLE);
1281 		usleep_range(100, 110);
1282 	}
1283 	wcd->sido_input_src = sido_src;
1284 
1285 	return 0;
1286 }
1287 
wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec * wcd)1288 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1289 {
1290 	mutex_lock(&wcd->sysclk_mutex);
1291 
1292 	if (++wcd->sysclk_users != 1) {
1293 		mutex_unlock(&wcd->sysclk_mutex);
1294 		return 0;
1295 	}
1296 	mutex_unlock(&wcd->sysclk_mutex);
1297 
1298 	regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1299 			   WCD934X_ANA_BIAS_EN_MASK,
1300 			   WCD934X_ANA_BIAS_EN);
1301 	regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1302 			   WCD934X_ANA_PRECHRG_EN_MASK,
1303 			   WCD934X_ANA_PRECHRG_EN);
1304 	/*
1305 	 * 1ms delay is required after pre-charge is enabled
1306 	 * as per HW requirement
1307 	 */
1308 	usleep_range(1000, 1100);
1309 	regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1310 			   WCD934X_ANA_PRECHRG_EN_MASK, 0);
1311 	regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1312 			   WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1313 
1314 	/*
1315 	 * In data clock contrl register is changed
1316 	 * to CLK_SYS_MCLK_PRG
1317 	 */
1318 
1319 	regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1320 			   WCD934X_EXT_CLK_BUF_EN_MASK,
1321 			   WCD934X_EXT_CLK_BUF_EN);
1322 	regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1323 			   WCD934X_EXT_CLK_DIV_RATIO_MASK,
1324 			   WCD934X_EXT_CLK_DIV_BY_2);
1325 	regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1326 			   WCD934X_MCLK_SRC_MASK,
1327 			   WCD934X_MCLK_SRC_EXT_CLK);
1328 	regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1329 			   WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1330 	regmap_update_bits(wcd->regmap,
1331 			   WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1332 			   WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1333 			   WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1334 	regmap_update_bits(wcd->regmap,
1335 			   WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1336 			   WCD934X_MCLK_EN_MASK,
1337 			   WCD934X_MCLK_EN);
1338 	regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1339 			   WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1340 	/*
1341 	 * 10us sleep is required after clock is enabled
1342 	 * as per HW requirement
1343 	 */
1344 	usleep_range(10, 15);
1345 
1346 	wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1347 
1348 	return 0;
1349 }
1350 
wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec * wcd)1351 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1352 {
1353 	mutex_lock(&wcd->sysclk_mutex);
1354 	if (--wcd->sysclk_users != 0) {
1355 		mutex_unlock(&wcd->sysclk_mutex);
1356 		return 0;
1357 	}
1358 	mutex_unlock(&wcd->sysclk_mutex);
1359 
1360 	regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1361 			   WCD934X_EXT_CLK_BUF_EN_MASK |
1362 			   WCD934X_MCLK_EN_MASK, 0x0);
1363 	regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1364 			   WCD934X_ANA_BIAS_EN_MASK, 0);
1365 	regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1366 			   WCD934X_ANA_PRECHRG_EN_MASK, 0);
1367 
1368 	return 0;
1369 }
1370 
__wcd934x_cdc_mclk_enable(struct wcd934x_codec * wcd,bool enable)1371 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1372 {
1373 	int ret = 0;
1374 
1375 	if (enable) {
1376 		ret = clk_prepare_enable(wcd->extclk);
1377 
1378 		if (ret) {
1379 			dev_err(wcd->dev, "%s: ext clk enable failed\n",
1380 				__func__);
1381 			return ret;
1382 		}
1383 		ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1384 	} else {
1385 		int val;
1386 
1387 		regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1388 			    &val);
1389 
1390 		/* Don't disable clock if soundwire using it.*/
1391 		if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1392 			return 0;
1393 
1394 		wcd934x_disable_ana_bias_and_syclk(wcd);
1395 		clk_disable_unprepare(wcd->extclk);
1396 	}
1397 
1398 	return ret;
1399 }
1400 
wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)1401 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1402 				     struct snd_kcontrol *kc, int event)
1403 {
1404 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1405 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1406 
1407 	switch (event) {
1408 	case SND_SOC_DAPM_PRE_PMU:
1409 		return __wcd934x_cdc_mclk_enable(wcd, true);
1410 	case SND_SOC_DAPM_POST_PMD:
1411 		return __wcd934x_cdc_mclk_enable(wcd, false);
1412 	}
1413 
1414 	return 0;
1415 }
1416 
wcd934x_get_version(struct wcd934x_codec * wcd)1417 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1418 {
1419 	int val1, val2, ver, ret;
1420 	struct regmap *regmap;
1421 	u16 id_minor;
1422 	u32 version_mask = 0;
1423 
1424 	regmap = wcd->regmap;
1425 	ver = 0;
1426 
1427 	ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1428 			       (u8 *)&id_minor, sizeof(u16));
1429 
1430 	if (ret)
1431 		return ret;
1432 
1433 	regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1434 	regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1435 
1436 	version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1437 	version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1438 
1439 	switch (version_mask) {
1440 	case DSD_DISABLED | SLNQ_DISABLED:
1441 		if (id_minor == 0)
1442 			ver = WCD_VERSION_WCD9340_1_0;
1443 		else if (id_minor == 0x01)
1444 			ver = WCD_VERSION_WCD9340_1_1;
1445 		break;
1446 	case SLNQ_DISABLED:
1447 		if (id_minor == 0)
1448 			ver = WCD_VERSION_WCD9341_1_0;
1449 		else if (id_minor == 0x01)
1450 			ver = WCD_VERSION_WCD9341_1_1;
1451 		break;
1452 	}
1453 
1454 	wcd->version = ver;
1455 	dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1456 
1457 	return 0;
1458 }
1459 
wcd934x_enable_efuse_sensing(struct wcd934x_codec * wcd)1460 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1461 {
1462 	int rc, val;
1463 
1464 	__wcd934x_cdc_mclk_enable(wcd, true);
1465 
1466 	regmap_update_bits(wcd->regmap,
1467 			   WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1468 			   WCD934X_EFUSE_SENSE_STATE_MASK,
1469 			   WCD934X_EFUSE_SENSE_STATE_DEF);
1470 	regmap_update_bits(wcd->regmap,
1471 			   WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1472 			   WCD934X_EFUSE_SENSE_EN_MASK,
1473 			   WCD934X_EFUSE_SENSE_ENABLE);
1474 	/*
1475 	 * 5ms sleep required after enabling efuse control
1476 	 * before checking the status.
1477 	 */
1478 	usleep_range(5000, 5500);
1479 	wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1480 
1481 	rc = regmap_read(wcd->regmap,
1482 			 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1483 	if (rc || (!(val & 0x01)))
1484 		WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1485 		     __func__, val, rc);
1486 
1487 	__wcd934x_cdc_mclk_enable(wcd, false);
1488 }
1489 
wcd934x_swrm_clock(struct wcd934x_codec * wcd,bool enable)1490 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1491 {
1492 	if (enable) {
1493 		__wcd934x_cdc_mclk_enable(wcd, true);
1494 		regmap_update_bits(wcd->regmap,
1495 				   WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1496 				   WCD934X_CDC_SWR_CLK_EN_MASK,
1497 				   WCD934X_CDC_SWR_CLK_ENABLE);
1498 	} else {
1499 		regmap_update_bits(wcd->regmap,
1500 				   WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1501 				   WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1502 		__wcd934x_cdc_mclk_enable(wcd, false);
1503 	}
1504 
1505 	return 0;
1506 }
1507 
wcd934x_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1508 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1509 					      u8 rate_val, u32 rate)
1510 {
1511 	struct snd_soc_component *comp = dai->component;
1512 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1513 	struct wcd934x_slim_ch *ch;
1514 	u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1515 	int inp, j;
1516 
1517 	list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1518 		inp = ch->shift + INTn_1_INP_SEL_RX0;
1519 		/*
1520 		 * Loop through all interpolator MUX inputs and find out
1521 		 * to which interpolator input, the slim rx port
1522 		 * is connected
1523 		 */
1524 		for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1525 			/* Interpolators 5 and 6 are not aviliable in Tavil */
1526 			if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1527 				continue;
1528 
1529 			cfg0 = snd_soc_component_read(comp,
1530 					WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1531 			cfg1 = snd_soc_component_read(comp,
1532 					WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1533 
1534 			inp0_sel = cfg0 &
1535 				 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1536 			inp1_sel = (cfg0 >> 4) &
1537 				 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1538 			inp2_sel = (cfg1 >> 4) &
1539 				 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1540 
1541 			if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1542 			    (inp2_sel == inp)) {
1543 				/* rate is in Hz */
1544 				/*
1545 				 * Ear and speaker primary path does not support
1546 				 * native sample rates
1547 				 */
1548 				if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1549 				     j == INTERP_SPKR2) && rate == 44100)
1550 					dev_err(wcd->dev,
1551 						"Cannot set 44.1KHz on INT%d\n",
1552 						j);
1553 				else
1554 					snd_soc_component_update_bits(comp,
1555 					      WCD934X_CDC_RX_PATH_CTL(j),
1556 					      WCD934X_CDC_MIX_PCM_RATE_MASK,
1557 					      rate_val);
1558 			}
1559 		}
1560 	}
1561 
1562 	return 0;
1563 }
1564 
wcd934x_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1565 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1566 					     int rate_val, u32 rate)
1567 {
1568 	struct snd_soc_component *component = dai->component;
1569 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1570 	struct wcd934x_slim_ch *ch;
1571 	int val, j;
1572 
1573 	list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1574 		for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1575 			/* Interpolators 5 and 6 are not aviliable in Tavil */
1576 			if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1577 				continue;
1578 			val = snd_soc_component_read(component,
1579 					WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1580 					WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1581 
1582 			if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1583 				/*
1584 				 * Ear mix path supports only 48, 96, 192,
1585 				 * 384KHz only
1586 				 */
1587 				if ((j == INTERP_EAR) &&
1588 				    (rate_val < 0x4 ||
1589 				     rate_val > 0x7)) {
1590 					dev_err(component->dev,
1591 						"Invalid rate for AIF_PB DAI(%d)\n",
1592 						dai->id);
1593 					return -EINVAL;
1594 				}
1595 
1596 				snd_soc_component_update_bits(component,
1597 					      WCD934X_CDC_RX_PATH_MIX_CTL(j),
1598 					      WCD934X_CDC_MIX_PCM_RATE_MASK,
1599 					      rate_val);
1600 			}
1601 		}
1602 	}
1603 
1604 	return 0;
1605 }
1606 
wcd934x_set_interpolator_rate(struct snd_soc_dai * dai,u32 sample_rate)1607 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1608 					 u32 sample_rate)
1609 {
1610 	int rate_val = 0;
1611 	int i, ret;
1612 
1613 	for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1614 		if (sample_rate == sr_val_tbl[i].sample_rate) {
1615 			rate_val = sr_val_tbl[i].rate_val;
1616 			break;
1617 		}
1618 	}
1619 	if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1620 		dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1621 		return -EINVAL;
1622 	}
1623 
1624 	ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1625 						 sample_rate);
1626 	if (ret)
1627 		return ret;
1628 	ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1629 						sample_rate);
1630 
1631 	return ret;
1632 }
1633 
wcd934x_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1634 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1635 				      u8 rate_val, u32 rate)
1636 {
1637 	struct snd_soc_component *comp = dai->component;
1638 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1639 	u8 shift = 0, shift_val = 0, tx_mux_sel;
1640 	struct wcd934x_slim_ch *ch;
1641 	int tx_port, tx_port_reg;
1642 	int decimator = -1;
1643 
1644 	list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1645 		tx_port = ch->port;
1646 		/* Find the SB TX MUX input - which decimator is connected */
1647 		switch (tx_port) {
1648 		case 0 ...  3:
1649 			tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1650 			shift = (tx_port << 1);
1651 			shift_val = 0x03;
1652 			break;
1653 		case 4 ... 7:
1654 			tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1655 			shift = ((tx_port - 4) << 1);
1656 			shift_val = 0x03;
1657 			break;
1658 		case 8 ... 10:
1659 			tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1660 			shift = ((tx_port - 8) << 1);
1661 			shift_val = 0x03;
1662 			break;
1663 		case 11:
1664 			tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1665 			shift = 0;
1666 			shift_val = 0x0F;
1667 			break;
1668 		case 13:
1669 			tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1670 			shift = 4;
1671 			shift_val = 0x03;
1672 			break;
1673 		default:
1674 			dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1675 				tx_port, dai->id);
1676 			return -EINVAL;
1677 		}
1678 
1679 		tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1680 						      (shift_val << shift);
1681 
1682 		tx_mux_sel = tx_mux_sel >> shift;
1683 		switch (tx_port) {
1684 		case 0 ... 8:
1685 			if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1686 				decimator = tx_port;
1687 			break;
1688 		case 9 ... 10:
1689 			if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1690 				decimator = ((tx_port == 9) ? 7 : 6);
1691 			break;
1692 		case 11:
1693 			if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1694 				decimator = tx_mux_sel - 1;
1695 			break;
1696 		case 13:
1697 			if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1698 				decimator = 5;
1699 			break;
1700 		default:
1701 			dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1702 				tx_port);
1703 			return -EINVAL;
1704 		}
1705 
1706 		snd_soc_component_update_bits(comp,
1707 				      WCD934X_CDC_TX_PATH_CTL(decimator),
1708 				      WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1709 				      rate_val);
1710 	}
1711 
1712 	return 0;
1713 }
1714 
wcd934x_slim_set_hw_params(struct wcd934x_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1715 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1716 				      struct wcd_slim_codec_dai_data *dai_data,
1717 				      int direction)
1718 {
1719 	struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1720 	struct slim_stream_config *cfg = &dai_data->sconfig;
1721 	struct wcd934x_slim_ch *ch;
1722 	u16 payload = 0;
1723 	int ret, i;
1724 
1725 	cfg->ch_count = 0;
1726 	cfg->direction = direction;
1727 	cfg->port_mask = 0;
1728 
1729 	/* Configure slave interface device */
1730 	list_for_each_entry(ch, slim_ch_list, list) {
1731 		cfg->ch_count++;
1732 		payload |= 1 << ch->shift;
1733 		cfg->port_mask |= BIT(ch->port);
1734 	}
1735 
1736 	cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1737 	if (!cfg->chs)
1738 		return -ENOMEM;
1739 
1740 	i = 0;
1741 	list_for_each_entry(ch, slim_ch_list, list) {
1742 		cfg->chs[i++] = ch->ch_num;
1743 		if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1744 			/* write to interface device */
1745 			ret = regmap_write(wcd->if_regmap,
1746 			   WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1747 			   payload);
1748 
1749 			if (ret < 0)
1750 				goto err;
1751 
1752 			/* configure the slave port for water mark and enable*/
1753 			ret = regmap_write(wcd->if_regmap,
1754 					WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1755 					WCD934X_SLIM_WATER_MARK_VAL);
1756 			if (ret < 0)
1757 				goto err;
1758 		} else {
1759 			ret = regmap_write(wcd->if_regmap,
1760 				WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1761 				payload & 0x00FF);
1762 			if (ret < 0)
1763 				goto err;
1764 
1765 			/* ports 8,9 */
1766 			ret = regmap_write(wcd->if_regmap,
1767 				WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1768 				(payload & 0xFF00) >> 8);
1769 			if (ret < 0)
1770 				goto err;
1771 
1772 			/* configure the slave port for water mark and enable*/
1773 			ret = regmap_write(wcd->if_regmap,
1774 					WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1775 					WCD934X_SLIM_WATER_MARK_VAL);
1776 
1777 			if (ret < 0)
1778 				goto err;
1779 		}
1780 	}
1781 
1782 	dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1783 
1784 	return 0;
1785 
1786 err:
1787 	dev_err(wcd->dev, "Error Setting slim hw params\n");
1788 	kfree(cfg->chs);
1789 	cfg->chs = NULL;
1790 
1791 	return ret;
1792 }
1793 
wcd934x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1794 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1795 			     struct snd_pcm_hw_params *params,
1796 			     struct snd_soc_dai *dai)
1797 {
1798 	struct wcd934x_codec *wcd;
1799 	int ret, tx_fs_rate = 0;
1800 
1801 	wcd = snd_soc_component_get_drvdata(dai->component);
1802 
1803 	switch (substream->stream) {
1804 	case SNDRV_PCM_STREAM_PLAYBACK:
1805 		ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1806 		if (ret) {
1807 			dev_err(wcd->dev, "cannot set sample rate: %u\n",
1808 				params_rate(params));
1809 			return ret;
1810 		}
1811 		switch (params_width(params)) {
1812 		case 16 ... 24:
1813 			wcd->dai[dai->id].sconfig.bps = params_width(params);
1814 			break;
1815 		default:
1816 			dev_err(wcd->dev, "Invalid format 0x%x\n",
1817 				params_width(params));
1818 			return -EINVAL;
1819 		}
1820 		break;
1821 
1822 	case SNDRV_PCM_STREAM_CAPTURE:
1823 		switch (params_rate(params)) {
1824 		case 8000:
1825 			tx_fs_rate = 0;
1826 			break;
1827 		case 16000:
1828 			tx_fs_rate = 1;
1829 			break;
1830 		case 32000:
1831 			tx_fs_rate = 3;
1832 			break;
1833 		case 48000:
1834 			tx_fs_rate = 4;
1835 			break;
1836 		case 96000:
1837 			tx_fs_rate = 5;
1838 			break;
1839 		case 192000:
1840 			tx_fs_rate = 6;
1841 			break;
1842 		case 384000:
1843 			tx_fs_rate = 7;
1844 			break;
1845 		default:
1846 			dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1847 				params_rate(params));
1848 			return -EINVAL;
1849 
1850 		}
1851 
1852 		ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1853 						 params_rate(params));
1854 		if (ret < 0) {
1855 			dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1856 			return ret;
1857 		}
1858 		switch (params_width(params)) {
1859 		case 16 ... 32:
1860 			wcd->dai[dai->id].sconfig.bps = params_width(params);
1861 			break;
1862 		default:
1863 			dev_err(wcd->dev, "Invalid format 0x%x\n",
1864 				params_width(params));
1865 			return -EINVAL;
1866 		}
1867 		break;
1868 	default:
1869 		dev_err(wcd->dev, "Invalid stream type %d\n",
1870 			substream->stream);
1871 		return -EINVAL;
1872 	}
1873 
1874 	wcd->dai[dai->id].sconfig.rate = params_rate(params);
1875 
1876 	return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1877 }
1878 
wcd934x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1879 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1880 			   struct snd_soc_dai *dai)
1881 {
1882 	struct wcd_slim_codec_dai_data *dai_data;
1883 	struct wcd934x_codec *wcd;
1884 
1885 	wcd = snd_soc_component_get_drvdata(dai->component);
1886 
1887 	dai_data = &wcd->dai[dai->id];
1888 
1889 	kfree(dai_data->sconfig.chs);
1890 
1891 	return 0;
1892 }
1893 
wcd934x_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1894 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1895 			   struct snd_soc_dai *dai)
1896 {
1897 	struct wcd_slim_codec_dai_data *dai_data;
1898 	struct wcd934x_codec *wcd;
1899 	struct slim_stream_config *cfg;
1900 
1901 	wcd = snd_soc_component_get_drvdata(dai->component);
1902 
1903 	dai_data = &wcd->dai[dai->id];
1904 
1905 	switch (cmd) {
1906 	case SNDRV_PCM_TRIGGER_START:
1907 	case SNDRV_PCM_TRIGGER_RESUME:
1908 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1909 		cfg = &dai_data->sconfig;
1910 		slim_stream_prepare(dai_data->sruntime, cfg);
1911 		slim_stream_enable(dai_data->sruntime);
1912 		break;
1913 	case SNDRV_PCM_TRIGGER_STOP:
1914 	case SNDRV_PCM_TRIGGER_SUSPEND:
1915 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1916 		slim_stream_disable(dai_data->sruntime);
1917 		slim_stream_unprepare(dai_data->sruntime);
1918 		break;
1919 	default:
1920 		break;
1921 	}
1922 
1923 	return 0;
1924 }
1925 
wcd934x_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,unsigned int * tx_slot,unsigned int rx_num,unsigned int * rx_slot)1926 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1927 				   unsigned int tx_num, unsigned int *tx_slot,
1928 				   unsigned int rx_num, unsigned int *rx_slot)
1929 {
1930 	struct wcd934x_codec *wcd;
1931 	int i;
1932 
1933 	wcd = snd_soc_component_get_drvdata(dai->component);
1934 
1935 	if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1936 		dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1937 			tx_num, rx_num);
1938 		return -EINVAL;
1939 	}
1940 
1941 	if (!tx_slot || !rx_slot) {
1942 		dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1943 			tx_slot, rx_slot);
1944 		return -EINVAL;
1945 	}
1946 
1947 	wcd->num_rx_port = rx_num;
1948 	for (i = 0; i < rx_num; i++) {
1949 		wcd->rx_chs[i].ch_num = rx_slot[i];
1950 		INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1951 	}
1952 
1953 	wcd->num_tx_port = tx_num;
1954 	for (i = 0; i < tx_num; i++) {
1955 		wcd->tx_chs[i].ch_num = tx_slot[i];
1956 		INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1957 	}
1958 
1959 	return 0;
1960 }
1961 
wcd934x_get_channel_map(struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1962 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1963 				   unsigned int *tx_num, unsigned int *tx_slot,
1964 				   unsigned int *rx_num, unsigned int *rx_slot)
1965 {
1966 	struct wcd934x_slim_ch *ch;
1967 	struct wcd934x_codec *wcd;
1968 	int i = 0;
1969 
1970 	wcd = snd_soc_component_get_drvdata(dai->component);
1971 
1972 	switch (dai->id) {
1973 	case AIF1_PB:
1974 	case AIF2_PB:
1975 	case AIF3_PB:
1976 	case AIF4_PB:
1977 		if (!rx_slot || !rx_num) {
1978 			dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1979 				rx_slot, rx_num);
1980 			return -EINVAL;
1981 		}
1982 
1983 		list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1984 			rx_slot[i++] = ch->ch_num;
1985 
1986 		*rx_num = i;
1987 		break;
1988 	case AIF1_CAP:
1989 	case AIF2_CAP:
1990 	case AIF3_CAP:
1991 		if (!tx_slot || !tx_num) {
1992 			dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1993 				tx_slot, tx_num);
1994 			return -EINVAL;
1995 		}
1996 
1997 		list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1998 			tx_slot[i++] = ch->ch_num;
1999 
2000 		*tx_num = i;
2001 		break;
2002 	default:
2003 		dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2004 		break;
2005 	}
2006 
2007 	return 0;
2008 }
2009 
2010 static const struct snd_soc_dai_ops wcd934x_dai_ops = {
2011 	.hw_params = wcd934x_hw_params,
2012 	.hw_free = wcd934x_hw_free,
2013 	.trigger = wcd934x_trigger,
2014 	.set_channel_map = wcd934x_set_channel_map,
2015 	.get_channel_map = wcd934x_get_channel_map,
2016 };
2017 
2018 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
2019 	[0] = {
2020 		.name = "wcd934x_rx1",
2021 		.id = AIF1_PB,
2022 		.playback = {
2023 			.stream_name = "AIF1 Playback",
2024 			.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2025 			.formats = WCD934X_FORMATS_S16_S24_LE,
2026 			.rate_max = 192000,
2027 			.rate_min = 8000,
2028 			.channels_min = 1,
2029 			.channels_max = 2,
2030 		},
2031 		.ops = &wcd934x_dai_ops,
2032 	},
2033 	[1] = {
2034 		.name = "wcd934x_tx1",
2035 		.id = AIF1_CAP,
2036 		.capture = {
2037 			.stream_name = "AIF1 Capture",
2038 			.rates = WCD934X_RATES_MASK,
2039 			.formats = SNDRV_PCM_FMTBIT_S16_LE,
2040 			.rate_min = 8000,
2041 			.rate_max = 192000,
2042 			.channels_min = 1,
2043 			.channels_max = 4,
2044 		},
2045 		.ops = &wcd934x_dai_ops,
2046 	},
2047 	[2] = {
2048 		.name = "wcd934x_rx2",
2049 		.id = AIF2_PB,
2050 		.playback = {
2051 			.stream_name = "AIF2 Playback",
2052 			.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2053 			.formats = WCD934X_FORMATS_S16_S24_LE,
2054 			.rate_min = 8000,
2055 			.rate_max = 192000,
2056 			.channels_min = 1,
2057 			.channels_max = 2,
2058 		},
2059 		.ops = &wcd934x_dai_ops,
2060 	},
2061 	[3] = {
2062 		.name = "wcd934x_tx2",
2063 		.id = AIF2_CAP,
2064 		.capture = {
2065 			.stream_name = "AIF2 Capture",
2066 			.rates = WCD934X_RATES_MASK,
2067 			.formats = SNDRV_PCM_FMTBIT_S16_LE,
2068 			.rate_min = 8000,
2069 			.rate_max = 192000,
2070 			.channels_min = 1,
2071 			.channels_max = 4,
2072 		},
2073 		.ops = &wcd934x_dai_ops,
2074 	},
2075 	[4] = {
2076 		.name = "wcd934x_rx3",
2077 		.id = AIF3_PB,
2078 		.playback = {
2079 			.stream_name = "AIF3 Playback",
2080 			.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2081 			.formats = WCD934X_FORMATS_S16_S24_LE,
2082 			.rate_min = 8000,
2083 			.rate_max = 192000,
2084 			.channels_min = 1,
2085 			.channels_max = 2,
2086 		},
2087 		.ops = &wcd934x_dai_ops,
2088 	},
2089 	[5] = {
2090 		.name = "wcd934x_tx3",
2091 		.id = AIF3_CAP,
2092 		.capture = {
2093 			.stream_name = "AIF3 Capture",
2094 			.rates = WCD934X_RATES_MASK,
2095 			.formats = SNDRV_PCM_FMTBIT_S16_LE,
2096 			.rate_min = 8000,
2097 			.rate_max = 192000,
2098 			.channels_min = 1,
2099 			.channels_max = 4,
2100 		},
2101 		.ops = &wcd934x_dai_ops,
2102 	},
2103 	[6] = {
2104 		.name = "wcd934x_rx4",
2105 		.id = AIF4_PB,
2106 		.playback = {
2107 			.stream_name = "AIF4 Playback",
2108 			.rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2109 			.formats = WCD934X_FORMATS_S16_S24_LE,
2110 			.rate_min = 8000,
2111 			.rate_max = 192000,
2112 			.channels_min = 1,
2113 			.channels_max = 2,
2114 		},
2115 		.ops = &wcd934x_dai_ops,
2116 	},
2117 };
2118 
swclk_gate_enable(struct clk_hw * hw)2119 static int swclk_gate_enable(struct clk_hw *hw)
2120 {
2121 	return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2122 }
2123 
swclk_gate_disable(struct clk_hw * hw)2124 static void swclk_gate_disable(struct clk_hw *hw)
2125 {
2126 	wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2127 }
2128 
swclk_gate_is_enabled(struct clk_hw * hw)2129 static int swclk_gate_is_enabled(struct clk_hw *hw)
2130 {
2131 	struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2132 	int ret, val;
2133 
2134 	regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2135 	ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2136 
2137 	return ret;
2138 }
2139 
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2140 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2141 				       unsigned long parent_rate)
2142 {
2143 	return parent_rate / 2;
2144 }
2145 
2146 static const struct clk_ops swclk_gate_ops = {
2147 	.prepare = swclk_gate_enable,
2148 	.unprepare = swclk_gate_disable,
2149 	.is_enabled = swclk_gate_is_enabled,
2150 	.recalc_rate = swclk_recalc_rate,
2151 
2152 };
2153 
wcd934x_register_mclk_output(struct wcd934x_codec * wcd)2154 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2155 {
2156 	struct clk *parent = wcd->extclk;
2157 	struct device *dev = wcd->dev;
2158 	struct device_node *np = dev->parent->of_node;
2159 	const char *parent_clk_name = NULL;
2160 	const char *clk_name = "mclk";
2161 	struct clk_hw *hw;
2162 	struct clk_init_data init;
2163 	int ret;
2164 
2165 	if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2166 		return NULL;
2167 
2168 	parent_clk_name = __clk_get_name(parent);
2169 
2170 	of_property_read_string(np, "clock-output-names", &clk_name);
2171 
2172 	init.name = clk_name;
2173 	init.ops = &swclk_gate_ops;
2174 	init.flags = 0;
2175 	init.parent_names = &parent_clk_name;
2176 	init.num_parents = 1;
2177 	wcd->hw.init = &init;
2178 
2179 	hw = &wcd->hw;
2180 	ret = devm_clk_hw_register(wcd->dev->parent, hw);
2181 	if (ret)
2182 		return ERR_PTR(ret);
2183 
2184 	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2185 	if (ret)
2186 		return ERR_PTR(ret);
2187 
2188 	return NULL;
2189 }
2190 
wcd934x_get_micbias_val(struct device * dev,const char * micbias,u32 * micb_mv)2191 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias,
2192 				   u32 *micb_mv)
2193 {
2194 	int mv;
2195 
2196 	if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2197 		dev_err(dev, "%s value not found, using default\n", micbias);
2198 		mv = WCD934X_DEF_MICBIAS_MV;
2199 	} else {
2200 		/* convert it to milli volts */
2201 		mv = mv/1000;
2202 	}
2203 
2204 	if (mv < 1000 || mv > 2850) {
2205 		dev_err(dev, "%s value not in valid range, using default\n",
2206 			micbias);
2207 		mv = WCD934X_DEF_MICBIAS_MV;
2208 	}
2209 
2210 	*micb_mv = mv;
2211 
2212 	return (mv - 1000) / 50;
2213 }
2214 
wcd934x_init_dmic(struct snd_soc_component * comp)2215 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2216 {
2217 	int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2218 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2219 	u32 def_dmic_rate, dmic_clk_drv;
2220 
2221 	vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2222 					     "qcom,micbias1-microvolt",
2223 					     &wcd->micb1_mv);
2224 	vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2225 					     "qcom,micbias2-microvolt",
2226 					     &wcd->micb2_mv);
2227 	vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2228 					     "qcom,micbias3-microvolt",
2229 					     &wcd->micb3_mv);
2230 	vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2231 					     "qcom,micbias4-microvolt",
2232 					     &wcd->micb4_mv);
2233 
2234 	snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2235 				      WCD934X_MICB_VAL_MASK, vout_ctl_1);
2236 	snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2237 				      WCD934X_MICB_VAL_MASK, vout_ctl_2);
2238 	snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2239 				      WCD934X_MICB_VAL_MASK, vout_ctl_3);
2240 	snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2241 				      WCD934X_MICB_VAL_MASK, vout_ctl_4);
2242 
2243 	if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2244 		def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2245 	else
2246 		def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2247 
2248 	wcd->dmic_sample_rate = def_dmic_rate;
2249 
2250 	dmic_clk_drv = 0;
2251 	snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2252 				      0x0C, dmic_clk_drv << 2);
2253 
2254 	return 0;
2255 }
2256 
wcd934x_hw_init(struct wcd934x_codec * wcd)2257 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2258 {
2259 	struct regmap *rm = wcd->regmap;
2260 
2261 	/* set SPKR rate to FS_2P4_3P072 */
2262 	regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2263 	regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2264 
2265 	/* Take DMICs out of reset */
2266 	regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2267 }
2268 
wcd934x_comp_init(struct snd_soc_component * component)2269 static int wcd934x_comp_init(struct snd_soc_component *component)
2270 {
2271 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2272 
2273 	wcd934x_hw_init(wcd);
2274 	wcd934x_enable_efuse_sensing(wcd);
2275 	wcd934x_get_version(wcd);
2276 
2277 	return 0;
2278 }
2279 
wcd934x_slim_irq_handler(int irq,void * data)2280 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2281 {
2282 	struct wcd934x_codec *wcd = data;
2283 	unsigned long status = 0;
2284 	int i, j, port_id;
2285 	unsigned int val, int_val = 0;
2286 	irqreturn_t ret = IRQ_NONE;
2287 	bool tx;
2288 	unsigned short reg = 0;
2289 
2290 	for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2291 	     i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2292 		regmap_read(wcd->if_regmap, i, &val);
2293 		status |= ((u32)val << (8 * j));
2294 	}
2295 
2296 	for_each_set_bit(j, &status, 32) {
2297 		tx = false;
2298 		port_id = j;
2299 
2300 		if (j >= 16) {
2301 			tx = true;
2302 			port_id = j - 16;
2303 		}
2304 
2305 		regmap_read(wcd->if_regmap,
2306 			    WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2307 		if (val) {
2308 			if (!tx)
2309 				reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2310 					(port_id / 8);
2311 			else
2312 				reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2313 					(port_id / 8);
2314 			regmap_read(wcd->if_regmap, reg, &int_val);
2315 		}
2316 
2317 		if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2318 			dev_err_ratelimited(wcd->dev,
2319 					    "overflow error on %s port %d, value %x\n",
2320 					    (tx ? "TX" : "RX"), port_id, val);
2321 
2322 		if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2323 			dev_err_ratelimited(wcd->dev,
2324 					    "underflow error on %s port %d, value %x\n",
2325 					    (tx ? "TX" : "RX"), port_id, val);
2326 
2327 		if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2328 		    (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2329 			if (!tx)
2330 				reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2331 					(port_id / 8);
2332 			else
2333 				reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2334 					(port_id / 8);
2335 			regmap_read(
2336 				wcd->if_regmap, reg, &int_val);
2337 			if (int_val & (1 << (port_id % 8))) {
2338 				int_val = int_val ^ (1 << (port_id % 8));
2339 				regmap_write(wcd->if_regmap,
2340 					     reg, int_val);
2341 			}
2342 		}
2343 
2344 		if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2345 			dev_err_ratelimited(wcd->dev,
2346 					    "Port Closed %s port %d, value %x\n",
2347 					    (tx ? "TX" : "RX"), port_id, val);
2348 
2349 		regmap_write(wcd->if_regmap,
2350 			     WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2351 				BIT(j % 8));
2352 		ret = IRQ_HANDLED;
2353 	}
2354 
2355 	return ret;
2356 }
2357 
wcd934x_mbhc_clk_setup(struct snd_soc_component * component,bool enable)2358 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component,
2359 				   bool enable)
2360 {
2361 	snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1,
2362 				      WCD934X_MBHC_CTL_RCO_EN_MASK, enable);
2363 }
2364 
wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component * component,bool enable)2365 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2366 					   bool enable)
2367 {
2368 	snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT,
2369 				      WCD934X_ANA_MBHC_BIAS_EN, enable);
2370 }
2371 
wcd934x_mbhc_program_btn_thr(struct snd_soc_component * component,int * btn_low,int * btn_high,int num_btn,bool is_micbias)2372 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component,
2373 					 int *btn_low, int *btn_high,
2374 					 int num_btn, bool is_micbias)
2375 {
2376 	int i, vth;
2377 
2378 	if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2379 		dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2380 			__func__, num_btn);
2381 		return;
2382 	}
2383 
2384 	for (i = 0; i < num_btn; i++) {
2385 		vth = ((btn_high[i] * 2) / 25) & 0x3F;
2386 		snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i,
2387 					   WCD934X_MBHC_BTN_VTH_MASK, vth);
2388 	}
2389 }
2390 
wcd934x_mbhc_micb_en_status(struct snd_soc_component * component,int micb_num)2391 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2392 {
2393 	u8 val;
2394 
2395 	if (micb_num == MIC_BIAS_2) {
2396 		val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
2397 						   WCD934X_ANA_MICB2_ENABLE_MASK);
2398 		if (val == WCD934X_MICB_ENABLE)
2399 			return true;
2400 	}
2401 	return false;
2402 }
2403 
wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component * component,enum mbhc_hs_pullup_iref pull_up_cur)2404 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2405 					       enum mbhc_hs_pullup_iref pull_up_cur)
2406 {
2407 	/* Default pull up current to 2uA */
2408 	if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
2409 	    pull_up_cur == I_DEFAULT)
2410 		pull_up_cur = I_2P0_UA;
2411 
2412 
2413 	snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL,
2414 				      WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur);
2415 }
2416 
wcd934x_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2417 static int wcd934x_micbias_control(struct snd_soc_component *component,
2418 			    int micb_num, int req, bool is_dapm)
2419 {
2420 	struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2421 	int micb_index = micb_num - 1;
2422 	u16 micb_reg;
2423 
2424 	switch (micb_num) {
2425 	case MIC_BIAS_1:
2426 		micb_reg = WCD934X_ANA_MICB1;
2427 		break;
2428 	case MIC_BIAS_2:
2429 		micb_reg = WCD934X_ANA_MICB2;
2430 		break;
2431 	case MIC_BIAS_3:
2432 		micb_reg = WCD934X_ANA_MICB3;
2433 		break;
2434 	case MIC_BIAS_4:
2435 		micb_reg = WCD934X_ANA_MICB4;
2436 		break;
2437 	default:
2438 		dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2439 			__func__, micb_num);
2440 		return -EINVAL;
2441 	}
2442 	mutex_lock(&wcd934x->micb_lock);
2443 
2444 	switch (req) {
2445 	case MICB_PULLUP_ENABLE:
2446 		wcd934x->pullup_ref[micb_index]++;
2447 		if ((wcd934x->pullup_ref[micb_index] == 1) &&
2448 		    (wcd934x->micb_ref[micb_index] == 0))
2449 			snd_soc_component_write_field(component, micb_reg,
2450 						      WCD934X_ANA_MICB_EN_MASK,
2451 						      WCD934X_MICB_PULL_UP);
2452 		break;
2453 	case MICB_PULLUP_DISABLE:
2454 		if (wcd934x->pullup_ref[micb_index] > 0)
2455 			wcd934x->pullup_ref[micb_index]--;
2456 
2457 		if ((wcd934x->pullup_ref[micb_index] == 0) &&
2458 		    (wcd934x->micb_ref[micb_index] == 0))
2459 			snd_soc_component_write_field(component, micb_reg,
2460 						      WCD934X_ANA_MICB_EN_MASK, 0);
2461 		break;
2462 	case MICB_ENABLE:
2463 		wcd934x->micb_ref[micb_index]++;
2464 		if (wcd934x->micb_ref[micb_index] == 1) {
2465 			snd_soc_component_write_field(component, micb_reg,
2466 						      WCD934X_ANA_MICB_EN_MASK,
2467 						      WCD934X_MICB_ENABLE);
2468 			if (micb_num  == MIC_BIAS_2)
2469 				wcd_mbhc_event_notify(wcd934x->mbhc,
2470 						      WCD_EVENT_POST_MICBIAS_2_ON);
2471 		}
2472 
2473 		if (micb_num  == MIC_BIAS_2 && is_dapm)
2474 			wcd_mbhc_event_notify(wcd934x->mbhc,
2475 					      WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2476 		break;
2477 	case MICB_DISABLE:
2478 		if (wcd934x->micb_ref[micb_index] > 0)
2479 			wcd934x->micb_ref[micb_index]--;
2480 
2481 		if ((wcd934x->micb_ref[micb_index] == 0) &&
2482 		    (wcd934x->pullup_ref[micb_index] > 0))
2483 			snd_soc_component_write_field(component, micb_reg,
2484 						      WCD934X_ANA_MICB_EN_MASK,
2485 						      WCD934X_MICB_PULL_UP);
2486 		else if ((wcd934x->micb_ref[micb_index] == 0) &&
2487 			 (wcd934x->pullup_ref[micb_index] == 0)) {
2488 			if (micb_num  == MIC_BIAS_2)
2489 				wcd_mbhc_event_notify(wcd934x->mbhc,
2490 						      WCD_EVENT_PRE_MICBIAS_2_OFF);
2491 
2492 			snd_soc_component_write_field(component, micb_reg,
2493 						      WCD934X_ANA_MICB_EN_MASK, 0);
2494 			if (micb_num  == MIC_BIAS_2)
2495 				wcd_mbhc_event_notify(wcd934x->mbhc,
2496 						      WCD_EVENT_POST_MICBIAS_2_OFF);
2497 		}
2498 		if (is_dapm && micb_num  == MIC_BIAS_2)
2499 			wcd_mbhc_event_notify(wcd934x->mbhc,
2500 					      WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2501 		break;
2502 	}
2503 
2504 	mutex_unlock(&wcd934x->micb_lock);
2505 
2506 	return 0;
2507 }
2508 
wcd934x_mbhc_request_micbias(struct snd_soc_component * component,int micb_num,int req)2509 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component,
2510 					int micb_num, int req)
2511 {
2512 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2513 	int ret;
2514 
2515 	if (req == MICB_ENABLE)
2516 		__wcd934x_cdc_mclk_enable(wcd, true);
2517 
2518 	ret = wcd934x_micbias_control(component, micb_num, req, false);
2519 
2520 	if (req == MICB_DISABLE)
2521 		__wcd934x_cdc_mclk_enable(wcd, false);
2522 
2523 	return ret;
2524 }
2525 
wcd934x_mbhc_micb_ramp_control(struct snd_soc_component * component,bool enable)2526 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2527 					   bool enable)
2528 {
2529 	if (enable) {
2530 		snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2531 				    WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3);
2532 		snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2533 				    WCD934X_RAMP_EN_MASK, 1);
2534 	} else {
2535 		snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2536 				    WCD934X_RAMP_EN_MASK, 0);
2537 		snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2538 				    WCD934X_RAMP_SHIFT_CTRL_MASK, 0);
2539 	}
2540 }
2541 
wcd934x_get_micb_vout_ctl_val(u32 micb_mv)2542 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv)
2543 {
2544 	/* min micbias voltage is 1V and maximum is 2.85V */
2545 	if (micb_mv < 1000 || micb_mv > 2850)
2546 		return -EINVAL;
2547 
2548 	return (micb_mv - 1000) / 50;
2549 }
2550 
wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component * component,int req_volt,int micb_num)2551 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
2552 					    int req_volt, int micb_num)
2553 {
2554 	struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2555 	int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
2556 
2557 	switch (micb_num) {
2558 	case MIC_BIAS_1:
2559 		micb_reg = WCD934X_ANA_MICB1;
2560 		break;
2561 	case MIC_BIAS_2:
2562 		micb_reg = WCD934X_ANA_MICB2;
2563 		break;
2564 	case MIC_BIAS_3:
2565 		micb_reg = WCD934X_ANA_MICB3;
2566 		break;
2567 	case MIC_BIAS_4:
2568 		micb_reg = WCD934X_ANA_MICB4;
2569 		break;
2570 	default:
2571 		return -EINVAL;
2572 	}
2573 	mutex_lock(&wcd934x->micb_lock);
2574 	/*
2575 	 * If requested micbias voltage is same as current micbias
2576 	 * voltage, then just return. Otherwise, adjust voltage as
2577 	 * per requested value. If micbias is already enabled, then
2578 	 * to avoid slow micbias ramp-up or down enable pull-up
2579 	 * momentarily, change the micbias value and then re-enable
2580 	 * micbias.
2581 	 */
2582 	micb_en = snd_soc_component_read_field(component, micb_reg,
2583 						WCD934X_ANA_MICB_EN_MASK);
2584 	cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
2585 						    WCD934X_MICB_VAL_MASK);
2586 
2587 	req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt);
2588 	if (req_vout_ctl < 0) {
2589 		ret = -EINVAL;
2590 		goto exit;
2591 	}
2592 
2593 	if (cur_vout_ctl == req_vout_ctl) {
2594 		ret = 0;
2595 		goto exit;
2596 	}
2597 
2598 	if (micb_en == WCD934X_MICB_ENABLE)
2599 		snd_soc_component_write_field(component, micb_reg,
2600 					      WCD934X_ANA_MICB_EN_MASK,
2601 					      WCD934X_MICB_PULL_UP);
2602 
2603 	snd_soc_component_write_field(component, micb_reg,
2604 				      WCD934X_MICB_VAL_MASK,
2605 				      req_vout_ctl);
2606 
2607 	if (micb_en == WCD934X_MICB_ENABLE) {
2608 		snd_soc_component_write_field(component, micb_reg,
2609 					      WCD934X_ANA_MICB_EN_MASK,
2610 					      WCD934X_MICB_ENABLE);
2611 		/*
2612 		 * Add 2ms delay as per HW requirement after enabling
2613 		 * micbias
2614 		 */
2615 		usleep_range(2000, 2100);
2616 	}
2617 exit:
2618 	mutex_unlock(&wcd934x->micb_lock);
2619 	return ret;
2620 }
2621 
wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component * component,int micb_num,bool req_en)2622 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2623 						int micb_num, bool req_en)
2624 {
2625 	struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2626 	int rc, micb_mv;
2627 
2628 	if (micb_num != MIC_BIAS_2)
2629 		return -EINVAL;
2630 	/*
2631 	 * If device tree micbias level is already above the minimum
2632 	 * voltage needed to detect threshold microphone, then do
2633 	 * not change the micbias, just return.
2634 	 */
2635 	if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2636 		return 0;
2637 
2638 	micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv;
2639 
2640 	rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2641 
2642 	return rc;
2643 }
2644 
wcd934x_mbhc_get_result_params(struct wcd934x_codec * wcd934x,s16 * d1_a,u16 noff,int32_t * zdet)2645 static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x,
2646 						s16 *d1_a, u16 noff,
2647 						int32_t *zdet)
2648 {
2649 	int i;
2650 	int val, val1;
2651 	s16 c1;
2652 	s32 x1, d1;
2653 	int32_t denom;
2654 	int minCode_param[] = {
2655 			3277, 1639, 820, 410, 205, 103, 52, 26
2656 	};
2657 
2658 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20);
2659 	for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) {
2660 		regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
2661 		if (val & 0x80)
2662 			break;
2663 	}
2664 	val = val << 0x8;
2665 	regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1);
2666 	val |= val1;
2667 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00);
2668 	x1 = WCD934X_MBHC_GET_X1(val);
2669 	c1 = WCD934X_MBHC_GET_C1(val);
2670 	/* If ramp is not complete, give additional 5ms */
2671 	if ((c1 < 2) && x1)
2672 		usleep_range(5000, 5050);
2673 
2674 	if (!c1 || !x1) {
2675 		dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2676 			__func__, c1, x1);
2677 		goto ramp_down;
2678 	}
2679 	d1 = d1_a[c1];
2680 	denom = (x1 * d1) - (1 << (14 - noff));
2681 	if (denom > 0)
2682 		*zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom;
2683 	else if (x1 < minCode_param[noff])
2684 		*zdet = WCD934X_ZDET_FLOATING_IMPEDANCE;
2685 
2686 	dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n",
2687 		__func__, d1, c1, x1, *zdet);
2688 ramp_down:
2689 	i = 0;
2690 
2691 	while (x1) {
2692 		regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
2693 		regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1);
2694 		val = val << 0x08;
2695 		val |= val1;
2696 		x1 = WCD934X_MBHC_GET_X1(val);
2697 		i++;
2698 		if (i == WCD934X_ZDET_NUM_MEASUREMENTS)
2699 			break;
2700 	}
2701 }
2702 
wcd934x_mbhc_zdet_ramp(struct snd_soc_component * component,struct wcd934x_mbhc_zdet_param * zdet_param,int32_t * zl,int32_t * zr,s16 * d1_a)2703 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component,
2704 				 struct wcd934x_mbhc_zdet_param *zdet_param,
2705 				 int32_t *zl, int32_t *zr, s16 *d1_a)
2706 {
2707 	struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2708 	int32_t zdet = 0;
2709 
2710 	snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2711 				WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
2712 	snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5,
2713 				    WCD934X_VTH_MASK, zdet_param->btn5);
2714 	snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6,
2715 				      WCD934X_VTH_MASK, zdet_param->btn6);
2716 	snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7,
2717 				     WCD934X_VTH_MASK, zdet_param->btn7);
2718 	snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2719 				WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
2720 	snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL,
2721 				0x0F, zdet_param->nshift);
2722 
2723 	if (!zl)
2724 		goto z_right;
2725 	/* Start impedance measurement for HPH_L */
2726 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80);
2727 	wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2728 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00);
2729 
2730 	*zl = zdet;
2731 
2732 z_right:
2733 	if (!zr)
2734 		return;
2735 	/* Start impedance measurement for HPH_R */
2736 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40);
2737 	wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2738 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00);
2739 
2740 	*zr = zdet;
2741 }
2742 
wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component * component,int32_t * z_val,int flag_l_r)2743 static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2744 					int32_t *z_val, int flag_l_r)
2745 {
2746 	s16 q1;
2747 	int q1_cal;
2748 
2749 	if (*z_val < (WCD934X_ZDET_VAL_400/1000))
2750 		q1 = snd_soc_component_read(component,
2751 			WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
2752 	else
2753 		q1 = snd_soc_component_read(component,
2754 			WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
2755 	if (q1 & 0x80)
2756 		q1_cal = (10000 - ((q1 & 0x7F) * 25));
2757 	else
2758 		q1_cal = (10000 + (q1 * 25));
2759 	if (q1_cal > 0)
2760 		*z_val = ((*z_val) * 10000) / q1_cal;
2761 }
2762 
wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component * component,uint32_t * zl,uint32_t * zr)2763 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2764 					    uint32_t *zl, uint32_t *zr)
2765 {
2766 	struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2767 	s16 reg0, reg1, reg2, reg3, reg4;
2768 	int32_t z1L, z1R, z1Ls;
2769 	int zMono, z_diff1, z_diff2;
2770 	bool is_fsm_disable = false;
2771 	struct wcd934x_mbhc_zdet_param zdet_param[] = {
2772 		{4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
2773 		{2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
2774 		{1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
2775 		{1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
2776 	};
2777 	struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL;
2778 	s16 d1_a[][4] = {
2779 		{0, 30, 90, 30},
2780 		{0, 30, 30, 5},
2781 		{0, 30, 30, 5},
2782 		{0, 30, 30, 5},
2783 	};
2784 	s16 *d1 = NULL;
2785 
2786 	reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5);
2787 	reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
2788 	reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7);
2789 	reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK);
2790 	reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL);
2791 
2792 	if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) {
2793 		is_fsm_disable = true;
2794 		regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00);
2795 	}
2796 
2797 	/* For NO-jack, disable L_DET_EN before Z-det measurements */
2798 	if (wcd934x->mbhc_cfg.hphl_swh)
2799 		regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00);
2800 
2801 	/* Turn off 100k pull down on HPHL */
2802 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00);
2803 
2804 	/* First get impedance on Left */
2805 	d1 = d1_a[1];
2806 	zdet_param_ptr = &zdet_param[1];
2807 	wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2808 
2809 	if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2810 		goto left_ch_impedance;
2811 
2812 	/* Second ramp for left ch */
2813 	if (z1L < WCD934X_ZDET_VAL_32) {
2814 		zdet_param_ptr = &zdet_param[0];
2815 		d1 = d1_a[0];
2816 	} else if ((z1L > WCD934X_ZDET_VAL_400) &&
2817 		  (z1L <= WCD934X_ZDET_VAL_1200)) {
2818 		zdet_param_ptr = &zdet_param[2];
2819 		d1 = d1_a[2];
2820 	} else if (z1L > WCD934X_ZDET_VAL_1200) {
2821 		zdet_param_ptr = &zdet_param[3];
2822 		d1 = d1_a[3];
2823 	}
2824 	wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2825 
2826 left_ch_impedance:
2827 	if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2828 		(z1L > WCD934X_ZDET_VAL_100K)) {
2829 		*zl = WCD934X_ZDET_FLOATING_IMPEDANCE;
2830 		zdet_param_ptr = &zdet_param[1];
2831 		d1 = d1_a[1];
2832 	} else {
2833 		*zl = z1L/1000;
2834 		wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0);
2835 	}
2836 	dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2837 		__func__, *zl);
2838 
2839 	/* Start of right impedance ramp and calculation */
2840 	wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2841 	if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2842 		if (((z1R > WCD934X_ZDET_VAL_1200) &&
2843 			(zdet_param_ptr->noff == 0x6)) ||
2844 			((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE))
2845 			goto right_ch_impedance;
2846 		/* Second ramp for right ch */
2847 		if (z1R < WCD934X_ZDET_VAL_32) {
2848 			zdet_param_ptr = &zdet_param[0];
2849 			d1 = d1_a[0];
2850 		} else if ((z1R > WCD934X_ZDET_VAL_400) &&
2851 			(z1R <= WCD934X_ZDET_VAL_1200)) {
2852 			zdet_param_ptr = &zdet_param[2];
2853 			d1 = d1_a[2];
2854 		} else if (z1R > WCD934X_ZDET_VAL_1200) {
2855 			zdet_param_ptr = &zdet_param[3];
2856 			d1 = d1_a[3];
2857 		}
2858 		wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2859 	}
2860 right_ch_impedance:
2861 	if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2862 		(z1R > WCD934X_ZDET_VAL_100K)) {
2863 		*zr = WCD934X_ZDET_FLOATING_IMPEDANCE;
2864 	} else {
2865 		*zr = z1R/1000;
2866 		wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1);
2867 	}
2868 	dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2869 		__func__, *zr);
2870 
2871 	/* Mono/stereo detection */
2872 	if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) &&
2873 		(*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) {
2874 		dev_dbg(component->dev,
2875 			"%s: plug type is invalid or extension cable\n",
2876 			__func__);
2877 		goto zdet_complete;
2878 	}
2879 	if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2880 	    (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2881 	    ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2882 	    ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2883 		dev_dbg(component->dev,
2884 			"%s: Mono plug type with one ch floating or shorted to GND\n",
2885 			__func__);
2886 		wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2887 		goto zdet_complete;
2888 	}
2889 	snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2890 				      WCD934X_HPHPA_GND_OVR_MASK, 1);
2891 	snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2892 				      WCD934X_HPHPA_GND_R_MASK, 1);
2893 	if (*zl < (WCD934X_ZDET_VAL_32/1000))
2894 		wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
2895 	else
2896 		wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
2897 	snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2898 				      WCD934X_HPHPA_GND_R_MASK, 0);
2899 	snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2900 				      WCD934X_HPHPA_GND_OVR_MASK, 0);
2901 	z1Ls /= 1000;
2902 	wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
2903 	/* Parallel of left Z and 9 ohm pull down resistor */
2904 	zMono = ((*zl) * 9) / ((*zl) + 9);
2905 	z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2906 	z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2907 	if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2908 		dev_err(component->dev, "%s: stereo plug type detected\n",
2909 			__func__);
2910 		wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO);
2911 	} else {
2912 		dev_err(component->dev, "%s: MONO plug type detected\n",
2913 			__func__);
2914 		wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2915 	}
2916 
2917 zdet_complete:
2918 	snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0);
2919 	snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
2920 	snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2);
2921 	/* Turn on 100k pull down on HPHL */
2922 	regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01);
2923 
2924 	/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2925 	if (wcd934x->mbhc_cfg.hphl_swh)
2926 		regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80);
2927 
2928 	snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2929 	snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3);
2930 	if (is_fsm_disable)
2931 		regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80);
2932 }
2933 
wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component * component,bool enable)2934 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2935 			bool enable)
2936 {
2937 	if (enable) {
2938 		snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2939 					      WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1);
2940 		snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2941 					      WCD934X_MBHC_GND_DET_EN_MASK, 1);
2942 	} else {
2943 		snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2944 					      WCD934X_MBHC_GND_DET_EN_MASK, 0);
2945 		snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2946 					      WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0);
2947 	}
2948 }
2949 
wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component * component,bool enable)2950 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2951 					  bool enable)
2952 {
2953 	snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2954 				      WCD934X_HPHPA_GND_R_MASK, enable);
2955 	snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2956 				      WCD934X_HPHPA_GND_L_MASK, enable);
2957 }
2958 
2959 static const struct wcd_mbhc_cb mbhc_cb = {
2960 	.clk_setup = wcd934x_mbhc_clk_setup,
2961 	.mbhc_bias = wcd934x_mbhc_mbhc_bias_control,
2962 	.set_btn_thr = wcd934x_mbhc_program_btn_thr,
2963 	.micbias_enable_status = wcd934x_mbhc_micb_en_status,
2964 	.hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control,
2965 	.mbhc_micbias_control = wcd934x_mbhc_request_micbias,
2966 	.mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control,
2967 	.mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic,
2968 	.compute_impedance = wcd934x_wcd_mbhc_calc_impedance,
2969 	.mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl,
2970 	.hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl,
2971 };
2972 
wcd934x_get_hph_type(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2973 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol,
2974 			      struct snd_ctl_elem_value *ucontrol)
2975 {
2976 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2977 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2978 
2979 	ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc);
2980 
2981 	return 0;
2982 }
2983 
wcd934x_hph_impedance_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2984 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2985 				   struct snd_ctl_elem_value *ucontrol)
2986 {
2987 	uint32_t zl, zr;
2988 	bool hphr;
2989 	struct soc_mixer_control *mc;
2990 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2991 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2992 
2993 	mc = (struct soc_mixer_control *)(kcontrol->private_value);
2994 	hphr = mc->shift;
2995 	wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr);
2996 	dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2997 	ucontrol->value.integer.value[0] = hphr ? zr : zl;
2998 
2999 	return 0;
3000 }
3001 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
3002 	SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
3003 		       wcd934x_get_hph_type, NULL),
3004 };
3005 
3006 static const struct snd_kcontrol_new impedance_detect_controls[] = {
3007 	SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
3008 		       wcd934x_hph_impedance_get, NULL),
3009 	SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
3010 		       wcd934x_hph_impedance_get, NULL),
3011 };
3012 
wcd934x_mbhc_init(struct snd_soc_component * component)3013 static int wcd934x_mbhc_init(struct snd_soc_component *component)
3014 {
3015 	struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent);
3016 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3017 	struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids;
3018 
3019 	intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data,
3020 						     WCD934X_IRQ_MBHC_SW_DET);
3021 	intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data,
3022 							    WCD934X_IRQ_MBHC_BUTTON_PRESS_DET);
3023 	intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data,
3024 							      WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET);
3025 	intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data,
3026 							 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3027 	intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data,
3028 							 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET);
3029 	intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data,
3030 						     WCD934X_IRQ_HPH_PA_OCPL_FAULT);
3031 	intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data,
3032 						      WCD934X_IRQ_HPH_PA_OCPR_FAULT);
3033 
3034 	wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3035 	if (IS_ERR(wcd->mbhc)) {
3036 		wcd->mbhc = NULL;
3037 		return -EINVAL;
3038 	}
3039 
3040 	snd_soc_add_component_controls(component, impedance_detect_controls,
3041 				       ARRAY_SIZE(impedance_detect_controls));
3042 	snd_soc_add_component_controls(component, hph_type_detect_controls,
3043 				       ARRAY_SIZE(hph_type_detect_controls));
3044 
3045 	return 0;
3046 }
3047 
wcd934x_mbhc_deinit(struct snd_soc_component * component)3048 static void wcd934x_mbhc_deinit(struct snd_soc_component *component)
3049 {
3050 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3051 
3052 	if (!wcd->mbhc)
3053 		return;
3054 
3055 	wcd_mbhc_deinit(wcd->mbhc);
3056 }
3057 
wcd934x_comp_probe(struct snd_soc_component * component)3058 static int wcd934x_comp_probe(struct snd_soc_component *component)
3059 {
3060 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3061 	int i;
3062 
3063 	snd_soc_component_init_regmap(component, wcd->regmap);
3064 	wcd->component = component;
3065 
3066 	/* Class-H Init*/
3067 	wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
3068 	if (IS_ERR(wcd->clsh_ctrl))
3069 		return PTR_ERR(wcd->clsh_ctrl);
3070 
3071 	/* Default HPH Mode to Class-H Low HiFi */
3072 	wcd->hph_mode = CLS_H_LOHIFI;
3073 
3074 	wcd934x_comp_init(component);
3075 
3076 	for (i = 0; i < NUM_CODEC_DAIS; i++)
3077 		INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
3078 
3079 	wcd934x_init_dmic(component);
3080 
3081 	if (wcd934x_mbhc_init(component))
3082 		dev_err(component->dev, "Failed to Initialize MBHC\n");
3083 
3084 	return 0;
3085 }
3086 
wcd934x_comp_remove(struct snd_soc_component * comp)3087 static void wcd934x_comp_remove(struct snd_soc_component *comp)
3088 {
3089 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3090 
3091 	wcd934x_mbhc_deinit(comp);
3092 	wcd_clsh_ctrl_free(wcd->clsh_ctrl);
3093 }
3094 
wcd934x_comp_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)3095 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
3096 				   int clk_id, int source,
3097 				   unsigned int freq, int dir)
3098 {
3099 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3100 	int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
3101 
3102 	wcd->rate = freq;
3103 
3104 	if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
3105 		val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
3106 
3107 	snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
3108 				      WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
3109 				      val);
3110 
3111 	return clk_set_rate(wcd->extclk, freq);
3112 }
3113 
get_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,int coeff_idx)3114 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
3115 				   int iir_idx, int band_idx, int coeff_idx)
3116 {
3117 	u32 value = 0;
3118 	int reg, b2_reg;
3119 
3120 	/* Address does not automatically update if reading */
3121 	reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3122 	b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3123 
3124 	snd_soc_component_write(component, reg,
3125 				((band_idx * BAND_MAX + coeff_idx) *
3126 				 sizeof(uint32_t)) & 0x7F);
3127 
3128 	value |= snd_soc_component_read(component, b2_reg);
3129 	snd_soc_component_write(component, reg,
3130 				((band_idx * BAND_MAX + coeff_idx)
3131 				 * sizeof(uint32_t) + 1) & 0x7F);
3132 
3133 	value |= (snd_soc_component_read(component, b2_reg) << 8);
3134 	snd_soc_component_write(component, reg,
3135 				((band_idx * BAND_MAX + coeff_idx)
3136 				 * sizeof(uint32_t) + 2) & 0x7F);
3137 
3138 	value |= (snd_soc_component_read(component, b2_reg) << 16);
3139 	snd_soc_component_write(component, reg,
3140 		((band_idx * BAND_MAX + coeff_idx)
3141 		* sizeof(uint32_t) + 3) & 0x7F);
3142 
3143 	/* Mask bits top 2 bits since they are reserved */
3144 	value |= (snd_soc_component_read(component, b2_reg) << 24);
3145 	return value;
3146 }
3147 
set_iir_band_coeff(struct snd_soc_component * component,int iir_idx,int band_idx,uint32_t value)3148 static void set_iir_band_coeff(struct snd_soc_component *component,
3149 			       int iir_idx, int band_idx, uint32_t value)
3150 {
3151 	int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3152 
3153 	snd_soc_component_write(component, reg, (value & 0xFF));
3154 	snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
3155 	snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
3156 	/* Mask top 2 bits, 7-8 are reserved */
3157 	snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
3158 }
3159 
wcd934x_put_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3160 static int wcd934x_put_iir_band_audio_mixer(
3161 					struct snd_kcontrol *kcontrol,
3162 					struct snd_ctl_elem_value *ucontrol)
3163 {
3164 	struct snd_soc_component *component =
3165 			snd_soc_kcontrol_component(kcontrol);
3166 	struct wcd_iir_filter_ctl *ctl =
3167 			(struct wcd_iir_filter_ctl *)kcontrol->private_value;
3168 	struct soc_bytes_ext *params = &ctl->bytes_ext;
3169 	int iir_idx = ctl->iir_idx;
3170 	int band_idx = ctl->band_idx;
3171 	u32 coeff[BAND_MAX];
3172 	int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3173 
3174 	memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
3175 
3176 	/* Mask top bit it is reserved */
3177 	/* Updates addr automatically for each B2 write */
3178 	snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
3179 						 sizeof(uint32_t)) & 0x7F);
3180 
3181 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
3182 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
3183 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
3184 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
3185 	set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
3186 
3187 	return 0;
3188 }
3189 
wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3190 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
3191 				    struct snd_ctl_elem_value *ucontrol)
3192 {
3193 	struct snd_soc_component *component =
3194 			snd_soc_kcontrol_component(kcontrol);
3195 	struct wcd_iir_filter_ctl *ctl =
3196 			(struct wcd_iir_filter_ctl *)kcontrol->private_value;
3197 	struct soc_bytes_ext *params = &ctl->bytes_ext;
3198 	int iir_idx = ctl->iir_idx;
3199 	int band_idx = ctl->band_idx;
3200 	u32 coeff[BAND_MAX];
3201 
3202 	coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
3203 	coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
3204 	coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
3205 	coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
3206 	coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
3207 
3208 	memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
3209 
3210 	return 0;
3211 }
3212 
wcd934x_iir_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * ucontrol)3213 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
3214 				   struct snd_ctl_elem_info *ucontrol)
3215 {
3216 	struct wcd_iir_filter_ctl *ctl =
3217 		(struct wcd_iir_filter_ctl *)kcontrol->private_value;
3218 	struct soc_bytes_ext *params = &ctl->bytes_ext;
3219 
3220 	ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
3221 	ucontrol->count = params->max;
3222 
3223 	return 0;
3224 }
3225 
wcd934x_compander_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3226 static int wcd934x_compander_get(struct snd_kcontrol *kc,
3227 				 struct snd_ctl_elem_value *ucontrol)
3228 {
3229 	struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3230 	int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3231 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3232 
3233 	ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
3234 
3235 	return 0;
3236 }
3237 
wcd934x_compander_set(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3238 static int wcd934x_compander_set(struct snd_kcontrol *kc,
3239 				 struct snd_ctl_elem_value *ucontrol)
3240 {
3241 	struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3242 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3243 	int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3244 	int value = ucontrol->value.integer.value[0];
3245 	int sel;
3246 
3247 	if (wcd->comp_enabled[comp] == value)
3248 		return 0;
3249 
3250 	wcd->comp_enabled[comp] = value;
3251 	sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
3252 		WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
3253 
3254 	/* Any specific register configuration for compander */
3255 	switch (comp) {
3256 	case COMPANDER_1:
3257 		/* Set Gain Source Select based on compander enable/disable */
3258 		snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
3259 					      WCD934X_HPH_GAIN_SRC_SEL_MASK,
3260 					      sel);
3261 		break;
3262 	case COMPANDER_2:
3263 		snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
3264 					      WCD934X_HPH_GAIN_SRC_SEL_MASK,
3265 					      sel);
3266 		break;
3267 	case COMPANDER_3:
3268 	case COMPANDER_4:
3269 	case COMPANDER_7:
3270 	case COMPANDER_8:
3271 		break;
3272 	default:
3273 		return 0;
3274 	}
3275 
3276 	return 1;
3277 }
3278 
wcd934x_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3279 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
3280 				   struct snd_ctl_elem_value *ucontrol)
3281 {
3282 	struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3283 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3284 
3285 	ucontrol->value.enumerated.item[0] = wcd->hph_mode;
3286 
3287 	return 0;
3288 }
3289 
wcd934x_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3290 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
3291 				   struct snd_ctl_elem_value *ucontrol)
3292 {
3293 	struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3294 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3295 	u32 mode_val;
3296 
3297 	mode_val = ucontrol->value.enumerated.item[0];
3298 
3299 	if (mode_val == wcd->hph_mode)
3300 		return 0;
3301 
3302 	if (mode_val == 0) {
3303 		dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
3304 		mode_val = CLS_H_LOHIFI;
3305 	}
3306 	wcd->hph_mode = mode_val;
3307 
3308 	return 1;
3309 }
3310 
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3311 static int slim_rx_mux_get(struct snd_kcontrol *kc,
3312 			   struct snd_ctl_elem_value *ucontrol)
3313 {
3314 	struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3315 	struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3316 	struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3317 
3318 	ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
3319 
3320 	return 0;
3321 }
3322 
slim_rx_mux_to_dai_id(int mux)3323 static int slim_rx_mux_to_dai_id(int mux)
3324 {
3325 	int aif_id;
3326 
3327 	switch (mux) {
3328 	case 1:
3329 		aif_id = AIF1_PB;
3330 		break;
3331 	case 2:
3332 		aif_id = AIF2_PB;
3333 		break;
3334 	case 3:
3335 		aif_id = AIF3_PB;
3336 		break;
3337 	case 4:
3338 		aif_id = AIF4_PB;
3339 		break;
3340 	default:
3341 		aif_id = -1;
3342 		break;
3343 	}
3344 
3345 	return aif_id;
3346 }
3347 
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3348 static int slim_rx_mux_put(struct snd_kcontrol *kc,
3349 			   struct snd_ctl_elem_value *ucontrol)
3350 {
3351 	struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3352 	struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
3353 	struct soc_enum *e = (struct soc_enum *)kc->private_value;
3354 	struct snd_soc_dapm_update *update = NULL;
3355 	struct wcd934x_slim_ch *ch, *c;
3356 	u32 port_id = w->shift;
3357 	bool found = false;
3358 	int mux_idx;
3359 	int prev_mux_idx = wcd->rx_port_value[port_id];
3360 	int aif_id;
3361 
3362 	mux_idx = ucontrol->value.enumerated.item[0];
3363 
3364 	if (mux_idx == prev_mux_idx)
3365 		return 0;
3366 
3367 	switch(mux_idx) {
3368 	case 0:
3369 		aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
3370 		if (aif_id < 0)
3371 			return 0;
3372 
3373 		list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
3374 			if (ch->port == port_id + WCD934X_RX_START) {
3375 				found = true;
3376 				list_del_init(&ch->list);
3377 				break;
3378 			}
3379 		}
3380 		if (!found)
3381 			return 0;
3382 
3383 		break;
3384 	case 1 ... 4:
3385 		aif_id = slim_rx_mux_to_dai_id(mux_idx);
3386 		if (aif_id < 0)
3387 			return 0;
3388 
3389 		if (list_empty(&wcd->rx_chs[port_id].list)) {
3390 			list_add_tail(&wcd->rx_chs[port_id].list,
3391 				      &wcd->dai[aif_id].slim_ch_list);
3392 		} else {
3393 			dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
3394 			return 0;
3395 		}
3396 		break;
3397 
3398 	default:
3399 		dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
3400 		goto err;
3401 	}
3402 
3403 	wcd->rx_port_value[port_id] = mux_idx;
3404 	snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
3405 				      e, update);
3406 
3407 	return 1;
3408 err:
3409 	return -EINVAL;
3410 }
3411 
wcd934x_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3412 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
3413 				       struct snd_ctl_elem_value *ucontrol)
3414 {
3415 	struct soc_enum *e = (struct soc_enum *)kc->private_value;
3416 	struct snd_soc_component *component;
3417 	int reg, val;
3418 
3419 	component = snd_soc_dapm_kcontrol_component(kc);
3420 	val = ucontrol->value.enumerated.item[0];
3421 	if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
3422 		reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
3423 	else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
3424 		reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3425 	else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
3426 		reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3427 	else
3428 		return -EINVAL;
3429 
3430 	/* Set Look Ahead Delay */
3431 	if (val)
3432 		snd_soc_component_update_bits(component, reg,
3433 					      WCD934X_RX_DLY_ZN_EN_MASK,
3434 					      WCD934X_RX_DLY_ZN_ENABLE);
3435 	else
3436 		snd_soc_component_update_bits(component, reg,
3437 					      WCD934X_RX_DLY_ZN_EN_MASK,
3438 					      WCD934X_RX_DLY_ZN_DISABLE);
3439 
3440 	return snd_soc_dapm_put_enum_double(kc, ucontrol);
3441 }
3442 
wcd934x_dec_enum_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3443 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
3444 				struct snd_ctl_elem_value *ucontrol)
3445 {
3446 	struct snd_soc_component *comp;
3447 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3448 	unsigned int val;
3449 	u16 mic_sel_reg = 0;
3450 	u8 mic_sel;
3451 
3452 	comp = snd_soc_dapm_kcontrol_component(kcontrol);
3453 
3454 	val = ucontrol->value.enumerated.item[0];
3455 	if (val > e->items - 1)
3456 		return -EINVAL;
3457 
3458 	switch (e->reg) {
3459 	case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
3460 		if (e->shift_l == 0)
3461 			mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
3462 		else if (e->shift_l == 2)
3463 			mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
3464 		else if (e->shift_l == 4)
3465 			mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
3466 		break;
3467 	case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
3468 		if (e->shift_l == 0)
3469 			mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
3470 		else if (e->shift_l == 2)
3471 			mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
3472 		break;
3473 	case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
3474 		if (e->shift_l == 0)
3475 			mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
3476 		else if (e->shift_l == 2)
3477 			mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
3478 		break;
3479 	case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
3480 		if (e->shift_l == 0)
3481 			mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
3482 		else if (e->shift_l == 2)
3483 			mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
3484 		break;
3485 	default:
3486 		dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
3487 			__func__, e->reg);
3488 		return -EINVAL;
3489 	}
3490 
3491 	/* ADC: 0, DMIC: 1 */
3492 	mic_sel = val ? 0x0 : 0x1;
3493 	if (mic_sel_reg)
3494 		snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
3495 					      mic_sel << 7);
3496 
3497 	return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
3498 }
3499 
3500 static const struct snd_kcontrol_new rx_int0_2_mux =
3501 	SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
3502 
3503 static const struct snd_kcontrol_new rx_int1_2_mux =
3504 	SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
3505 
3506 static const struct snd_kcontrol_new rx_int2_2_mux =
3507 	SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
3508 
3509 static const struct snd_kcontrol_new rx_int3_2_mux =
3510 	SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
3511 
3512 static const struct snd_kcontrol_new rx_int4_2_mux =
3513 	SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
3514 
3515 static const struct snd_kcontrol_new rx_int7_2_mux =
3516 	SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
3517 
3518 static const struct snd_kcontrol_new rx_int8_2_mux =
3519 	SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
3520 
3521 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
3522 	SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
3523 
3524 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
3525 	SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
3526 
3527 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
3528 	SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
3529 
3530 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
3531 	SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
3532 
3533 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
3534 	SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
3535 
3536 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
3537 	SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
3538 
3539 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
3540 	SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
3541 
3542 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
3543 	SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
3544 
3545 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
3546 	SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
3547 
3548 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
3549 	SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
3550 
3551 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
3552 	SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
3553 
3554 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
3555 	SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
3556 
3557 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
3558 	SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
3559 
3560 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
3561 	SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
3562 
3563 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
3564 	SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
3565 
3566 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
3567 	SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
3568 
3569 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
3570 	SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
3571 
3572 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
3573 	SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
3574 
3575 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
3576 	SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
3577 
3578 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
3579 	SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
3580 
3581 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
3582 	SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
3583 
3584 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
3585 	SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
3586 
3587 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
3588 	SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
3589 
3590 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
3591 	SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
3592 
3593 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
3594 	SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
3595 
3596 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
3597 	SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
3598 
3599 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
3600 	SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
3601 
3602 static const struct snd_kcontrol_new iir0_inp0_mux =
3603 	SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
3604 static const struct snd_kcontrol_new iir0_inp1_mux =
3605 	SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
3606 static const struct snd_kcontrol_new iir0_inp2_mux =
3607 	SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
3608 static const struct snd_kcontrol_new iir0_inp3_mux =
3609 	SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
3610 
3611 static const struct snd_kcontrol_new iir1_inp0_mux =
3612 	SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
3613 static const struct snd_kcontrol_new iir1_inp1_mux =
3614 	SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
3615 static const struct snd_kcontrol_new iir1_inp2_mux =
3616 	SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
3617 static const struct snd_kcontrol_new iir1_inp3_mux =
3618 	SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
3619 
3620 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
3621 	SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
3622 			  slim_rx_mux_get, slim_rx_mux_put),
3623 	SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
3624 			  slim_rx_mux_get, slim_rx_mux_put),
3625 	SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
3626 			  slim_rx_mux_get, slim_rx_mux_put),
3627 	SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
3628 			  slim_rx_mux_get, slim_rx_mux_put),
3629 	SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
3630 			  slim_rx_mux_get, slim_rx_mux_put),
3631 	SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
3632 			  slim_rx_mux_get, slim_rx_mux_put),
3633 	SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
3634 			  slim_rx_mux_get, slim_rx_mux_put),
3635 	SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
3636 			  slim_rx_mux_get, slim_rx_mux_put),
3637 };
3638 
3639 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
3640 	SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
3641 };
3642 
3643 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
3644 	SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
3645 };
3646 
3647 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
3648 	SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
3649 };
3650 
3651 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
3652 	SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
3653 };
3654 
3655 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
3656 	SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
3657 			  snd_soc_dapm_get_enum_double,
3658 			  wcd934x_int_dem_inp_mux_put);
3659 
3660 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
3661 	SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
3662 			  snd_soc_dapm_get_enum_double,
3663 			  wcd934x_int_dem_inp_mux_put);
3664 
3665 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
3666 	SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
3667 			  snd_soc_dapm_get_enum_double,
3668 			  wcd934x_int_dem_inp_mux_put);
3669 
3670 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
3671 	SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
3672 
3673 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
3674 	SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
3675 
3676 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
3677 	SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
3678 
3679 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
3680 	SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
3681 
3682 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
3683 	SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
3684 
3685 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
3686 	SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
3687 
3688 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
3689 	SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
3690 
3691 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
3692 	SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
3693 
3694 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
3695 	SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
3696 
3697 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
3698 	SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
3699 
3700 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
3701 	SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
3702 
3703 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
3704 	SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
3705 
3706 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
3707 	SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
3708 
3709 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
3710 	SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
3711 
3712 static const struct snd_kcontrol_new tx_dmic_mux0 =
3713 	SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
3714 
3715 static const struct snd_kcontrol_new tx_dmic_mux1 =
3716 	SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
3717 
3718 static const struct snd_kcontrol_new tx_dmic_mux2 =
3719 	SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
3720 
3721 static const struct snd_kcontrol_new tx_dmic_mux3 =
3722 	SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
3723 
3724 static const struct snd_kcontrol_new tx_dmic_mux4 =
3725 	SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
3726 
3727 static const struct snd_kcontrol_new tx_dmic_mux5 =
3728 	SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
3729 
3730 static const struct snd_kcontrol_new tx_dmic_mux6 =
3731 	SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
3732 
3733 static const struct snd_kcontrol_new tx_dmic_mux7 =
3734 	SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
3735 
3736 static const struct snd_kcontrol_new tx_dmic_mux8 =
3737 	SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
3738 
3739 static const struct snd_kcontrol_new tx_amic_mux0 =
3740 	SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
3741 
3742 static const struct snd_kcontrol_new tx_amic_mux1 =
3743 	SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
3744 
3745 static const struct snd_kcontrol_new tx_amic_mux2 =
3746 	SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
3747 
3748 static const struct snd_kcontrol_new tx_amic_mux3 =
3749 	SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
3750 
3751 static const struct snd_kcontrol_new tx_amic_mux4 =
3752 	SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
3753 
3754 static const struct snd_kcontrol_new tx_amic_mux5 =
3755 	SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
3756 
3757 static const struct snd_kcontrol_new tx_amic_mux6 =
3758 	SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
3759 
3760 static const struct snd_kcontrol_new tx_amic_mux7 =
3761 	SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
3762 
3763 static const struct snd_kcontrol_new tx_amic_mux8 =
3764 	SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
3765 
3766 static const struct snd_kcontrol_new tx_amic4_5 =
3767 	SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
3768 
3769 static const struct snd_kcontrol_new tx_adc_mux0_mux =
3770 	SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
3771 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3772 static const struct snd_kcontrol_new tx_adc_mux1_mux =
3773 	SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
3774 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3775 static const struct snd_kcontrol_new tx_adc_mux2_mux =
3776 	SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
3777 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3778 static const struct snd_kcontrol_new tx_adc_mux3_mux =
3779 	SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
3780 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3781 static const struct snd_kcontrol_new tx_adc_mux4_mux =
3782 	SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
3783 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3784 static const struct snd_kcontrol_new tx_adc_mux5_mux =
3785 	SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
3786 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3787 static const struct snd_kcontrol_new tx_adc_mux6_mux =
3788 	SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
3789 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3790 static const struct snd_kcontrol_new tx_adc_mux7_mux =
3791 	SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
3792 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3793 static const struct snd_kcontrol_new tx_adc_mux8_mux =
3794 	SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
3795 			  snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3796 
3797 static const struct snd_kcontrol_new cdc_if_tx0_mux =
3798 	SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3799 static const struct snd_kcontrol_new cdc_if_tx1_mux =
3800 	SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3801 static const struct snd_kcontrol_new cdc_if_tx2_mux =
3802 	SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3803 static const struct snd_kcontrol_new cdc_if_tx3_mux =
3804 	SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3805 static const struct snd_kcontrol_new cdc_if_tx4_mux =
3806 	SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3807 static const struct snd_kcontrol_new cdc_if_tx5_mux =
3808 	SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3809 static const struct snd_kcontrol_new cdc_if_tx6_mux =
3810 	SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3811 static const struct snd_kcontrol_new cdc_if_tx7_mux =
3812 	SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3813 static const struct snd_kcontrol_new cdc_if_tx8_mux =
3814 	SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3815 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3816 	SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3817 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3818 	SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3819 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3820 	SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3821 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3822 	SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3823 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3824 	SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3825 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3826 	SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3827 
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3828 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3829 			     struct snd_ctl_elem_value *ucontrol)
3830 {
3831 	struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3832 	struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3833 	struct soc_mixer_control *mixer =
3834 			(struct soc_mixer_control *)kc->private_value;
3835 	int port_id = mixer->shift;
3836 
3837 	ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3838 
3839 	return 0;
3840 }
3841 
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)3842 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3843 			     struct snd_ctl_elem_value *ucontrol)
3844 {
3845 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3846 	struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3847 	struct snd_soc_dapm_update *update = NULL;
3848 	struct soc_mixer_control *mixer =
3849 			(struct soc_mixer_control *)kc->private_value;
3850 	int enable = ucontrol->value.integer.value[0];
3851 	struct wcd934x_slim_ch *ch, *c;
3852 	int dai_id = widget->shift;
3853 	int port_id = mixer->shift;
3854 
3855 	/* only add to the list if value not set */
3856 	if (enable == wcd->tx_port_value[port_id])
3857 		return 0;
3858 
3859 	if (enable) {
3860 		if (list_empty(&wcd->tx_chs[port_id].list)) {
3861 			list_add_tail(&wcd->tx_chs[port_id].list,
3862 				      &wcd->dai[dai_id].slim_ch_list);
3863 		} else {
3864 			dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3865 			return 0;
3866 		}
3867 	 } else {
3868 		bool found = false;
3869 
3870 		list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3871 			if (ch->port == port_id) {
3872 				found = true;
3873 				list_del_init(&wcd->tx_chs[port_id].list);
3874 				break;
3875 			}
3876 		}
3877 		if (!found)
3878 			return 0;
3879 	 }
3880 
3881 	wcd->tx_port_value[port_id] = enable;
3882 	snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3883 
3884 	return 1;
3885 }
3886 
3887 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3888 	SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3889 		       slim_tx_mixer_get, slim_tx_mixer_put),
3890 	SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3891 		       slim_tx_mixer_get, slim_tx_mixer_put),
3892 	SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3893 		       slim_tx_mixer_get, slim_tx_mixer_put),
3894 	SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3895 		       slim_tx_mixer_get, slim_tx_mixer_put),
3896 	SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3897 		       slim_tx_mixer_get, slim_tx_mixer_put),
3898 	SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3899 		       slim_tx_mixer_get, slim_tx_mixer_put),
3900 	SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3901 		       slim_tx_mixer_get, slim_tx_mixer_put),
3902 	SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3903 		       slim_tx_mixer_get, slim_tx_mixer_put),
3904 	SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3905 		       slim_tx_mixer_get, slim_tx_mixer_put),
3906 	SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3907 		       slim_tx_mixer_get, slim_tx_mixer_put),
3908 	SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3909 		       slim_tx_mixer_get, slim_tx_mixer_put),
3910 	SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3911 		       slim_tx_mixer_get, slim_tx_mixer_put),
3912 	SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3913 		       slim_tx_mixer_get, slim_tx_mixer_put),
3914 };
3915 
3916 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3917 	SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3918 		       slim_tx_mixer_get, slim_tx_mixer_put),
3919 	SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3920 		       slim_tx_mixer_get, slim_tx_mixer_put),
3921 	SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3922 		       slim_tx_mixer_get, slim_tx_mixer_put),
3923 	SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3924 		       slim_tx_mixer_get, slim_tx_mixer_put),
3925 	SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3926 		       slim_tx_mixer_get, slim_tx_mixer_put),
3927 	SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3928 		       slim_tx_mixer_get, slim_tx_mixer_put),
3929 	SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3930 		       slim_tx_mixer_get, slim_tx_mixer_put),
3931 	SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3932 		       slim_tx_mixer_get, slim_tx_mixer_put),
3933 	SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3934 		       slim_tx_mixer_get, slim_tx_mixer_put),
3935 	SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3936 		       slim_tx_mixer_get, slim_tx_mixer_put),
3937 	SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3938 		       slim_tx_mixer_get, slim_tx_mixer_put),
3939 	SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3940 		       slim_tx_mixer_get, slim_tx_mixer_put),
3941 	SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3942 		       slim_tx_mixer_get, slim_tx_mixer_put),
3943 };
3944 
3945 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3946 	SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3947 		       slim_tx_mixer_get, slim_tx_mixer_put),
3948 	SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3949 		       slim_tx_mixer_get, slim_tx_mixer_put),
3950 	SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3951 		       slim_tx_mixer_get, slim_tx_mixer_put),
3952 	SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3953 		       slim_tx_mixer_get, slim_tx_mixer_put),
3954 	SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3955 		       slim_tx_mixer_get, slim_tx_mixer_put),
3956 	SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3957 		       slim_tx_mixer_get, slim_tx_mixer_put),
3958 	SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3959 		       slim_tx_mixer_get, slim_tx_mixer_put),
3960 	SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3961 		       slim_tx_mixer_get, slim_tx_mixer_put),
3962 	SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3963 		       slim_tx_mixer_get, slim_tx_mixer_put),
3964 	SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3965 		       slim_tx_mixer_get, slim_tx_mixer_put),
3966 	SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3967 		       slim_tx_mixer_get, slim_tx_mixer_put),
3968 	SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3969 		       slim_tx_mixer_get, slim_tx_mixer_put),
3970 	SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3971 		       slim_tx_mixer_get, slim_tx_mixer_put),
3972 };
3973 
3974 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3975 	/* Gain Controls */
3976 	SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3977 	SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3978 	SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3979 	SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3980 		       3, 16, 1, line_gain),
3981 	SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3982 		       3, 16, 1, line_gain),
3983 
3984 	SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3985 	SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3986 	SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3987 	SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3988 
3989 	SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3990 			  -84, 40, digital_gain), /* -84dB min - 40dB max */
3991 	SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3992 			  -84, 40, digital_gain),
3993 	SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3994 			  -84, 40, digital_gain),
3995 	SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3996 			  -84, 40, digital_gain),
3997 	SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3998 			  -84, 40, digital_gain),
3999 	SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
4000 			  -84, 40, digital_gain),
4001 	SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
4002 			  -84, 40, digital_gain),
4003 	SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
4004 			  WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
4005 			  -84, 40, digital_gain),
4006 	SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
4007 			  WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
4008 			  -84, 40, digital_gain),
4009 	SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
4010 			  WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
4011 			  -84, 40, digital_gain),
4012 	SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
4013 			  WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
4014 			  -84, 40, digital_gain),
4015 	SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
4016 			  WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
4017 			  -84, 40, digital_gain),
4018 	SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
4019 			  WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
4020 			  -84, 40, digital_gain),
4021 	SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
4022 			  WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
4023 			  -84, 40, digital_gain),
4024 
4025 	SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
4026 			  -84, 40, digital_gain),
4027 	SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
4028 			  -84, 40, digital_gain),
4029 	SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
4030 			  -84, 40, digital_gain),
4031 	SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
4032 			  -84, 40, digital_gain),
4033 	SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
4034 			  -84, 40, digital_gain),
4035 	SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
4036 			  -84, 40, digital_gain),
4037 	SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
4038 			  -84, 40, digital_gain),
4039 	SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
4040 			  -84, 40, digital_gain),
4041 	SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
4042 			  -84, 40, digital_gain),
4043 
4044 	SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
4045 			  WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
4046 			  digital_gain),
4047 	SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
4048 			  WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
4049 			  digital_gain),
4050 	SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
4051 			  WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
4052 			  digital_gain),
4053 	SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
4054 			  WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
4055 			  digital_gain),
4056 	SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
4057 			  WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
4058 			  digital_gain),
4059 	SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
4060 			  WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
4061 			  digital_gain),
4062 	SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
4063 			  WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
4064 			  digital_gain),
4065 	SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
4066 			  WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
4067 			  digital_gain),
4068 
4069 	SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
4070 	SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
4071 	SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
4072 	SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
4073 	SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
4074 	SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
4075 	SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
4076 	SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
4077 	SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
4078 
4079 	SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
4080 	SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
4081 	SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
4082 	SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
4083 	SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
4084 	SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
4085 	SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
4086 	SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
4087 	SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
4088 	SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
4089 	SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
4090 	SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
4091 	SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
4092 	SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
4093 
4094 	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
4095 		     wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
4096 
4097 	SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4098 		   0, 1, 0),
4099 	SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4100 		   1, 1, 0),
4101 	SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4102 		   2, 1, 0),
4103 	SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4104 		   3, 1, 0),
4105 	SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4106 		   4, 1, 0),
4107 	SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4108 		   0, 1, 0),
4109 	SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4110 		   1, 1, 0),
4111 	SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4112 		   2, 1, 0),
4113 	SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4114 		   3, 1, 0),
4115 	SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4116 		   4, 1, 0),
4117 	WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
4118 	WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
4119 	WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
4120 	WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
4121 	WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
4122 
4123 	WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
4124 	WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
4125 	WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
4126 	WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
4127 	WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
4128 
4129 	SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
4130 		       wcd934x_compander_get, wcd934x_compander_set),
4131 	SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
4132 		       wcd934x_compander_get, wcd934x_compander_set),
4133 	SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
4134 		       wcd934x_compander_get, wcd934x_compander_set),
4135 	SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
4136 		       wcd934x_compander_get, wcd934x_compander_set),
4137 	SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
4138 		       wcd934x_compander_get, wcd934x_compander_set),
4139 	SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
4140 		       wcd934x_compander_get, wcd934x_compander_set),
4141 };
4142 
wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)4143 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
4144 					  struct snd_soc_component *component)
4145 {
4146 	int port_num = 0;
4147 	unsigned short reg = 0;
4148 	unsigned int val = 0;
4149 	struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
4150 	struct wcd934x_slim_ch *ch;
4151 
4152 	list_for_each_entry(ch, &dai->slim_ch_list, list) {
4153 		if (ch->port >= WCD934X_RX_START) {
4154 			port_num = ch->port - WCD934X_RX_START;
4155 			reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
4156 		} else {
4157 			port_num = ch->port;
4158 			reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
4159 		}
4160 
4161 		regmap_read(wcd->if_regmap, reg, &val);
4162 		if (!(val & BIT(port_num % 8)))
4163 			regmap_write(wcd->if_regmap, reg,
4164 				     val | BIT(port_num % 8));
4165 	}
4166 }
4167 
wcd934x_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4168 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
4169 				     struct snd_kcontrol *kc, int event)
4170 {
4171 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4172 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4173 	struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
4174 
4175 	switch (event) {
4176 	case SND_SOC_DAPM_POST_PMU:
4177 		wcd934x_codec_enable_int_port(dai, comp);
4178 		break;
4179 	}
4180 
4181 	return 0;
4182 }
4183 
wcd934x_codec_hd2_control(struct snd_soc_component * component,u16 interp_idx,int event)4184 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
4185 				      u16 interp_idx, int event)
4186 {
4187 	u16 hd2_scale_reg;
4188 	u16 hd2_enable_reg = 0;
4189 
4190 	switch (interp_idx) {
4191 	case INTERP_HPHL:
4192 		hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
4193 		hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
4194 		break;
4195 	case INTERP_HPHR:
4196 		hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
4197 		hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
4198 		break;
4199 	default:
4200 		return;
4201 	}
4202 
4203 	if (SND_SOC_DAPM_EVENT_ON(event)) {
4204 		snd_soc_component_update_bits(component, hd2_scale_reg,
4205 				      WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4206 				      WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
4207 		snd_soc_component_update_bits(component, hd2_enable_reg,
4208 				      WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4209 				      WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
4210 	}
4211 
4212 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
4213 		snd_soc_component_update_bits(component, hd2_enable_reg,
4214 				      WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4215 				      WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
4216 		snd_soc_component_update_bits(component, hd2_scale_reg,
4217 				      WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4218 				      WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
4219 	}
4220 }
4221 
wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component * comp,u16 interp_idx,int event)4222 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
4223 					     u16 interp_idx, int event)
4224 {
4225 	u8 hph_dly_mask;
4226 	u16 hph_lut_bypass_reg = 0;
4227 
4228 	switch (interp_idx) {
4229 	case INTERP_HPHL:
4230 		hph_dly_mask = 1;
4231 		hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
4232 		break;
4233 	case INTERP_HPHR:
4234 		hph_dly_mask = 2;
4235 		hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
4236 		break;
4237 	default:
4238 		return;
4239 	}
4240 
4241 	if (SND_SOC_DAPM_EVENT_ON(event)) {
4242 		snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4243 					      hph_dly_mask, 0x0);
4244 		snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4245 					      WCD934X_HPH_LUT_BYPASS_MASK,
4246 					      WCD934X_HPH_LUT_BYPASS_ENABLE);
4247 	}
4248 
4249 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
4250 		snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4251 					      hph_dly_mask, hph_dly_mask);
4252 		snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4253 					      WCD934X_HPH_LUT_BYPASS_MASK,
4254 					      WCD934X_HPH_LUT_BYPASS_DISABLE);
4255 	}
4256 }
4257 
wcd934x_config_compander(struct snd_soc_component * comp,int interp_n,int event)4258 static int wcd934x_config_compander(struct snd_soc_component *comp,
4259 				    int interp_n, int event)
4260 {
4261 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4262 	int compander;
4263 	u16 comp_ctl0_reg, rx_path_cfg0_reg;
4264 
4265 	/* EAR does not have compander */
4266 	if (!interp_n)
4267 		return 0;
4268 
4269 	compander = interp_n - 1;
4270 	if (!wcd->comp_enabled[compander])
4271 		return 0;
4272 
4273 	comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
4274 	rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
4275 
4276 	switch (event) {
4277 	case SND_SOC_DAPM_PRE_PMU:
4278 		/* Enable Compander Clock */
4279 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4280 					      WCD934X_COMP_CLK_EN_MASK,
4281 					      WCD934X_COMP_CLK_ENABLE);
4282 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4283 					      WCD934X_COMP_SOFT_RST_MASK,
4284 					      WCD934X_COMP_SOFT_RST_ENABLE);
4285 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4286 					      WCD934X_COMP_SOFT_RST_MASK,
4287 					      WCD934X_COMP_SOFT_RST_DISABLE);
4288 		snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4289 					      WCD934X_HPH_CMP_EN_MASK,
4290 					      WCD934X_HPH_CMP_ENABLE);
4291 		break;
4292 	case SND_SOC_DAPM_POST_PMD:
4293 		snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4294 					      WCD934X_HPH_CMP_EN_MASK,
4295 					      WCD934X_HPH_CMP_DISABLE);
4296 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4297 					      WCD934X_COMP_HALT_MASK,
4298 					      WCD934X_COMP_HALT);
4299 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4300 					      WCD934X_COMP_SOFT_RST_MASK,
4301 					      WCD934X_COMP_SOFT_RST_ENABLE);
4302 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4303 					      WCD934X_COMP_SOFT_RST_MASK,
4304 					      WCD934X_COMP_SOFT_RST_DISABLE);
4305 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4306 					      WCD934X_COMP_CLK_EN_MASK, 0x0);
4307 		snd_soc_component_update_bits(comp, comp_ctl0_reg,
4308 					      WCD934X_COMP_SOFT_RST_MASK, 0x0);
4309 		break;
4310 	}
4311 
4312 	return 0;
4313 }
4314 
wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4315 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
4316 					 struct snd_kcontrol *kc, int event)
4317 {
4318 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4319 	int interp_idx = w->shift;
4320 	u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
4321 
4322 	switch (event) {
4323 	case SND_SOC_DAPM_PRE_PMU:
4324 		/* Clk enable */
4325 		snd_soc_component_update_bits(comp, main_reg,
4326 					     WCD934X_RX_CLK_EN_MASK,
4327 					     WCD934X_RX_CLK_ENABLE);
4328 		wcd934x_codec_hd2_control(comp, interp_idx, event);
4329 		wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4330 		wcd934x_config_compander(comp, interp_idx, event);
4331 		break;
4332 	case SND_SOC_DAPM_POST_PMD:
4333 		wcd934x_config_compander(comp, interp_idx, event);
4334 		wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4335 		wcd934x_codec_hd2_control(comp, interp_idx, event);
4336 		/* Clk Disable */
4337 		snd_soc_component_update_bits(comp, main_reg,
4338 					     WCD934X_RX_CLK_EN_MASK, 0);
4339 		/* Reset enable and disable */
4340 		snd_soc_component_update_bits(comp, main_reg,
4341 					      WCD934X_RX_RESET_MASK,
4342 					      WCD934X_RX_RESET_ENABLE);
4343 		snd_soc_component_update_bits(comp, main_reg,
4344 					      WCD934X_RX_RESET_MASK,
4345 					      WCD934X_RX_RESET_DISABLE);
4346 		/* Reset rate to 48K*/
4347 		snd_soc_component_update_bits(comp, main_reg,
4348 					      WCD934X_RX_PCM_RATE_MASK,
4349 					      WCD934X_RX_PCM_RATE_F_48K);
4350 		break;
4351 	}
4352 
4353 	return 0;
4354 }
4355 
wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4356 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
4357 					 struct snd_kcontrol *kc, int event)
4358 {
4359 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4360 	int offset_val = 0;
4361 	u16 gain_reg, mix_reg;
4362 	int val = 0;
4363 
4364 	gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
4365 					(w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4366 	mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
4367 					(w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4368 
4369 	switch (event) {
4370 	case SND_SOC_DAPM_PRE_PMU:
4371 		/* Clk enable */
4372 		snd_soc_component_update_bits(comp, mix_reg,
4373 					      WCD934X_CDC_RX_MIX_CLK_EN_MASK,
4374 					      WCD934X_CDC_RX_MIX_CLK_ENABLE);
4375 		break;
4376 
4377 	case SND_SOC_DAPM_POST_PMU:
4378 		val = snd_soc_component_read(comp, gain_reg);
4379 		val += offset_val;
4380 		snd_soc_component_write(comp, gain_reg, val);
4381 		break;
4382 	}
4383 
4384 	return 0;
4385 }
4386 
wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4387 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
4388 				      struct snd_kcontrol *kcontrol, int event)
4389 {
4390 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4391 	int reg = w->reg;
4392 
4393 	switch (event) {
4394 	case SND_SOC_DAPM_POST_PMU:
4395 		/* B1 GAIN */
4396 		snd_soc_component_write(comp, reg,
4397 					snd_soc_component_read(comp, reg));
4398 		/* B2 GAIN */
4399 		reg++;
4400 		snd_soc_component_write(comp, reg,
4401 					snd_soc_component_read(comp, reg));
4402 		/* B3 GAIN */
4403 		reg++;
4404 		snd_soc_component_write(comp, reg,
4405 					snd_soc_component_read(comp, reg));
4406 		/* B4 GAIN */
4407 		reg++;
4408 		snd_soc_component_write(comp, reg,
4409 					snd_soc_component_read(comp, reg));
4410 		/* B5 GAIN */
4411 		reg++;
4412 		snd_soc_component_write(comp, reg,
4413 					snd_soc_component_read(comp, reg));
4414 		break;
4415 	default:
4416 		break;
4417 	}
4418 	return 0;
4419 }
4420 
wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4421 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
4422 					  struct snd_kcontrol *kcontrol,
4423 					  int event)
4424 {
4425 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4426 	u16 gain_reg;
4427 
4428 	gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
4429 						 WCD934X_RX_PATH_CTL_OFFSET);
4430 
4431 	switch (event) {
4432 	case SND_SOC_DAPM_POST_PMU:
4433 		snd_soc_component_write(comp, gain_reg,
4434 				snd_soc_component_read(comp, gain_reg));
4435 		break;
4436 	}
4437 
4438 	return 0;
4439 }
4440 
wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4441 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
4442 				       struct snd_kcontrol *kc, int event)
4443 {
4444 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4445 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4446 
4447 	switch (event) {
4448 	case SND_SOC_DAPM_PRE_PMU:
4449 		/* Disable AutoChop timer during power up */
4450 		snd_soc_component_update_bits(comp,
4451 				      WCD934X_HPH_NEW_INT_HPH_TIMER1,
4452 				      WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4453 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4454 					WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4455 
4456 		break;
4457 	case SND_SOC_DAPM_POST_PMD:
4458 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4459 					WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4460 		break;
4461 	}
4462 
4463 	return 0;
4464 }
4465 
wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4466 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
4467 					struct snd_kcontrol *kcontrol,
4468 					int event)
4469 {
4470 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4471 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4472 	int hph_mode = wcd->hph_mode;
4473 	u8 dem_inp;
4474 
4475 	switch (event) {
4476 	case SND_SOC_DAPM_PRE_PMU:
4477 		/* Read DEM INP Select */
4478 		dem_inp = snd_soc_component_read(comp,
4479 				   WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
4480 
4481 		if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4482 		     (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4483 			return -EINVAL;
4484 		}
4485 		if (hph_mode != CLS_H_LP)
4486 			/* Ripple freq control enable */
4487 			snd_soc_component_update_bits(comp,
4488 					WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4489 					WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4490 					WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4491 		/* Disable AutoChop timer during power up */
4492 		snd_soc_component_update_bits(comp,
4493 				      WCD934X_HPH_NEW_INT_HPH_TIMER1,
4494 				      WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4495 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4496 					WCD_CLSH_STATE_HPHL, hph_mode);
4497 
4498 		break;
4499 	case SND_SOC_DAPM_POST_PMD:
4500 		/* 1000us required as per HW requirement */
4501 		usleep_range(1000, 1100);
4502 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4503 					WCD_CLSH_STATE_HPHL, hph_mode);
4504 		if (hph_mode != CLS_H_LP)
4505 			/* Ripple freq control disable */
4506 			snd_soc_component_update_bits(comp,
4507 					WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4508 					WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4509 
4510 		break;
4511 	default:
4512 		break;
4513 	}
4514 
4515 	return 0;
4516 }
4517 
wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4518 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
4519 					struct snd_kcontrol *kcontrol,
4520 					int event)
4521 {
4522 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4523 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4524 	int hph_mode = wcd->hph_mode;
4525 	u8 dem_inp;
4526 
4527 	switch (event) {
4528 	case SND_SOC_DAPM_PRE_PMU:
4529 		dem_inp = snd_soc_component_read(comp,
4530 					WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
4531 		if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4532 		     (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4533 			return -EINVAL;
4534 		}
4535 		if (hph_mode != CLS_H_LP)
4536 			/* Ripple freq control enable */
4537 			snd_soc_component_update_bits(comp,
4538 					WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4539 					WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4540 					WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4541 		/* Disable AutoChop timer during power up */
4542 		snd_soc_component_update_bits(comp,
4543 				      WCD934X_HPH_NEW_INT_HPH_TIMER1,
4544 				      WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4545 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4546 					WCD_CLSH_STATE_HPHR,
4547 			     hph_mode);
4548 		break;
4549 	case SND_SOC_DAPM_POST_PMD:
4550 		/* 1000us required as per HW requirement */
4551 		usleep_range(1000, 1100);
4552 
4553 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4554 					WCD_CLSH_STATE_HPHR, hph_mode);
4555 		if (hph_mode != CLS_H_LP)
4556 			/* Ripple freq control disable */
4557 			snd_soc_component_update_bits(comp,
4558 					WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4559 					WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4560 		break;
4561 	default:
4562 		break;
4563 	}
4564 
4565 	return 0;
4566 }
4567 
wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4568 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
4569 					   struct snd_kcontrol *kc, int event)
4570 {
4571 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4572 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4573 
4574 	switch (event) {
4575 	case SND_SOC_DAPM_PRE_PMU:
4576 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4577 					WCD_CLSH_STATE_LO, CLS_AB);
4578 		break;
4579 	case SND_SOC_DAPM_POST_PMD:
4580 		wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4581 					WCD_CLSH_STATE_LO, CLS_AB);
4582 		break;
4583 	}
4584 
4585 	return 0;
4586 }
4587 
wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4588 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
4589 					struct snd_kcontrol *kcontrol,
4590 					int event)
4591 {
4592 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4593 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4594 
4595 	switch (event) {
4596 	case SND_SOC_DAPM_POST_PMU:
4597 		/*
4598 		 * 7ms sleep is required after PA is enabled as per
4599 		 * HW requirement. If compander is disabled, then
4600 		 * 20ms delay is needed.
4601 		 */
4602 		usleep_range(20000, 20100);
4603 
4604 		snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4605 					      WCD934X_HPH_OCP_DET_MASK,
4606 					      WCD934X_HPH_OCP_DET_ENABLE);
4607 		/* Remove Mute on primary path */
4608 		snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4609 				      WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4610 				      0);
4611 		/* Enable GM3 boost */
4612 		snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4613 					      WCD934X_HPH_GM3_BOOST_EN_MASK,
4614 					      WCD934X_HPH_GM3_BOOST_ENABLE);
4615 		/* Enable AutoChop timer at the end of power up */
4616 		snd_soc_component_update_bits(comp,
4617 				      WCD934X_HPH_NEW_INT_HPH_TIMER1,
4618 				      WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4619 				      WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4620 		/* Remove mix path mute */
4621 		snd_soc_component_update_bits(comp,
4622 				WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4623 				WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
4624 		break;
4625 	case SND_SOC_DAPM_PRE_PMD:
4626 		wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4627 		/* Enable DSD Mute before PA disable */
4628 		snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4629 					      WCD934X_HPH_OCP_DET_MASK,
4630 					      WCD934X_HPH_OCP_DET_DISABLE);
4631 		snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4632 					      WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4633 					      WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4634 		snd_soc_component_update_bits(comp,
4635 					      WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4636 					      WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4637 					      WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4638 		break;
4639 	case SND_SOC_DAPM_POST_PMD:
4640 		/*
4641 		 * 5ms sleep is required after PA disable. If compander is
4642 		 * disabled, then 20ms delay is needed after PA disable.
4643 		 */
4644 		usleep_range(20000, 20100);
4645 		wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4646 		break;
4647 	}
4648 
4649 	return 0;
4650 }
4651 
wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4652 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
4653 					struct snd_kcontrol *kcontrol,
4654 					int event)
4655 {
4656 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4657 	struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4658 
4659 	switch (event) {
4660 	case SND_SOC_DAPM_POST_PMU:
4661 		/*
4662 		 * 7ms sleep is required after PA is enabled as per
4663 		 * HW requirement. If compander is disabled, then
4664 		 * 20ms delay is needed.
4665 		 */
4666 		usleep_range(20000, 20100);
4667 		snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4668 					      WCD934X_HPH_OCP_DET_MASK,
4669 					      WCD934X_HPH_OCP_DET_ENABLE);
4670 		/* Remove mute */
4671 		snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4672 					      WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4673 					      0);
4674 		/* Enable GM3 boost */
4675 		snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4676 					      WCD934X_HPH_GM3_BOOST_EN_MASK,
4677 					      WCD934X_HPH_GM3_BOOST_ENABLE);
4678 		/* Enable AutoChop timer at the end of power up */
4679 		snd_soc_component_update_bits(comp,
4680 				      WCD934X_HPH_NEW_INT_HPH_TIMER1,
4681 				      WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4682 				      WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4683 		/* Remove mix path mute if it is enabled */
4684 		if ((snd_soc_component_read(comp,
4685 				      WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
4686 			snd_soc_component_update_bits(comp,
4687 					      WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4688 					      WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4689 					      WCD934X_CDC_RX_PGA_MUTE_DISABLE);
4690 		break;
4691 	case SND_SOC_DAPM_PRE_PMD:
4692 		wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
4693 		snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4694 					      WCD934X_HPH_OCP_DET_MASK,
4695 					      WCD934X_HPH_OCP_DET_DISABLE);
4696 		snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4697 					      WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4698 					      WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4699 		snd_soc_component_update_bits(comp,
4700 					      WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4701 					      WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4702 					      WCD934X_CDC_RX_PGA_MUTE_ENABLE);
4703 		break;
4704 	case SND_SOC_DAPM_POST_PMD:
4705 		/*
4706 		 * 5ms sleep is required after PA disable. If compander is
4707 		 * disabled, then 20ms delay is needed after PA disable.
4708 		 */
4709 		usleep_range(20000, 20100);
4710 		wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
4711 		break;
4712 	}
4713 
4714 	return 0;
4715 }
4716 
wcd934x_get_dmic_sample_rate(struct snd_soc_component * comp,unsigned int dmic,struct wcd934x_codec * wcd)4717 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
4718 					unsigned int dmic,
4719 				      struct wcd934x_codec *wcd)
4720 {
4721 	u8 tx_stream_fs;
4722 	u8 adc_mux_index = 0, adc_mux_sel = 0;
4723 	bool dec_found = false;
4724 	u16 adc_mux_ctl_reg, tx_fs_reg;
4725 	u32 dmic_fs;
4726 
4727 	while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
4728 		if (adc_mux_index < 4) {
4729 			adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4730 						(adc_mux_index * 2);
4731 		} else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
4732 			adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4733 						adc_mux_index - 4;
4734 		} else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
4735 			++adc_mux_index;
4736 			continue;
4737 		}
4738 		adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
4739 			       & 0xF8) >> 3) - 1;
4740 
4741 		if (adc_mux_sel == dmic) {
4742 			dec_found = true;
4743 			break;
4744 		}
4745 
4746 		++adc_mux_index;
4747 	}
4748 
4749 	if (dec_found && adc_mux_index <= 8) {
4750 		tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
4751 		tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
4752 		if (tx_stream_fs <= 4)
4753 			dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ);
4754 		else
4755 			dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
4756 	} else {
4757 		dmic_fs = wcd->dmic_sample_rate;
4758 	}
4759 
4760 	return dmic_fs;
4761 }
4762 
wcd934x_get_dmic_clk_val(struct snd_soc_component * comp,u32 mclk_rate,u32 dmic_clk_rate)4763 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
4764 				   u32 mclk_rate, u32 dmic_clk_rate)
4765 {
4766 	u32 div_factor;
4767 	u8 dmic_ctl_val;
4768 
4769 	/* Default value to return in case of error */
4770 	if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
4771 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4772 	else
4773 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4774 
4775 	if (dmic_clk_rate == 0) {
4776 		dev_err(comp->dev,
4777 			"%s: dmic_sample_rate cannot be 0\n",
4778 			__func__);
4779 		goto done;
4780 	}
4781 
4782 	div_factor = mclk_rate / dmic_clk_rate;
4783 	switch (div_factor) {
4784 	case 2:
4785 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4786 		break;
4787 	case 3:
4788 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4789 		break;
4790 	case 4:
4791 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
4792 		break;
4793 	case 6:
4794 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
4795 		break;
4796 	case 8:
4797 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4798 		break;
4799 	case 16:
4800 		dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4801 		break;
4802 	default:
4803 		dev_err(comp->dev,
4804 			"%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4805 			__func__, div_factor, mclk_rate, dmic_clk_rate);
4806 		break;
4807 	}
4808 
4809 done:
4810 	return dmic_ctl_val;
4811 }
4812 
wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4813 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4814 				     struct snd_kcontrol *kcontrol, int event)
4815 {
4816 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4817 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4818 	u8  dmic_clk_en = 0x01;
4819 	u16 dmic_clk_reg;
4820 	s32 *dmic_clk_cnt;
4821 	u8 dmic_rate_val, dmic_rate_shift = 1;
4822 	unsigned int dmic;
4823 	u32 dmic_sample_rate;
4824 	int ret;
4825 	char *wname;
4826 
4827 	wname = strpbrk(w->name, "012345");
4828 	if (!wname) {
4829 		dev_err(comp->dev, "%s: widget not found\n", __func__);
4830 		return -EINVAL;
4831 	}
4832 
4833 	ret = kstrtouint(wname, 10, &dmic);
4834 	if (ret < 0) {
4835 		dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4836 			__func__);
4837 		return -EINVAL;
4838 	}
4839 
4840 	switch (dmic) {
4841 	case 0:
4842 	case 1:
4843 		dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4844 		dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4845 		break;
4846 	case 2:
4847 	case 3:
4848 		dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4849 		dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4850 		break;
4851 	case 4:
4852 	case 5:
4853 		dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4854 		dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4855 		break;
4856 	default:
4857 		dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4858 			__func__);
4859 		return -EINVAL;
4860 	}
4861 
4862 	switch (event) {
4863 	case SND_SOC_DAPM_PRE_PMU:
4864 		dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4865 								wcd);
4866 		dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4867 							 dmic_sample_rate);
4868 		(*dmic_clk_cnt)++;
4869 		if (*dmic_clk_cnt == 1) {
4870 			dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4871 			snd_soc_component_update_bits(comp, dmic_clk_reg,
4872 						      WCD934X_DMIC_RATE_MASK,
4873 						      dmic_rate_val);
4874 			snd_soc_component_update_bits(comp, dmic_clk_reg,
4875 						      dmic_clk_en, dmic_clk_en);
4876 		}
4877 
4878 		break;
4879 	case SND_SOC_DAPM_POST_PMD:
4880 		(*dmic_clk_cnt)--;
4881 		if (*dmic_clk_cnt == 0)
4882 			snd_soc_component_update_bits(comp, dmic_clk_reg,
4883 						      dmic_clk_en, 0);
4884 		break;
4885 	}
4886 
4887 	return 0;
4888 }
4889 
wcd934x_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)4890 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4891 					 int adc_mux_n)
4892 {
4893 	u16 mask, shift, adc_mux_in_reg;
4894 	u16 amic_mux_sel_reg;
4895 	bool is_amic;
4896 
4897 	if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4898 	    adc_mux_n == WCD934X_INVALID_ADC_MUX)
4899 		return 0;
4900 
4901 	if (adc_mux_n < 3) {
4902 		adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4903 				 adc_mux_n;
4904 		mask = 0x03;
4905 		shift = 0;
4906 		amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4907 				   2 * adc_mux_n;
4908 	} else if (adc_mux_n < 4) {
4909 		adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4910 		mask = 0x03;
4911 		shift = 0;
4912 		amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4913 				   2 * adc_mux_n;
4914 	} else if (adc_mux_n < 7) {
4915 		adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4916 				 (adc_mux_n - 4);
4917 		mask = 0x0C;
4918 		shift = 2;
4919 		amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4920 				   adc_mux_n - 4;
4921 	} else if (adc_mux_n < 8) {
4922 		adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4923 		mask = 0x0C;
4924 		shift = 2;
4925 		amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4926 				   adc_mux_n - 4;
4927 	} else if (adc_mux_n < 12) {
4928 		adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4929 				 ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4930 				  (adc_mux_n - 9));
4931 		mask = 0x30;
4932 		shift = 4;
4933 		amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4934 				   adc_mux_n - 4;
4935 	} else if (adc_mux_n < 13) {
4936 		adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4937 		mask = 0x30;
4938 		shift = 4;
4939 		amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4940 				   adc_mux_n - 4;
4941 	} else {
4942 		adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4943 		mask = 0xC0;
4944 		shift = 6;
4945 		amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4946 				   adc_mux_n - 4;
4947 	}
4948 
4949 	is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4950 		     & mask) >> shift) == 1);
4951 	if (!is_amic)
4952 		return 0;
4953 
4954 	return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4955 }
4956 
wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)4957 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4958 					    int amic)
4959 {
4960 	u16 pwr_level_reg = 0;
4961 
4962 	switch (amic) {
4963 	case 1:
4964 	case 2:
4965 		pwr_level_reg = WCD934X_ANA_AMIC1;
4966 		break;
4967 
4968 	case 3:
4969 	case 4:
4970 		pwr_level_reg = WCD934X_ANA_AMIC3;
4971 		break;
4972 	default:
4973 		break;
4974 	}
4975 
4976 	return pwr_level_reg;
4977 }
4978 
wcd934x_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)4979 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4980 				    struct snd_kcontrol *kcontrol, int event)
4981 {
4982 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4983 	unsigned int decimator;
4984 	char *dec_adc_mux_name = NULL;
4985 	char *widget_name = NULL;
4986 	char *wname;
4987 	int ret = 0, amic_n;
4988 	u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4989 	u16 tx_gain_ctl_reg;
4990 	char *dec;
4991 	u8 hpf_coff_freq;
4992 
4993 	widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4994 	if (!widget_name)
4995 		return -ENOMEM;
4996 
4997 	wname = widget_name;
4998 	dec_adc_mux_name = strsep(&widget_name, " ");
4999 	if (!dec_adc_mux_name) {
5000 		dev_err(comp->dev, "%s: Invalid decimator = %s\n",
5001 			__func__, w->name);
5002 		ret =  -EINVAL;
5003 		goto out;
5004 	}
5005 	dec_adc_mux_name = widget_name;
5006 
5007 	dec = strpbrk(dec_adc_mux_name, "012345678");
5008 	if (!dec) {
5009 		dev_err(comp->dev, "%s: decimator index not found\n",
5010 			__func__);
5011 		ret =  -EINVAL;
5012 		goto out;
5013 	}
5014 
5015 	ret = kstrtouint(dec, 10, &decimator);
5016 	if (ret < 0) {
5017 		dev_err(comp->dev, "%s: Invalid decimator = %s\n",
5018 			__func__, wname);
5019 		ret =  -EINVAL;
5020 		goto out;
5021 	}
5022 
5023 	tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
5024 	hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
5025 	dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
5026 	tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
5027 
5028 	switch (event) {
5029 	case SND_SOC_DAPM_PRE_PMU:
5030 		amic_n = wcd934x_codec_find_amic_input(comp, decimator);
5031 		if (amic_n)
5032 			pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
5033 								 amic_n);
5034 
5035 		if (!pwr_level_reg)
5036 			break;
5037 
5038 		switch ((snd_soc_component_read(comp, pwr_level_reg) &
5039 				      WCD934X_AMIC_PWR_LVL_MASK) >>
5040 				      WCD934X_AMIC_PWR_LVL_SHIFT) {
5041 		case WCD934X_AMIC_PWR_LEVEL_LP:
5042 			snd_soc_component_update_bits(comp, dec_cfg_reg,
5043 					WCD934X_DEC_PWR_LVL_MASK,
5044 					WCD934X_DEC_PWR_LVL_LP);
5045 			break;
5046 		case WCD934X_AMIC_PWR_LEVEL_HP:
5047 			snd_soc_component_update_bits(comp, dec_cfg_reg,
5048 					WCD934X_DEC_PWR_LVL_MASK,
5049 					WCD934X_DEC_PWR_LVL_HP);
5050 			break;
5051 		case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
5052 		case WCD934X_AMIC_PWR_LEVEL_HYBRID:
5053 		default:
5054 			snd_soc_component_update_bits(comp, dec_cfg_reg,
5055 					WCD934X_DEC_PWR_LVL_MASK,
5056 					WCD934X_DEC_PWR_LVL_DF);
5057 			break;
5058 		}
5059 		break;
5060 	case SND_SOC_DAPM_POST_PMU:
5061 		hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5062 				 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5063 		if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5064 			snd_soc_component_update_bits(comp, dec_cfg_reg,
5065 						      TX_HPF_CUT_OFF_FREQ_MASK,
5066 						      CF_MIN_3DB_150HZ << 5);
5067 			snd_soc_component_update_bits(comp, hpf_gate_reg,
5068 				      WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5069 				      WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5070 			/*
5071 			 * Minimum 1 clk cycle delay is required as per
5072 			 * HW spec.
5073 			 */
5074 			usleep_range(1000, 1010);
5075 			snd_soc_component_update_bits(comp, hpf_gate_reg,
5076 				      WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5077 				      0);
5078 		}
5079 		/* apply gain after decimator is enabled */
5080 		snd_soc_component_write(comp, tx_gain_ctl_reg,
5081 					snd_soc_component_read(comp,
5082 							 tx_gain_ctl_reg));
5083 		break;
5084 	case SND_SOC_DAPM_PRE_PMD:
5085 		hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5086 				 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5087 
5088 		if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5089 			snd_soc_component_update_bits(comp, dec_cfg_reg,
5090 						      TX_HPF_CUT_OFF_FREQ_MASK,
5091 						      hpf_coff_freq << 5);
5092 			snd_soc_component_update_bits(comp, hpf_gate_reg,
5093 				      WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5094 				      WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5095 				/*
5096 				 * Minimum 1 clk cycle delay is required as per
5097 				 * HW spec.
5098 				 */
5099 			usleep_range(1000, 1010);
5100 			snd_soc_component_update_bits(comp, hpf_gate_reg,
5101 				      WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5102 				      0);
5103 		}
5104 		break;
5105 	case SND_SOC_DAPM_POST_PMD:
5106 		snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
5107 					      0x10, 0x00);
5108 		snd_soc_component_update_bits(comp, dec_cfg_reg,
5109 					      WCD934X_DEC_PWR_LVL_MASK,
5110 					      WCD934X_DEC_PWR_LVL_DF);
5111 		break;
5112 	}
5113 out:
5114 	kfree(wname);
5115 	return ret;
5116 }
5117 
wcd934x_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)5118 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
5119 				      u16 amic_reg, bool set)
5120 {
5121 	u8 mask = 0x20;
5122 	u8 val;
5123 
5124 	if (amic_reg == WCD934X_ANA_AMIC1 ||
5125 	    amic_reg == WCD934X_ANA_AMIC3)
5126 		mask = 0x40;
5127 
5128 	val = set ? mask : 0x00;
5129 
5130 	switch (amic_reg) {
5131 	case WCD934X_ANA_AMIC1:
5132 	case WCD934X_ANA_AMIC2:
5133 		snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
5134 					      mask, val);
5135 		break;
5136 	case WCD934X_ANA_AMIC3:
5137 	case WCD934X_ANA_AMIC4:
5138 		snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
5139 					      mask, val);
5140 		break;
5141 	default:
5142 		break;
5143 	}
5144 }
5145 
wcd934x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)5146 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
5147 				    struct snd_kcontrol *kcontrol, int event)
5148 {
5149 	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
5150 
5151 	switch (event) {
5152 	case SND_SOC_DAPM_PRE_PMU:
5153 		wcd934x_codec_set_tx_hold(comp, w->reg, true);
5154 		break;
5155 	default:
5156 		break;
5157 	}
5158 
5159 	return 0;
5160 }
5161 
wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)5162 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
5163 					struct snd_kcontrol *kcontrol,
5164 					int event)
5165 {
5166 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5167 	int micb_num = w->shift;
5168 
5169 	switch (event) {
5170 	case SND_SOC_DAPM_PRE_PMU:
5171 		wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true);
5172 		break;
5173 	case SND_SOC_DAPM_POST_PMU:
5174 		/* 1 msec delay as per HW requirement */
5175 		usleep_range(1000, 1100);
5176 		break;
5177 	case SND_SOC_DAPM_POST_PMD:
5178 		wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true);
5179 		break;
5180 	}
5181 
5182 	return 0;
5183 }
5184 
5185 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
5186 	/* Analog Outputs */
5187 	SND_SOC_DAPM_OUTPUT("EAR"),
5188 	SND_SOC_DAPM_OUTPUT("HPHL"),
5189 	SND_SOC_DAPM_OUTPUT("HPHR"),
5190 	SND_SOC_DAPM_OUTPUT("LINEOUT1"),
5191 	SND_SOC_DAPM_OUTPUT("LINEOUT2"),
5192 	SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
5193 	SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
5194 	SND_SOC_DAPM_OUTPUT("ANC EAR"),
5195 	SND_SOC_DAPM_OUTPUT("ANC HPHL"),
5196 	SND_SOC_DAPM_OUTPUT("ANC HPHR"),
5197 	SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
5198 	SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
5199 	SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
5200 	SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
5201 			      AIF1_PB, 0, wcd934x_codec_enable_slim,
5202 			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5203 	SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
5204 			      AIF2_PB, 0, wcd934x_codec_enable_slim,
5205 			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5206 	SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
5207 			      AIF3_PB, 0, wcd934x_codec_enable_slim,
5208 			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5209 	SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
5210 			      AIF4_PB, 0, wcd934x_codec_enable_slim,
5211 			      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5212 
5213 	SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
5214 			 &slim_rx_mux[WCD934X_RX0]),
5215 	SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
5216 			 &slim_rx_mux[WCD934X_RX1]),
5217 	SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
5218 			 &slim_rx_mux[WCD934X_RX2]),
5219 	SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
5220 			 &slim_rx_mux[WCD934X_RX3]),
5221 	SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
5222 			 &slim_rx_mux[WCD934X_RX4]),
5223 	SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
5224 			 &slim_rx_mux[WCD934X_RX5]),
5225 	SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
5226 			 &slim_rx_mux[WCD934X_RX6]),
5227 	SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
5228 			 &slim_rx_mux[WCD934X_RX7]),
5229 
5230 	SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5231 	SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5232 	SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5233 	SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5234 	SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5235 	SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5236 	SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5237 	SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5238 
5239 	SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
5240 			   &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
5241 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5242 			   SND_SOC_DAPM_POST_PMD),
5243 	SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
5244 			   &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
5245 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5246 			   SND_SOC_DAPM_POST_PMD),
5247 	SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
5248 			   &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
5249 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5250 			   SND_SOC_DAPM_POST_PMD),
5251 	SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
5252 			   &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
5253 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5254 			   SND_SOC_DAPM_POST_PMD),
5255 	SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
5256 			   &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
5257 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5258 			   SND_SOC_DAPM_POST_PMD),
5259 	SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
5260 			   &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
5261 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5262 			   SND_SOC_DAPM_POST_PMD),
5263 	SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
5264 			   &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
5265 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5266 			   SND_SOC_DAPM_POST_PMD),
5267 
5268 	SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5269 			 &rx_int0_1_mix_inp0_mux),
5270 	SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5271 			 &rx_int0_1_mix_inp1_mux),
5272 	SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5273 			 &rx_int0_1_mix_inp2_mux),
5274 	SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5275 			 &rx_int1_1_mix_inp0_mux),
5276 	SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5277 			 &rx_int1_1_mix_inp1_mux),
5278 	SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5279 			 &rx_int1_1_mix_inp2_mux),
5280 	SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5281 			 &rx_int2_1_mix_inp0_mux),
5282 	SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5283 			 &rx_int2_1_mix_inp1_mux),
5284 	SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5285 			 &rx_int2_1_mix_inp2_mux),
5286 	SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5287 			 &rx_int3_1_mix_inp0_mux),
5288 	SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5289 			 &rx_int3_1_mix_inp1_mux),
5290 	SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5291 			 &rx_int3_1_mix_inp2_mux),
5292 	SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5293 			 &rx_int4_1_mix_inp0_mux),
5294 	SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5295 			 &rx_int4_1_mix_inp1_mux),
5296 	SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5297 			 &rx_int4_1_mix_inp2_mux),
5298 	SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5299 			   &rx_int7_1_mix_inp0_mux),
5300 	SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5301 			   &rx_int7_1_mix_inp1_mux),
5302 	SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5303 			   &rx_int7_1_mix_inp2_mux),
5304 	SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5305 			   &rx_int8_1_mix_inp0_mux),
5306 	SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5307 			   &rx_int8_1_mix_inp1_mux),
5308 	SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5309 			   &rx_int8_1_mix_inp2_mux),
5310 	SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5311 	SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5312 	SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5313 	SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
5314 			   rx_int1_asrc_switch,
5315 			   ARRAY_SIZE(rx_int1_asrc_switch)),
5316 	SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5317 	SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
5318 			   rx_int2_asrc_switch,
5319 			   ARRAY_SIZE(rx_int2_asrc_switch)),
5320 	SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5321 	SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
5322 			   rx_int3_asrc_switch,
5323 			   ARRAY_SIZE(rx_int3_asrc_switch)),
5324 	SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5325 	SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
5326 			   rx_int4_asrc_switch,
5327 			   ARRAY_SIZE(rx_int4_asrc_switch)),
5328 	SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5329 	SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5330 	SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5331 	SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5332 	SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5333 	SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5334 	SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5335 	SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5336 	SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5337 	SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5338 	SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5339 	SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5340 	SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5341 
5342 	SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5343 	SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
5344 			     NULL, 0, NULL, 0),
5345 	SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
5346 			     NULL, 0, NULL, 0),
5347 	SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
5348 			   0,  &rx_int0_mix2_inp_mux, NULL,
5349 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5350 	SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
5351 			   0, &rx_int1_mix2_inp_mux,  NULL,
5352 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5353 	SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
5354 			   0, &rx_int2_mix2_inp_mux, NULL,
5355 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5356 	SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
5357 			   0, &rx_int3_mix2_inp_mux, NULL,
5358 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5359 	SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
5360 			   0, &rx_int4_mix2_inp_mux, NULL,
5361 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5362 	SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
5363 			   0, &rx_int7_mix2_inp_mux, NULL,
5364 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5365 
5366 	SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
5367 	SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
5368 	SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
5369 	SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
5370 	SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
5371 	SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
5372 	SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
5373 	SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
5374 
5375 	SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
5376 			   0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5377 			   SND_SOC_DAPM_POST_PMU),
5378 	SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5379 			   1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5380 			   SND_SOC_DAPM_POST_PMU),
5381 	SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
5382 			   4, 0, NULL, 0),
5383 	SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
5384 			   4, 0, NULL, 0),
5385 	SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
5386 			 &rx_int0_dem_inp_mux),
5387 	SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
5388 			 &rx_int1_dem_inp_mux),
5389 	SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
5390 			 &rx_int2_dem_inp_mux),
5391 
5392 	SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
5393 			   &rx_int0_1_interp_mux,
5394 			   wcd934x_codec_enable_main_path,
5395 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5396 			   SND_SOC_DAPM_POST_PMD),
5397 	SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
5398 			   &rx_int1_1_interp_mux,
5399 			   wcd934x_codec_enable_main_path,
5400 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5401 			   SND_SOC_DAPM_POST_PMD),
5402 	SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
5403 			   &rx_int2_1_interp_mux,
5404 			   wcd934x_codec_enable_main_path,
5405 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5406 			   SND_SOC_DAPM_POST_PMD),
5407 	SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
5408 			   &rx_int3_1_interp_mux,
5409 			   wcd934x_codec_enable_main_path,
5410 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5411 			   SND_SOC_DAPM_POST_PMD),
5412 	SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
5413 			   &rx_int4_1_interp_mux,
5414 			   wcd934x_codec_enable_main_path,
5415 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5416 			   SND_SOC_DAPM_POST_PMD),
5417 	SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
5418 			   &rx_int7_1_interp_mux,
5419 			   wcd934x_codec_enable_main_path,
5420 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5421 			   SND_SOC_DAPM_POST_PMD),
5422 	SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
5423 			   &rx_int8_1_interp_mux,
5424 			   wcd934x_codec_enable_main_path,
5425 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5426 			   SND_SOC_DAPM_POST_PMD),
5427 
5428 	SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
5429 			 &rx_int0_2_interp_mux),
5430 	SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
5431 			 &rx_int1_2_interp_mux),
5432 	SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
5433 			 &rx_int2_2_interp_mux),
5434 	SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
5435 			 &rx_int3_2_interp_mux),
5436 	SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
5437 			 &rx_int4_2_interp_mux),
5438 	SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
5439 			 &rx_int7_2_interp_mux),
5440 	SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
5441 			 &rx_int8_2_interp_mux),
5442 	SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
5443 			   0, 0, wcd934x_codec_ear_dac_event,
5444 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5445 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5446 	SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
5447 			   5, 0, wcd934x_codec_hphl_dac_event,
5448 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5449 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5450 	SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
5451 			   4, 0, wcd934x_codec_hphr_dac_event,
5452 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5453 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5454 	SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
5455 			   0, 0, wcd934x_codec_lineout_dac_event,
5456 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5457 	SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
5458 			   0, 0, wcd934x_codec_lineout_dac_event,
5459 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5460 	SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
5461 	SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
5462 			   wcd934x_codec_enable_hphl_pa,
5463 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5464 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5465 	SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
5466 			   wcd934x_codec_enable_hphr_pa,
5467 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5468 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5469 	SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
5470 			   NULL, 0),
5471 	SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
5472 			   NULL, 0),
5473 	SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
5474 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5475 	SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
5476 			 0, 0, NULL, 0),
5477 	SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
5478 			    0, 0, NULL, 0),
5479 	SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
5480 			 0, 0, NULL, 0),
5481 	SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
5482 			    0, 0, NULL, 0),
5483 	SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
5484 			    wcd934x_codec_enable_interp_clk,
5485 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5486 	SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
5487 			    wcd934x_codec_enable_interp_clk,
5488 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5489 	SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
5490 			    wcd934x_codec_enable_interp_clk,
5491 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5492 	SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
5493 			    wcd934x_codec_enable_interp_clk,
5494 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5495 	SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
5496 			    wcd934x_codec_enable_interp_clk,
5497 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5498 	SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
5499 			    wcd934x_codec_enable_interp_clk,
5500 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5501 	SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
5502 			    wcd934x_codec_enable_interp_clk,
5503 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5504 	SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
5505 			    0, 0, NULL, 0),
5506 	SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
5507 			    0, 0, NULL, 0),
5508 	SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
5509 			    0, 0, NULL, 0),
5510 	SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
5511 			    0, 0, NULL, 0),
5512 	SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
5513 			    0, 0, NULL, 0),
5514 	SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
5515 			    0, 0, NULL, 0),
5516 	SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
5517 			    0, 0, NULL, 0),
5518 	SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
5519 			    wcd934x_codec_enable_mclk,
5520 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5521 
5522 	/* TX */
5523 	SND_SOC_DAPM_INPUT("AMIC1"),
5524 	SND_SOC_DAPM_INPUT("AMIC2"),
5525 	SND_SOC_DAPM_INPUT("AMIC3"),
5526 	SND_SOC_DAPM_INPUT("AMIC4"),
5527 	SND_SOC_DAPM_INPUT("AMIC5"),
5528 	SND_SOC_DAPM_INPUT("DMIC0 Pin"),
5529 	SND_SOC_DAPM_INPUT("DMIC1 Pin"),
5530 	SND_SOC_DAPM_INPUT("DMIC2 Pin"),
5531 	SND_SOC_DAPM_INPUT("DMIC3 Pin"),
5532 	SND_SOC_DAPM_INPUT("DMIC4 Pin"),
5533 	SND_SOC_DAPM_INPUT("DMIC5 Pin"),
5534 
5535 	SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
5536 			       AIF1_CAP, 0, wcd934x_codec_enable_slim,
5537 			       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5538 	SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
5539 			       AIF2_CAP, 0, wcd934x_codec_enable_slim,
5540 			       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5541 	SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
5542 			       AIF3_CAP, 0, wcd934x_codec_enable_slim,
5543 			       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5544 
5545 	SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5546 	SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5547 	SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5548 	SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5549 	SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5550 	SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5551 	SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5552 	SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5553 	SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
5554 	SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
5555 	SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
5556 	SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
5557 	SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
5558 
5559 	/* Digital Mic Inputs */
5560 	SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
5561 			   wcd934x_codec_enable_dmic,
5562 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5563 	SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
5564 			   wcd934x_codec_enable_dmic,
5565 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5566 	SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
5567 			   wcd934x_codec_enable_dmic,
5568 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5569 	SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
5570 			   wcd934x_codec_enable_dmic,
5571 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5572 	SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
5573 			   wcd934x_codec_enable_dmic,
5574 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5575 	SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
5576 			   wcd934x_codec_enable_dmic,
5577 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5578 	SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
5579 	SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
5580 	SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
5581 	SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
5582 	SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
5583 	SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
5584 	SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
5585 	SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
5586 	SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
5587 	SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
5588 	SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
5589 	SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
5590 	SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
5591 	SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
5592 	SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
5593 	SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
5594 	SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
5595 	SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
5596 	SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
5597 			   &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
5598 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5599 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5600 	SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
5601 			   &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
5602 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5603 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5604 	SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
5605 			   &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
5606 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5607 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5608 	SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
5609 			   &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
5610 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5611 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5612 	SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
5613 			   &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
5614 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5615 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5616 	SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
5617 			   &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
5618 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5619 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5620 	SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
5621 			   &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
5622 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5623 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5624 	SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
5625 			   &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
5626 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5627 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5628 	SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
5629 			   &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
5630 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5631 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5632 	SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
5633 			   wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5634 	SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
5635 			   wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5636 	SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
5637 			   wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5638 	SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
5639 			   wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5640 	SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
5641 			    wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5642 			    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5643 	SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
5644 			    wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5645 			    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5646 	SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
5647 			    wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5648 			    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5649 	SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
5650 			    wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5651 			    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5652 
5653 	SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
5654 	SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
5655 			 &cdc_if_tx0_mux),
5656 	SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
5657 			 &cdc_if_tx1_mux),
5658 	SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
5659 			 &cdc_if_tx2_mux),
5660 	SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
5661 			 &cdc_if_tx3_mux),
5662 	SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
5663 			 &cdc_if_tx4_mux),
5664 	SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
5665 			 &cdc_if_tx5_mux),
5666 	SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
5667 			 &cdc_if_tx6_mux),
5668 	SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
5669 			 &cdc_if_tx7_mux),
5670 	SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
5671 			 &cdc_if_tx8_mux),
5672 	SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
5673 			 &cdc_if_tx9_mux),
5674 	SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
5675 			 &cdc_if_tx10_mux),
5676 	SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5677 			 &cdc_if_tx11_mux),
5678 	SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5679 			 &cdc_if_tx11_inp1_mux),
5680 	SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5681 			 &cdc_if_tx13_mux),
5682 	SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5683 			 &cdc_if_tx13_inp1_mux),
5684 	SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
5685 			   aif1_slim_cap_mixer,
5686 			   ARRAY_SIZE(aif1_slim_cap_mixer)),
5687 	SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
5688 			   aif2_slim_cap_mixer,
5689 			   ARRAY_SIZE(aif2_slim_cap_mixer)),
5690 	SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
5691 			   aif3_slim_cap_mixer,
5692 			   ARRAY_SIZE(aif3_slim_cap_mixer)),
5693 };
5694 
5695 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
5696 	/* RX0-RX7 */
5697 	WCD934X_SLIM_RX_AIF_PATH(0),
5698 	WCD934X_SLIM_RX_AIF_PATH(1),
5699 	WCD934X_SLIM_RX_AIF_PATH(2),
5700 	WCD934X_SLIM_RX_AIF_PATH(3),
5701 	WCD934X_SLIM_RX_AIF_PATH(4),
5702 	WCD934X_SLIM_RX_AIF_PATH(5),
5703 	WCD934X_SLIM_RX_AIF_PATH(6),
5704 	WCD934X_SLIM_RX_AIF_PATH(7),
5705 
5706 	/* RX0 Ear out */
5707 	WCD934X_INTERPOLATOR_PATH(0),
5708 	WCD934X_INTERPOLATOR_MIX2(0),
5709 	{"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
5710 	{"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
5711 	{"RX INT0 DAC", NULL, "RX_BIAS"},
5712 	{"EAR PA", NULL, "RX INT0 DAC"},
5713 	{"EAR", NULL, "EAR PA"},
5714 
5715 	/* RX1 Headphone left */
5716 	WCD934X_INTERPOLATOR_PATH(1),
5717 	WCD934X_INTERPOLATOR_MIX2(1),
5718 	{"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
5719 	{"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
5720 	{"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
5721 	{"RX INT1 DAC", NULL, "RX_BIAS"},
5722 	{"HPHL PA", NULL, "RX INT1 DAC"},
5723 	{"HPHL", NULL, "HPHL PA"},
5724 
5725 	/* RX2 Headphone right */
5726 	WCD934X_INTERPOLATOR_PATH(2),
5727 	WCD934X_INTERPOLATOR_MIX2(2),
5728 	{"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
5729 	{"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
5730 	{"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
5731 	{"RX INT2 DAC", NULL, "RX_BIAS"},
5732 	{"HPHR PA", NULL, "RX INT2 DAC"},
5733 	{"HPHR", NULL, "HPHR PA"},
5734 
5735 	/* RX3 HIFi LineOut1 */
5736 	WCD934X_INTERPOLATOR_PATH(3),
5737 	WCD934X_INTERPOLATOR_MIX2(3),
5738 	{"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
5739 	{"RX INT3 DAC", NULL, "RX INT3 MIX3"},
5740 	{"RX INT3 DAC", NULL, "RX_BIAS"},
5741 	{"LINEOUT1 PA", NULL, "RX INT3 DAC"},
5742 	{"LINEOUT1", NULL, "LINEOUT1 PA"},
5743 
5744 	/* RX4 HIFi LineOut2 */
5745 	WCD934X_INTERPOLATOR_PATH(4),
5746 	WCD934X_INTERPOLATOR_MIX2(4),
5747 	{"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
5748 	{"RX INT4 DAC", NULL, "RX INT4 MIX3"},
5749 	{"RX INT4 DAC", NULL, "RX_BIAS"},
5750 	{"LINEOUT2 PA", NULL, "RX INT4 DAC"},
5751 	{"LINEOUT2", NULL, "LINEOUT2 PA"},
5752 
5753 	/* RX7 Speaker Left Out PA */
5754 	WCD934X_INTERPOLATOR_PATH(7),
5755 	WCD934X_INTERPOLATOR_MIX2(7),
5756 	{"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
5757 	{"RX INT7 CHAIN", NULL, "RX_BIAS"},
5758 	{"RX INT7 CHAIN", NULL, "SBOOST0"},
5759 	{"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
5760 	{"SPK1 OUT", NULL, "RX INT7 CHAIN"},
5761 
5762 	/* RX8 Speaker Right Out PA */
5763 	WCD934X_INTERPOLATOR_PATH(8),
5764 	{"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
5765 	{"RX INT8 CHAIN", NULL, "RX_BIAS"},
5766 	{"RX INT8 CHAIN", NULL, "SBOOST1"},
5767 	{"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
5768 	{"SPK2 OUT", NULL, "RX INT8 CHAIN"},
5769 
5770 	/* Tx */
5771 	{"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
5772 	{"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
5773 	{"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
5774 
5775 	WCD934X_SLIM_TX_AIF_PATH(0),
5776 	WCD934X_SLIM_TX_AIF_PATH(1),
5777 	WCD934X_SLIM_TX_AIF_PATH(2),
5778 	WCD934X_SLIM_TX_AIF_PATH(3),
5779 	WCD934X_SLIM_TX_AIF_PATH(4),
5780 	WCD934X_SLIM_TX_AIF_PATH(5),
5781 	WCD934X_SLIM_TX_AIF_PATH(6),
5782 	WCD934X_SLIM_TX_AIF_PATH(7),
5783 	WCD934X_SLIM_TX_AIF_PATH(8),
5784 
5785 	WCD934X_ADC_MUX(0),
5786 	WCD934X_ADC_MUX(1),
5787 	WCD934X_ADC_MUX(2),
5788 	WCD934X_ADC_MUX(3),
5789 	WCD934X_ADC_MUX(4),
5790 	WCD934X_ADC_MUX(5),
5791 	WCD934X_ADC_MUX(6),
5792 	WCD934X_ADC_MUX(7),
5793 	WCD934X_ADC_MUX(8),
5794 
5795 	{"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
5796 	{"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
5797 	{"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
5798 	{"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
5799 	{"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
5800 	{"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
5801 	{"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
5802 	{"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
5803 	{"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
5804 
5805 	{"AMIC4_5 SEL", "AMIC4", "AMIC4"},
5806 	{"AMIC4_5 SEL", "AMIC5", "AMIC5"},
5807 
5808 	{ "DMIC0", NULL, "DMIC0 Pin" },
5809 	{ "DMIC1", NULL, "DMIC1 Pin" },
5810 	{ "DMIC2", NULL, "DMIC2 Pin" },
5811 	{ "DMIC3", NULL, "DMIC3 Pin" },
5812 	{ "DMIC4", NULL, "DMIC4 Pin" },
5813 	{ "DMIC5", NULL, "DMIC5 Pin" },
5814 
5815 	{"ADC1", NULL, "AMIC1"},
5816 	{"ADC2", NULL, "AMIC2"},
5817 	{"ADC3", NULL, "AMIC3"},
5818 	{"ADC4", NULL, "AMIC4_5 SEL"},
5819 
5820 	WCD934X_IIR_INP_MUX(0),
5821 	WCD934X_IIR_INP_MUX(1),
5822 
5823 	{"SRC0", NULL, "IIR0"},
5824 	{"SRC1", NULL, "IIR1"},
5825 };
5826 
wcd934x_codec_set_jack(struct snd_soc_component * comp,struct snd_soc_jack * jack,void * data)5827 static int wcd934x_codec_set_jack(struct snd_soc_component *comp,
5828 				  struct snd_soc_jack *jack, void *data)
5829 {
5830 	struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
5831 	int ret = 0;
5832 
5833 	if (!wcd->mbhc)
5834 		return -ENOTSUPP;
5835 
5836 	if (jack && !wcd->mbhc_started) {
5837 		ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack);
5838 		wcd->mbhc_started = true;
5839 	} else if (wcd->mbhc_started) {
5840 		wcd_mbhc_stop(wcd->mbhc);
5841 		wcd->mbhc_started = false;
5842 	}
5843 
5844 	return ret;
5845 }
5846 
5847 static const struct snd_soc_component_driver wcd934x_component_drv = {
5848 	.probe = wcd934x_comp_probe,
5849 	.remove = wcd934x_comp_remove,
5850 	.set_sysclk = wcd934x_comp_set_sysclk,
5851 	.controls = wcd934x_snd_controls,
5852 	.num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5853 	.dapm_widgets = wcd934x_dapm_widgets,
5854 	.num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5855 	.dapm_routes = wcd934x_audio_map,
5856 	.num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5857 	.set_jack = wcd934x_codec_set_jack,
5858 	.endianness = 1,
5859 };
5860 
wcd934x_codec_parse_data(struct wcd934x_codec * wcd)5861 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5862 {
5863 	struct device *dev = &wcd->sdev->dev;
5864 	struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg;
5865 	struct device_node *ifc_dev_np;
5866 
5867 	ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5868 	if (!ifc_dev_np) {
5869 		dev_err(dev, "No Interface device found\n");
5870 		return -EINVAL;
5871 	}
5872 
5873 	wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5874 	of_node_put(ifc_dev_np);
5875 	if (!wcd->sidev) {
5876 		dev_err(dev, "Unable to get SLIM Interface device\n");
5877 		return -EINVAL;
5878 	}
5879 
5880 	slim_get_logical_addr(wcd->sidev);
5881 	wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5882 				  &wcd934x_ifc_regmap_config);
5883 	if (IS_ERR(wcd->if_regmap))
5884 		return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5885 				     "Failed to allocate ifc register map\n");
5886 
5887 	of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5888 			     &wcd->dmic_sample_rate);
5889 
5890 	cfg->mbhc_micbias = MIC_BIAS_2;
5891 	cfg->anc_micbias = MIC_BIAS_2;
5892 	cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
5893 	cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS;
5894 	cfg->micb_mv = wcd->micb2_mv;
5895 	cfg->linein_th = 5000;
5896 	cfg->hs_thr = 1700;
5897 	cfg->hph_thr = 50;
5898 
5899 	wcd_dt_parse_mbhc_data(dev, cfg);
5900 
5901 
5902 	return 0;
5903 }
5904 
wcd934x_codec_probe(struct platform_device * pdev)5905 static int wcd934x_codec_probe(struct platform_device *pdev)
5906 {
5907 	struct device *dev = &pdev->dev;
5908 	struct wcd934x_ddata *data = dev_get_drvdata(dev->parent);
5909 	struct wcd934x_codec *wcd;
5910 	int ret, irq;
5911 
5912 	wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5913 	if (!wcd)
5914 		return -ENOMEM;
5915 
5916 	wcd->dev = dev;
5917 	wcd->regmap = data->regmap;
5918 	wcd->extclk = data->extclk;
5919 	wcd->sdev = to_slim_device(data->dev);
5920 	mutex_init(&wcd->sysclk_mutex);
5921 	mutex_init(&wcd->micb_lock);
5922 
5923 	ret = wcd934x_codec_parse_data(wcd);
5924 	if (ret) {
5925 		dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5926 		return ret;
5927 	}
5928 
5929 	/* set default rate 9P6MHz */
5930 	regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5931 			   WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5932 			   WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5933 	memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5934 	memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5935 
5936 	irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5937 	if (irq < 0)
5938 		return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n");
5939 
5940 	ret = devm_request_threaded_irq(dev, irq, NULL,
5941 					wcd934x_slim_irq_handler,
5942 					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5943 					"slim", wcd);
5944 	if (ret)
5945 		return dev_err_probe(dev, ret, "Failed to request slimbus irq\n");
5946 
5947 	wcd934x_register_mclk_output(wcd);
5948 	platform_set_drvdata(pdev, wcd);
5949 
5950 	return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5951 					       wcd934x_slim_dais,
5952 					       ARRAY_SIZE(wcd934x_slim_dais));
5953 }
5954 
5955 static const struct platform_device_id wcd934x_driver_id[] = {
5956 	{
5957 		.name = "wcd934x-codec",
5958 	},
5959 	{},
5960 };
5961 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5962 
5963 static struct platform_driver wcd934x_codec_driver = {
5964 	.probe	= &wcd934x_codec_probe,
5965 	.id_table = wcd934x_driver_id,
5966 	.driver = {
5967 		.name	= "wcd934x-codec",
5968 	}
5969 };
5970 
5971 MODULE_ALIAS("platform:wcd934x-codec");
5972 module_platform_driver(wcd934x_codec_driver);
5973 MODULE_DESCRIPTION("WCD934x codec driver");
5974 MODULE_LICENSE("GPL v2");
5975