1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Xilinx AXI platforms watchdog timer driver.
4  *
5  * Author(s):	Michal Simek <michal.simek@xilinx.com>
6  *		Shreenidhi Shedi <yesshedi@gmail.com>
7  *
8  * Copyright (c) 2011-2018 Xilinx Inc.
9  */
10 
11 #include <common.h>
12 #include <dm.h>
13 #include <wdt.h>
14 #include <linux/io.h>
15 
16 #define XWT_CSR0_WRS_MASK	0x00000008 /* Reset status Mask */
17 #define XWT_CSR0_WDS_MASK	0x00000004 /* Timer state Mask */
18 #define XWT_CSR0_EWDT1_MASK	0x00000002 /* Enable bit 1 Mask*/
19 #define XWT_CSRX_EWDT2_MASK	0x00000001 /* Enable bit 2 Mask */
20 
21 struct watchdog_regs {
22 	u32 twcsr0; /* 0x0 */
23 	u32 twcsr1; /* 0x4 */
24 	u32 tbr; /* 0x8 */
25 };
26 
27 struct xlnx_wdt_platdata {
28 	bool enable_once;
29 	struct watchdog_regs *regs;
30 };
31 
xlnx_wdt_reset(struct udevice * dev)32 static int xlnx_wdt_reset(struct udevice *dev)
33 {
34 	u32 reg;
35 	struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
36 
37 	debug("%s ", __func__);
38 
39 	/* Read the current contents of TCSR0 */
40 	reg = readl(&platdata->regs->twcsr0);
41 
42 	/* Clear the watchdog WDS bit */
43 	if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
44 		writel(reg | XWT_CSR0_WDS_MASK, &platdata->regs->twcsr0);
45 
46 	return 0;
47 }
48 
xlnx_wdt_stop(struct udevice * dev)49 static int xlnx_wdt_stop(struct udevice *dev)
50 {
51 	u32 reg;
52 	struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
53 
54 	if (platdata->enable_once) {
55 		debug("Can't stop Xilinx watchdog.\n");
56 		return -EBUSY;
57 	}
58 
59 	/* Read the current contents of TCSR0 */
60 	reg = readl(&platdata->regs->twcsr0);
61 
62 	writel(reg & ~XWT_CSR0_EWDT1_MASK, &platdata->regs->twcsr0);
63 	writel(~XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
64 
65 	debug("Watchdog disabled!\n");
66 
67 	return 0;
68 }
69 
xlnx_wdt_start(struct udevice * dev,u64 timeout,ulong flags)70 static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
71 {
72 	struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
73 
74 	debug("%s:\n", __func__);
75 
76 	writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
77 	       &platdata->regs->twcsr0);
78 
79 	writel(XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
80 
81 	return 0;
82 }
83 
xlnx_wdt_probe(struct udevice * dev)84 static int xlnx_wdt_probe(struct udevice *dev)
85 {
86 	debug("%s: Probing wdt%u\n", __func__, dev->seq);
87 
88 	return 0;
89 }
90 
xlnx_wdt_ofdata_to_platdata(struct udevice * dev)91 static int xlnx_wdt_ofdata_to_platdata(struct udevice *dev)
92 {
93 	struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
94 
95 	platdata->regs = (struct watchdog_regs *)dev_read_addr(dev);
96 	if (IS_ERR(platdata->regs))
97 		return PTR_ERR(platdata->regs);
98 
99 	platdata->enable_once = dev_read_u32_default(dev,
100 						     "xlnx,wdt-enable-once", 0);
101 
102 	debug("%s: wdt-enable-once %d\n", __func__, platdata->enable_once);
103 
104 	return 0;
105 }
106 
107 static const struct wdt_ops xlnx_wdt_ops = {
108 	.start = xlnx_wdt_start,
109 	.reset = xlnx_wdt_reset,
110 	.stop = xlnx_wdt_stop,
111 };
112 
113 static const struct udevice_id xlnx_wdt_ids[] = {
114 	{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
115 	{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
116 	{},
117 };
118 
119 U_BOOT_DRIVER(xlnx_wdt) = {
120 	.name = "xlnx_wdt",
121 	.id = UCLASS_WDT,
122 	.of_match = xlnx_wdt_ids,
123 	.probe = xlnx_wdt_probe,
124 	.platdata_auto_alloc_size = sizeof(struct xlnx_wdt_platdata),
125 	.ofdata_to_platdata = xlnx_wdt_ofdata_to_platdata,
126 	.ops = &xlnx_wdt_ops,
127 };
128