1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * tw68 functions to handle video data
4 *
5 * Much of this code is derived from the cx88 and sa7134 drivers, which
6 * were in turn derived from the bt87x driver. The original work was by
7 * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
8 * Hans Verkuil, Andy Walls and many others. Their work is gratefully
9 * acknowledged. Full credit goes to them - any problems within this code
10 * are mine.
11 *
12 * Copyright (C) 2009 William M. Brack
13 *
14 * Refactored and updated to the latest v4l core frameworks:
15 *
16 * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
17 */
18
19 #include <linux/module.h>
20 #include <media/v4l2-common.h>
21 #include <media/v4l2-event.h>
22 #include <media/videobuf2-dma-sg.h>
23
24 #include "tw68.h"
25 #include "tw68-reg.h"
26
27 /* ------------------------------------------------------------------ */
28 /* data structs for video */
29 /*
30 * FIXME -
31 * Note that the saa7134 has formats, e.g. YUV420, which are classified
32 * as "planar". These affect overlay mode, and are flagged with a field
33 * ".planar" in the format. Do we need to implement this in this driver?
34 */
35 static const struct tw68_format formats[] = {
36 {
37 .fourcc = V4L2_PIX_FMT_RGB555,
38 .depth = 16,
39 .twformat = ColorFormatRGB15,
40 }, {
41 .fourcc = V4L2_PIX_FMT_RGB555X,
42 .depth = 16,
43 .twformat = ColorFormatRGB15 | ColorFormatBSWAP,
44 }, {
45 .fourcc = V4L2_PIX_FMT_RGB565,
46 .depth = 16,
47 .twformat = ColorFormatRGB16,
48 }, {
49 .fourcc = V4L2_PIX_FMT_RGB565X,
50 .depth = 16,
51 .twformat = ColorFormatRGB16 | ColorFormatBSWAP,
52 }, {
53 .fourcc = V4L2_PIX_FMT_BGR24,
54 .depth = 24,
55 .twformat = ColorFormatRGB24,
56 }, {
57 .fourcc = V4L2_PIX_FMT_RGB24,
58 .depth = 24,
59 .twformat = ColorFormatRGB24 | ColorFormatBSWAP,
60 }, {
61 .fourcc = V4L2_PIX_FMT_BGR32,
62 .depth = 32,
63 .twformat = ColorFormatRGB32,
64 }, {
65 .fourcc = V4L2_PIX_FMT_RGB32,
66 .depth = 32,
67 .twformat = ColorFormatRGB32 | ColorFormatBSWAP |
68 ColorFormatWSWAP,
69 }, {
70 .fourcc = V4L2_PIX_FMT_YUYV,
71 .depth = 16,
72 .twformat = ColorFormatYUY2,
73 }, {
74 .fourcc = V4L2_PIX_FMT_UYVY,
75 .depth = 16,
76 .twformat = ColorFormatYUY2 | ColorFormatBSWAP,
77 }
78 };
79 #define FORMATS ARRAY_SIZE(formats)
80
81 #define NORM_625_50 \
82 .h_delay = 3, \
83 .h_delay0 = 133, \
84 .h_start = 0, \
85 .h_stop = 719, \
86 .v_delay = 24, \
87 .vbi_v_start_0 = 7, \
88 .vbi_v_stop_0 = 22, \
89 .video_v_start = 24, \
90 .video_v_stop = 311, \
91 .vbi_v_start_1 = 319
92
93 #define NORM_525_60 \
94 .h_delay = 8, \
95 .h_delay0 = 138, \
96 .h_start = 0, \
97 .h_stop = 719, \
98 .v_delay = 22, \
99 .vbi_v_start_0 = 10, \
100 .vbi_v_stop_0 = 21, \
101 .video_v_start = 22, \
102 .video_v_stop = 262, \
103 .vbi_v_start_1 = 273
104
105 /*
106 * The following table is searched by tw68_s_std, first for a specific
107 * match, then for an entry which contains the desired id. The table
108 * entries should therefore be ordered in ascending order of specificity.
109 */
110 static const struct tw68_tvnorm tvnorms[] = {
111 {
112 .name = "PAL", /* autodetect */
113 .id = V4L2_STD_PAL,
114 NORM_625_50,
115
116 .sync_control = 0x18,
117 .luma_control = 0x40,
118 .chroma_ctrl1 = 0x81,
119 .chroma_gain = 0x2a,
120 .chroma_ctrl2 = 0x06,
121 .vgate_misc = 0x1c,
122 .format = VideoFormatPALBDGHI,
123 }, {
124 .name = "NTSC",
125 .id = V4L2_STD_NTSC,
126 NORM_525_60,
127
128 .sync_control = 0x59,
129 .luma_control = 0x40,
130 .chroma_ctrl1 = 0x89,
131 .chroma_gain = 0x2a,
132 .chroma_ctrl2 = 0x0e,
133 .vgate_misc = 0x18,
134 .format = VideoFormatNTSC,
135 }, {
136 .name = "SECAM",
137 .id = V4L2_STD_SECAM,
138 NORM_625_50,
139
140 .sync_control = 0x18,
141 .luma_control = 0x1b,
142 .chroma_ctrl1 = 0xd1,
143 .chroma_gain = 0x80,
144 .chroma_ctrl2 = 0x00,
145 .vgate_misc = 0x1c,
146 .format = VideoFormatSECAM,
147 }, {
148 .name = "PAL-M",
149 .id = V4L2_STD_PAL_M,
150 NORM_525_60,
151
152 .sync_control = 0x59,
153 .luma_control = 0x40,
154 .chroma_ctrl1 = 0xb9,
155 .chroma_gain = 0x2a,
156 .chroma_ctrl2 = 0x0e,
157 .vgate_misc = 0x18,
158 .format = VideoFormatPALM,
159 }, {
160 .name = "PAL-Nc",
161 .id = V4L2_STD_PAL_Nc,
162 NORM_625_50,
163
164 .sync_control = 0x18,
165 .luma_control = 0x40,
166 .chroma_ctrl1 = 0xa1,
167 .chroma_gain = 0x2a,
168 .chroma_ctrl2 = 0x06,
169 .vgate_misc = 0x1c,
170 .format = VideoFormatPALNC,
171 }, {
172 .name = "PAL-60",
173 .id = V4L2_STD_PAL_60,
174 .h_delay = 186,
175 .h_start = 0,
176 .h_stop = 719,
177 .v_delay = 26,
178 .video_v_start = 23,
179 .video_v_stop = 262,
180 .vbi_v_start_0 = 10,
181 .vbi_v_stop_0 = 21,
182 .vbi_v_start_1 = 273,
183
184 .sync_control = 0x18,
185 .luma_control = 0x40,
186 .chroma_ctrl1 = 0x81,
187 .chroma_gain = 0x2a,
188 .chroma_ctrl2 = 0x06,
189 .vgate_misc = 0x1c,
190 .format = VideoFormatPAL60,
191 }
192 };
193 #define TVNORMS ARRAY_SIZE(tvnorms)
194
format_by_fourcc(unsigned int fourcc)195 static const struct tw68_format *format_by_fourcc(unsigned int fourcc)
196 {
197 unsigned int i;
198
199 for (i = 0; i < FORMATS; i++)
200 if (formats[i].fourcc == fourcc)
201 return formats+i;
202 return NULL;
203 }
204
205
206 /* ------------------------------------------------------------------ */
207 /*
208 * Note that the cropping rectangles are described in terms of a single
209 * frame, i.e. line positions are only 1/2 the interlaced equivalent
210 */
set_tvnorm(struct tw68_dev * dev,const struct tw68_tvnorm * norm)211 static void set_tvnorm(struct tw68_dev *dev, const struct tw68_tvnorm *norm)
212 {
213 if (norm != dev->tvnorm) {
214 dev->width = 720;
215 dev->height = (norm->id & V4L2_STD_525_60) ? 480 : 576;
216 dev->tvnorm = norm;
217 tw68_set_tvnorm_hw(dev);
218 }
219 }
220
221 /*
222 * tw68_set_scale
223 *
224 * Scaling and Cropping for video decoding
225 *
226 * We are working with 3 values for horizontal and vertical - scale,
227 * delay and active.
228 *
229 * HACTIVE represent the actual number of pixels in the "usable" image,
230 * before scaling. HDELAY represents the number of pixels skipped
231 * between the start of the horizontal sync and the start of the image.
232 * HSCALE is calculated using the formula
233 * HSCALE = (HACTIVE / (#pixels desired)) * 256
234 *
235 * The vertical registers are similar, except based upon the total number
236 * of lines in the image, and the first line of the image (i.e. ignoring
237 * vertical sync and VBI).
238 *
239 * Note that the number of bytes reaching the FIFO (and hence needing
240 * to be processed by the DMAP program) is completely dependent upon
241 * these values, especially HSCALE.
242 *
243 * Parameters:
244 * @dev pointer to the device structure, needed for
245 * getting current norm (as well as debug print)
246 * @width actual image width (from user buffer)
247 * @height actual image height
248 * @field indicates Top, Bottom or Interlaced
249 */
tw68_set_scale(struct tw68_dev * dev,unsigned int width,unsigned int height,enum v4l2_field field)250 static int tw68_set_scale(struct tw68_dev *dev, unsigned int width,
251 unsigned int height, enum v4l2_field field)
252 {
253 const struct tw68_tvnorm *norm = dev->tvnorm;
254 /* set individually for debugging clarity */
255 int hactive, hdelay, hscale;
256 int vactive, vdelay, vscale;
257 int comb;
258
259 if (V4L2_FIELD_HAS_BOTH(field)) /* if field is interlaced */
260 height /= 2; /* we must set for 1-frame */
261
262 pr_debug("%s: width=%d, height=%d, both=%d\n"
263 " tvnorm h_delay=%d, h_start=%d, h_stop=%d, v_delay=%d, v_start=%d, v_stop=%d\n",
264 __func__, width, height, V4L2_FIELD_HAS_BOTH(field),
265 norm->h_delay, norm->h_start, norm->h_stop,
266 norm->v_delay, norm->video_v_start,
267 norm->video_v_stop);
268
269 switch (dev->vdecoder) {
270 case TW6800:
271 hdelay = norm->h_delay0;
272 break;
273 default:
274 hdelay = norm->h_delay;
275 break;
276 }
277
278 hdelay += norm->h_start;
279 hactive = norm->h_stop - norm->h_start + 1;
280
281 hscale = (hactive * 256) / (width);
282
283 vdelay = norm->v_delay;
284 vactive = ((norm->id & V4L2_STD_525_60) ? 524 : 624) / 2 - norm->video_v_start;
285 vscale = (vactive * 256) / height;
286
287 pr_debug("%s: %dx%d [%s%s,%s]\n", __func__,
288 width, height,
289 V4L2_FIELD_HAS_TOP(field) ? "T" : "",
290 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
291 v4l2_norm_to_name(dev->tvnorm->id));
292 pr_debug("%s: hactive=%d, hdelay=%d, hscale=%d; vactive=%d, vdelay=%d, vscale=%d\n",
293 __func__,
294 hactive, hdelay, hscale, vactive, vdelay, vscale);
295
296 comb = ((vdelay & 0x300) >> 2) |
297 ((vactive & 0x300) >> 4) |
298 ((hdelay & 0x300) >> 6) |
299 ((hactive & 0x300) >> 8);
300 pr_debug("%s: setting CROP_HI=%02x, VDELAY_LO=%02x, VACTIVE_LO=%02x, HDELAY_LO=%02x, HACTIVE_LO=%02x\n",
301 __func__, comb, vdelay, vactive, hdelay, hactive);
302 tw_writeb(TW68_CROP_HI, comb);
303 tw_writeb(TW68_VDELAY_LO, vdelay & 0xff);
304 tw_writeb(TW68_VACTIVE_LO, vactive & 0xff);
305 tw_writeb(TW68_HDELAY_LO, hdelay & 0xff);
306 tw_writeb(TW68_HACTIVE_LO, hactive & 0xff);
307
308 comb = ((vscale & 0xf00) >> 4) | ((hscale & 0xf00) >> 8);
309 pr_debug("%s: setting SCALE_HI=%02x, VSCALE_LO=%02x, HSCALE_LO=%02x\n",
310 __func__, comb, vscale, hscale);
311 tw_writeb(TW68_SCALE_HI, comb);
312 tw_writeb(TW68_VSCALE_LO, vscale);
313 tw_writeb(TW68_HSCALE_LO, hscale);
314
315 return 0;
316 }
317
318 /* ------------------------------------------------------------------ */
319
tw68_video_start_dma(struct tw68_dev * dev,struct tw68_buf * buf)320 int tw68_video_start_dma(struct tw68_dev *dev, struct tw68_buf *buf)
321 {
322 /* Set cropping and scaling */
323 tw68_set_scale(dev, dev->width, dev->height, dev->field);
324 /*
325 * Set start address for RISC program. Note that if the DMAP
326 * processor is currently running, it must be stopped before
327 * a new address can be set.
328 */
329 tw_clearl(TW68_DMAC, TW68_DMAP_EN);
330 tw_writel(TW68_DMAP_SA, buf->dma);
331 /* Clear any pending interrupts */
332 tw_writel(TW68_INTSTAT, dev->board_virqmask);
333 /* Enable the risc engine and the fifo */
334 tw_andorl(TW68_DMAC, 0xff, dev->fmt->twformat |
335 ColorFormatGamma | TW68_DMAP_EN | TW68_FIFO_EN);
336 dev->pci_irqmask |= dev->board_virqmask;
337 tw_setl(TW68_INTMASK, dev->pci_irqmask);
338 return 0;
339 }
340
341 /* ------------------------------------------------------------------ */
342
343 /* calc max # of buffers from size (must not exceed the 4MB virtual
344 * address space per DMA channel) */
tw68_buffer_count(unsigned int size,unsigned int count)345 static int tw68_buffer_count(unsigned int size, unsigned int count)
346 {
347 unsigned int maxcount;
348
349 maxcount = (4 * 1024 * 1024) / roundup(size, PAGE_SIZE);
350 if (count > maxcount)
351 count = maxcount;
352 return count;
353 }
354
355 /* ------------------------------------------------------------- */
356 /* vb2 queue operations */
357
tw68_queue_setup(struct vb2_queue * q,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])358 static int tw68_queue_setup(struct vb2_queue *q,
359 unsigned int *num_buffers, unsigned int *num_planes,
360 unsigned int sizes[], struct device *alloc_devs[])
361 {
362 struct tw68_dev *dev = vb2_get_drv_priv(q);
363 unsigned tot_bufs = q->num_buffers + *num_buffers;
364 unsigned size = (dev->fmt->depth * dev->width * dev->height) >> 3;
365
366 if (tot_bufs < 2)
367 tot_bufs = 2;
368 tot_bufs = tw68_buffer_count(size, tot_bufs);
369 *num_buffers = tot_bufs - q->num_buffers;
370 /*
371 * We allow create_bufs, but only if the sizeimage is >= as the
372 * current sizeimage. The tw68_buffer_count calculation becomes quite
373 * difficult otherwise.
374 */
375 if (*num_planes)
376 return sizes[0] < size ? -EINVAL : 0;
377 *num_planes = 1;
378 sizes[0] = size;
379
380 return 0;
381 }
382
383 /*
384 * The risc program for each buffers works as follows: it starts with a simple
385 * 'JUMP to addr + 8', which is effectively a NOP. Then the program to DMA the
386 * buffer follows and at the end we have a JUMP back to the start + 8 (skipping
387 * the initial JUMP).
388 *
389 * This is the program of the first buffer to be queued if the active list is
390 * empty and it just keeps DMAing this buffer without generating any interrupts.
391 *
392 * If a new buffer is added then the initial JUMP in the program generates an
393 * interrupt as well which signals that the previous buffer has been DMAed
394 * successfully and that it can be returned to userspace.
395 *
396 * It also sets the final jump of the previous buffer to the start of the new
397 * buffer, thus chaining the new buffer into the DMA chain. This is a single
398 * atomic u32 write, so there is no race condition.
399 *
400 * The end-result of all this that you only get an interrupt when a buffer
401 * is ready, so the control flow is very easy.
402 */
tw68_buf_queue(struct vb2_buffer * vb)403 static void tw68_buf_queue(struct vb2_buffer *vb)
404 {
405 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
406 struct vb2_queue *vq = vb->vb2_queue;
407 struct tw68_dev *dev = vb2_get_drv_priv(vq);
408 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
409 struct tw68_buf *prev;
410 unsigned long flags;
411
412 spin_lock_irqsave(&dev->slock, flags);
413
414 /* append a 'JUMP to start of buffer' to the buffer risc program */
415 buf->jmp[0] = cpu_to_le32(RISC_JUMP);
416 buf->jmp[1] = cpu_to_le32(buf->dma + 8);
417
418 if (!list_empty(&dev->active)) {
419 prev = list_entry(dev->active.prev, struct tw68_buf, list);
420 buf->cpu[0] |= cpu_to_le32(RISC_INT_BIT);
421 prev->jmp[1] = cpu_to_le32(buf->dma);
422 }
423 list_add_tail(&buf->list, &dev->active);
424 spin_unlock_irqrestore(&dev->slock, flags);
425 }
426
427 /*
428 * buffer_prepare
429 *
430 * Set the ancillary information into the buffer structure. This
431 * includes generating the necessary risc program if it hasn't already
432 * been done for the current buffer format.
433 * The structure fh contains the details of the format requested by the
434 * user - type, width, height and #fields. This is compared with the
435 * last format set for the current buffer. If they differ, the risc
436 * code (which controls the filling of the buffer) is (re-)generated.
437 */
tw68_buf_prepare(struct vb2_buffer * vb)438 static int tw68_buf_prepare(struct vb2_buffer *vb)
439 {
440 int ret;
441 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
442 struct vb2_queue *vq = vb->vb2_queue;
443 struct tw68_dev *dev = vb2_get_drv_priv(vq);
444 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
445 struct sg_table *dma = vb2_dma_sg_plane_desc(vb, 0);
446 unsigned size, bpl;
447
448 size = (dev->width * dev->height * dev->fmt->depth) >> 3;
449 if (vb2_plane_size(vb, 0) < size)
450 return -EINVAL;
451 vb2_set_plane_payload(vb, 0, size);
452
453 bpl = (dev->width * dev->fmt->depth) >> 3;
454 switch (dev->field) {
455 case V4L2_FIELD_TOP:
456 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
457 0, UNSET, bpl, 0, dev->height);
458 break;
459 case V4L2_FIELD_BOTTOM:
460 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
461 UNSET, 0, bpl, 0, dev->height);
462 break;
463 case V4L2_FIELD_SEQ_TB:
464 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
465 0, bpl * (dev->height >> 1),
466 bpl, 0, dev->height >> 1);
467 break;
468 case V4L2_FIELD_SEQ_BT:
469 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
470 bpl * (dev->height >> 1), 0,
471 bpl, 0, dev->height >> 1);
472 break;
473 case V4L2_FIELD_INTERLACED:
474 default:
475 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
476 0, bpl, bpl, bpl, dev->height >> 1);
477 break;
478 }
479 return ret;
480 }
481
tw68_buf_finish(struct vb2_buffer * vb)482 static void tw68_buf_finish(struct vb2_buffer *vb)
483 {
484 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
485 struct vb2_queue *vq = vb->vb2_queue;
486 struct tw68_dev *dev = vb2_get_drv_priv(vq);
487 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
488
489 if (buf->cpu)
490 dma_free_coherent(&dev->pci->dev, buf->size, buf->cpu, buf->dma);
491 }
492
tw68_start_streaming(struct vb2_queue * q,unsigned int count)493 static int tw68_start_streaming(struct vb2_queue *q, unsigned int count)
494 {
495 struct tw68_dev *dev = vb2_get_drv_priv(q);
496 struct tw68_buf *buf =
497 container_of(dev->active.next, struct tw68_buf, list);
498
499 dev->seqnr = 0;
500 tw68_video_start_dma(dev, buf);
501 return 0;
502 }
503
tw68_stop_streaming(struct vb2_queue * q)504 static void tw68_stop_streaming(struct vb2_queue *q)
505 {
506 struct tw68_dev *dev = vb2_get_drv_priv(q);
507
508 /* Stop risc & fifo */
509 tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN);
510 while (!list_empty(&dev->active)) {
511 struct tw68_buf *buf =
512 container_of(dev->active.next, struct tw68_buf, list);
513
514 list_del(&buf->list);
515 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
516 }
517 }
518
519 static const struct vb2_ops tw68_video_qops = {
520 .queue_setup = tw68_queue_setup,
521 .buf_queue = tw68_buf_queue,
522 .buf_prepare = tw68_buf_prepare,
523 .buf_finish = tw68_buf_finish,
524 .start_streaming = tw68_start_streaming,
525 .stop_streaming = tw68_stop_streaming,
526 .wait_prepare = vb2_ops_wait_prepare,
527 .wait_finish = vb2_ops_wait_finish,
528 };
529
530 /* ------------------------------------------------------------------ */
531
tw68_s_ctrl(struct v4l2_ctrl * ctrl)532 static int tw68_s_ctrl(struct v4l2_ctrl *ctrl)
533 {
534 struct tw68_dev *dev =
535 container_of(ctrl->handler, struct tw68_dev, hdl);
536
537 switch (ctrl->id) {
538 case V4L2_CID_BRIGHTNESS:
539 tw_writeb(TW68_BRIGHT, ctrl->val);
540 break;
541 case V4L2_CID_HUE:
542 tw_writeb(TW68_HUE, ctrl->val);
543 break;
544 case V4L2_CID_CONTRAST:
545 tw_writeb(TW68_CONTRAST, ctrl->val);
546 break;
547 case V4L2_CID_SATURATION:
548 tw_writeb(TW68_SAT_U, ctrl->val);
549 tw_writeb(TW68_SAT_V, ctrl->val);
550 break;
551 case V4L2_CID_COLOR_KILLER:
552 if (ctrl->val)
553 tw_andorb(TW68_MISC2, 0xe0, 0xe0);
554 else
555 tw_andorb(TW68_MISC2, 0xe0, 0x00);
556 break;
557 case V4L2_CID_CHROMA_AGC:
558 if (ctrl->val)
559 tw_andorb(TW68_LOOP, 0x30, 0x20);
560 else
561 tw_andorb(TW68_LOOP, 0x30, 0x00);
562 break;
563 }
564 return 0;
565 }
566
567 /* ------------------------------------------------------------------ */
568
569 /*
570 * Note that this routine returns what is stored in the fh structure, and
571 * does not interrogate any of the device registers.
572 */
tw68_g_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)573 static int tw68_g_fmt_vid_cap(struct file *file, void *priv,
574 struct v4l2_format *f)
575 {
576 struct tw68_dev *dev = video_drvdata(file);
577
578 f->fmt.pix.width = dev->width;
579 f->fmt.pix.height = dev->height;
580 f->fmt.pix.field = dev->field;
581 f->fmt.pix.pixelformat = dev->fmt->fourcc;
582 f->fmt.pix.bytesperline =
583 (f->fmt.pix.width * (dev->fmt->depth)) >> 3;
584 f->fmt.pix.sizeimage =
585 f->fmt.pix.height * f->fmt.pix.bytesperline;
586 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
587 return 0;
588 }
589
tw68_try_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)590 static int tw68_try_fmt_vid_cap(struct file *file, void *priv,
591 struct v4l2_format *f)
592 {
593 struct tw68_dev *dev = video_drvdata(file);
594 const struct tw68_format *fmt;
595 enum v4l2_field field;
596 unsigned int maxh;
597
598 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
599 if (NULL == fmt)
600 return -EINVAL;
601
602 field = f->fmt.pix.field;
603 maxh = (dev->tvnorm->id & V4L2_STD_525_60) ? 480 : 576;
604
605 switch (field) {
606 case V4L2_FIELD_TOP:
607 case V4L2_FIELD_BOTTOM:
608 break;
609 case V4L2_FIELD_INTERLACED:
610 case V4L2_FIELD_SEQ_BT:
611 case V4L2_FIELD_SEQ_TB:
612 maxh = maxh * 2;
613 break;
614 default:
615 field = (f->fmt.pix.height > maxh / 2)
616 ? V4L2_FIELD_INTERLACED
617 : V4L2_FIELD_BOTTOM;
618 break;
619 }
620
621 f->fmt.pix.field = field;
622 if (f->fmt.pix.width < 48)
623 f->fmt.pix.width = 48;
624 if (f->fmt.pix.height < 32)
625 f->fmt.pix.height = 32;
626 if (f->fmt.pix.width > 720)
627 f->fmt.pix.width = 720;
628 if (f->fmt.pix.height > maxh)
629 f->fmt.pix.height = maxh;
630 f->fmt.pix.width &= ~0x03;
631 f->fmt.pix.bytesperline =
632 (f->fmt.pix.width * (fmt->depth)) >> 3;
633 f->fmt.pix.sizeimage =
634 f->fmt.pix.height * f->fmt.pix.bytesperline;
635 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
636 return 0;
637 }
638
639 /*
640 * Note that tw68_s_fmt_vid_cap sets the information into the fh structure,
641 * and it will be used for all future new buffers. However, there could be
642 * some number of buffers on the "active" chain which will be filled before
643 * the change takes place.
644 */
tw68_s_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)645 static int tw68_s_fmt_vid_cap(struct file *file, void *priv,
646 struct v4l2_format *f)
647 {
648 struct tw68_dev *dev = video_drvdata(file);
649 int err;
650
651 err = tw68_try_fmt_vid_cap(file, priv, f);
652 if (0 != err)
653 return err;
654
655 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
656 dev->width = f->fmt.pix.width;
657 dev->height = f->fmt.pix.height;
658 dev->field = f->fmt.pix.field;
659 return 0;
660 }
661
tw68_enum_input(struct file * file,void * priv,struct v4l2_input * i)662 static int tw68_enum_input(struct file *file, void *priv,
663 struct v4l2_input *i)
664 {
665 struct tw68_dev *dev = video_drvdata(file);
666 unsigned int n;
667
668 n = i->index;
669 if (n >= TW68_INPUT_MAX)
670 return -EINVAL;
671 i->index = n;
672 i->type = V4L2_INPUT_TYPE_CAMERA;
673 snprintf(i->name, sizeof(i->name), "Composite %d", n);
674
675 /* If the query is for the current input, get live data */
676 if (n == dev->input) {
677 int v1 = tw_readb(TW68_STATUS1);
678 int v2 = tw_readb(TW68_MVSN);
679
680 if (0 != (v1 & (1 << 7)))
681 i->status |= V4L2_IN_ST_NO_SYNC;
682 if (0 != (v1 & (1 << 6)))
683 i->status |= V4L2_IN_ST_NO_H_LOCK;
684 if (0 != (v1 & (1 << 2)))
685 i->status |= V4L2_IN_ST_NO_SIGNAL;
686 if (0 != (v1 & 1 << 1))
687 i->status |= V4L2_IN_ST_NO_COLOR;
688 if (0 != (v2 & (1 << 2)))
689 i->status |= V4L2_IN_ST_MACROVISION;
690 }
691 i->std = video_devdata(file)->tvnorms;
692 return 0;
693 }
694
tw68_g_input(struct file * file,void * priv,unsigned int * i)695 static int tw68_g_input(struct file *file, void *priv, unsigned int *i)
696 {
697 struct tw68_dev *dev = video_drvdata(file);
698
699 *i = dev->input;
700 return 0;
701 }
702
tw68_s_input(struct file * file,void * priv,unsigned int i)703 static int tw68_s_input(struct file *file, void *priv, unsigned int i)
704 {
705 struct tw68_dev *dev = video_drvdata(file);
706
707 if (i >= TW68_INPUT_MAX)
708 return -EINVAL;
709 dev->input = i;
710 tw_andorb(TW68_INFORM, 0x03 << 2, dev->input << 2);
711 return 0;
712 }
713
tw68_querycap(struct file * file,void * priv,struct v4l2_capability * cap)714 static int tw68_querycap(struct file *file, void *priv,
715 struct v4l2_capability *cap)
716 {
717 strscpy(cap->driver, "tw68", sizeof(cap->driver));
718 strscpy(cap->card, "Techwell Capture Card",
719 sizeof(cap->card));
720 return 0;
721 }
722
tw68_s_std(struct file * file,void * priv,v4l2_std_id id)723 static int tw68_s_std(struct file *file, void *priv, v4l2_std_id id)
724 {
725 struct tw68_dev *dev = video_drvdata(file);
726 unsigned int i;
727
728 if (vb2_is_busy(&dev->vidq))
729 return -EBUSY;
730
731 /* Look for match on complete norm id (may have mult bits) */
732 for (i = 0; i < TVNORMS; i++) {
733 if (id == tvnorms[i].id)
734 break;
735 }
736
737 /* If no exact match, look for norm which contains this one */
738 if (i == TVNORMS) {
739 for (i = 0; i < TVNORMS; i++)
740 if (id & tvnorms[i].id)
741 break;
742 }
743 /* If still not matched, give up */
744 if (i == TVNORMS)
745 return -EINVAL;
746
747 set_tvnorm(dev, &tvnorms[i]); /* do the actual setting */
748 return 0;
749 }
750
tw68_g_std(struct file * file,void * priv,v4l2_std_id * id)751 static int tw68_g_std(struct file *file, void *priv, v4l2_std_id *id)
752 {
753 struct tw68_dev *dev = video_drvdata(file);
754
755 *id = dev->tvnorm->id;
756 return 0;
757 }
758
tw68_enum_fmt_vid_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)759 static int tw68_enum_fmt_vid_cap(struct file *file, void *priv,
760 struct v4l2_fmtdesc *f)
761 {
762 if (f->index >= FORMATS)
763 return -EINVAL;
764
765 f->pixelformat = formats[f->index].fourcc;
766
767 return 0;
768 }
769
770 /*
771 * Used strictly for internal development and debugging, this routine
772 * prints out the current register contents for the tw68xx device.
773 */
tw68_dump_regs(struct tw68_dev * dev)774 static void tw68_dump_regs(struct tw68_dev *dev)
775 {
776 unsigned char line[80];
777 int i, j, k;
778 unsigned char *cptr;
779
780 pr_info("Full dump of TW68 registers:\n");
781 /* First we do the PCI regs, 8 4-byte regs per line */
782 for (i = 0; i < 0x100; i += 32) {
783 cptr = line;
784 cptr += sprintf(cptr, "%03x ", i);
785 /* j steps through the next 4 words */
786 for (j = i; j < i + 16; j += 4)
787 cptr += sprintf(cptr, "%08x ", tw_readl(j));
788 *cptr++ = ' ';
789 for (; j < i + 32; j += 4)
790 cptr += sprintf(cptr, "%08x ", tw_readl(j));
791 *cptr++ = '\n';
792 *cptr = 0;
793 pr_info("%s", line);
794 }
795 /* Next the control regs, which are single-byte, address mod 4 */
796 while (i < 0x400) {
797 cptr = line;
798 cptr += sprintf(cptr, "%03x ", i);
799 /* Print out 4 groups of 4 bytes */
800 for (j = 0; j < 4; j++) {
801 for (k = 0; k < 4; k++) {
802 cptr += sprintf(cptr, "%02x ",
803 tw_readb(i));
804 i += 4;
805 }
806 *cptr++ = ' ';
807 }
808 *cptr++ = '\n';
809 *cptr = 0;
810 pr_info("%s", line);
811 }
812 }
813
vidioc_log_status(struct file * file,void * priv)814 static int vidioc_log_status(struct file *file, void *priv)
815 {
816 struct tw68_dev *dev = video_drvdata(file);
817
818 tw68_dump_regs(dev);
819 return v4l2_ctrl_log_status(file, priv);
820 }
821
822 #ifdef CONFIG_VIDEO_ADV_DEBUG
vidioc_g_register(struct file * file,void * priv,struct v4l2_dbg_register * reg)823 static int vidioc_g_register(struct file *file, void *priv,
824 struct v4l2_dbg_register *reg)
825 {
826 struct tw68_dev *dev = video_drvdata(file);
827
828 if (reg->size == 1)
829 reg->val = tw_readb(reg->reg);
830 else
831 reg->val = tw_readl(reg->reg);
832 return 0;
833 }
834
vidioc_s_register(struct file * file,void * priv,const struct v4l2_dbg_register * reg)835 static int vidioc_s_register(struct file *file, void *priv,
836 const struct v4l2_dbg_register *reg)
837 {
838 struct tw68_dev *dev = video_drvdata(file);
839
840 if (reg->size == 1)
841 tw_writeb(reg->reg, reg->val);
842 else
843 tw_writel(reg->reg & 0xffff, reg->val);
844 return 0;
845 }
846 #endif
847
848 static const struct v4l2_ctrl_ops tw68_ctrl_ops = {
849 .s_ctrl = tw68_s_ctrl,
850 };
851
852 static const struct v4l2_file_operations video_fops = {
853 .owner = THIS_MODULE,
854 .open = v4l2_fh_open,
855 .release = vb2_fop_release,
856 .read = vb2_fop_read,
857 .poll = vb2_fop_poll,
858 .mmap = vb2_fop_mmap,
859 .unlocked_ioctl = video_ioctl2,
860 };
861
862 static const struct v4l2_ioctl_ops video_ioctl_ops = {
863 .vidioc_querycap = tw68_querycap,
864 .vidioc_enum_fmt_vid_cap = tw68_enum_fmt_vid_cap,
865 .vidioc_reqbufs = vb2_ioctl_reqbufs,
866 .vidioc_create_bufs = vb2_ioctl_create_bufs,
867 .vidioc_querybuf = vb2_ioctl_querybuf,
868 .vidioc_qbuf = vb2_ioctl_qbuf,
869 .vidioc_dqbuf = vb2_ioctl_dqbuf,
870 .vidioc_s_std = tw68_s_std,
871 .vidioc_g_std = tw68_g_std,
872 .vidioc_enum_input = tw68_enum_input,
873 .vidioc_g_input = tw68_g_input,
874 .vidioc_s_input = tw68_s_input,
875 .vidioc_streamon = vb2_ioctl_streamon,
876 .vidioc_streamoff = vb2_ioctl_streamoff,
877 .vidioc_g_fmt_vid_cap = tw68_g_fmt_vid_cap,
878 .vidioc_try_fmt_vid_cap = tw68_try_fmt_vid_cap,
879 .vidioc_s_fmt_vid_cap = tw68_s_fmt_vid_cap,
880 .vidioc_log_status = vidioc_log_status,
881 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
882 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
883 #ifdef CONFIG_VIDEO_ADV_DEBUG
884 .vidioc_g_register = vidioc_g_register,
885 .vidioc_s_register = vidioc_s_register,
886 #endif
887 };
888
889 static const struct video_device tw68_video_template = {
890 .name = "tw68_video",
891 .fops = &video_fops,
892 .ioctl_ops = &video_ioctl_ops,
893 .release = video_device_release_empty,
894 .tvnorms = TW68_NORMS,
895 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
896 V4L2_CAP_STREAMING,
897 };
898
899 /* ------------------------------------------------------------------ */
900 /* exported stuff */
tw68_set_tvnorm_hw(struct tw68_dev * dev)901 void tw68_set_tvnorm_hw(struct tw68_dev *dev)
902 {
903 tw_andorb(TW68_SDT, 0x07, dev->tvnorm->format);
904 }
905
tw68_video_init1(struct tw68_dev * dev)906 int tw68_video_init1(struct tw68_dev *dev)
907 {
908 struct v4l2_ctrl_handler *hdl = &dev->hdl;
909
910 v4l2_ctrl_handler_init(hdl, 6);
911 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
912 V4L2_CID_BRIGHTNESS, -128, 127, 1, 20);
913 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
914 V4L2_CID_CONTRAST, 0, 255, 1, 100);
915 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
916 V4L2_CID_SATURATION, 0, 255, 1, 128);
917 /* NTSC only */
918 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
919 V4L2_CID_HUE, -128, 127, 1, 0);
920 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
921 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
922 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
923 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
924 if (hdl->error) {
925 v4l2_ctrl_handler_free(hdl);
926 return hdl->error;
927 }
928 dev->v4l2_dev.ctrl_handler = hdl;
929 v4l2_ctrl_handler_setup(hdl);
930 return 0;
931 }
932
tw68_video_init2(struct tw68_dev * dev,int video_nr)933 int tw68_video_init2(struct tw68_dev *dev, int video_nr)
934 {
935 int ret;
936
937 set_tvnorm(dev, &tvnorms[0]);
938
939 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
940 dev->width = 720;
941 dev->height = 576;
942 dev->field = V4L2_FIELD_INTERLACED;
943
944 INIT_LIST_HEAD(&dev->active);
945 dev->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
946 dev->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
947 dev->vidq.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ | VB2_DMABUF;
948 dev->vidq.ops = &tw68_video_qops;
949 dev->vidq.mem_ops = &vb2_dma_sg_memops;
950 dev->vidq.drv_priv = dev;
951 dev->vidq.gfp_flags = __GFP_DMA32 | __GFP_KSWAPD_RECLAIM;
952 dev->vidq.buf_struct_size = sizeof(struct tw68_buf);
953 dev->vidq.lock = &dev->lock;
954 dev->vidq.min_buffers_needed = 2;
955 dev->vidq.dev = &dev->pci->dev;
956 ret = vb2_queue_init(&dev->vidq);
957 if (ret)
958 return ret;
959 dev->vdev = tw68_video_template;
960 dev->vdev.v4l2_dev = &dev->v4l2_dev;
961 dev->vdev.lock = &dev->lock;
962 dev->vdev.queue = &dev->vidq;
963 video_set_drvdata(&dev->vdev, dev);
964 return video_register_device(&dev->vdev, VFL_TYPE_VIDEO, video_nr);
965 }
966
967 /*
968 * tw68_irq_video_done
969 */
tw68_irq_video_done(struct tw68_dev * dev,unsigned long status)970 void tw68_irq_video_done(struct tw68_dev *dev, unsigned long status)
971 {
972 __u32 reg;
973
974 /* reset interrupts handled by this routine */
975 tw_writel(TW68_INTSTAT, status);
976 /*
977 * Check most likely first
978 *
979 * DMAPI shows we have reached the end of the risc code
980 * for the current buffer.
981 */
982 if (status & TW68_DMAPI) {
983 struct tw68_buf *buf;
984
985 spin_lock(&dev->slock);
986 buf = list_entry(dev->active.next, struct tw68_buf, list);
987 list_del(&buf->list);
988 spin_unlock(&dev->slock);
989 buf->vb.vb2_buf.timestamp = ktime_get_ns();
990 buf->vb.field = dev->field;
991 buf->vb.sequence = dev->seqnr++;
992 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
993 status &= ~(TW68_DMAPI);
994 if (0 == status)
995 return;
996 }
997 if (status & (TW68_VLOCK | TW68_HLOCK))
998 dev_dbg(&dev->pci->dev, "Lost sync\n");
999 if (status & TW68_PABORT)
1000 dev_err(&dev->pci->dev, "PABORT interrupt\n");
1001 if (status & TW68_DMAPERR)
1002 dev_err(&dev->pci->dev, "DMAPERR interrupt\n");
1003 /*
1004 * On TW6800, FDMIS is apparently generated if video input is switched
1005 * during operation. Therefore, it is not enabled for that chip.
1006 */
1007 if (status & TW68_FDMIS)
1008 dev_dbg(&dev->pci->dev, "FDMIS interrupt\n");
1009 if (status & TW68_FFOF) {
1010 /* probably a logic error */
1011 reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN;
1012 tw_clearl(TW68_DMAC, TW68_FIFO_EN);
1013 dev_dbg(&dev->pci->dev, "FFOF interrupt\n");
1014 tw_setl(TW68_DMAC, reg);
1015 }
1016 if (status & TW68_FFERR)
1017 dev_dbg(&dev->pci->dev, "FFERR interrupt\n");
1018 }
1019