1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Atmel MACB Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7 #ifndef _MACB_H
8 #define _MACB_H
9
10 #include <linux/clk.h>
11 #include <linux/phylink.h>
12 #include <linux/ptp_clock_kernel.h>
13 #include <linux/net_tstamp.h>
14 #include <linux/interrupt.h>
15 #include <linux/phy/phy.h>
16
17 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
18 #define MACB_EXT_DESC
19 #endif
20
21 #define MACB_GREGS_NBR 16
22 #define MACB_GREGS_VERSION 2
23 #define MACB_MAX_QUEUES 8
24
25 /* MACB register offsets */
26 #define MACB_NCR 0x0000 /* Network Control */
27 #define MACB_NCFGR 0x0004 /* Network Config */
28 #define MACB_NSR 0x0008 /* Network Status */
29 #define MACB_TAR 0x000c /* AT91RM9200 only */
30 #define MACB_TCR 0x0010 /* AT91RM9200 only */
31 #define MACB_TSR 0x0014 /* Transmit Status */
32 #define MACB_RBQP 0x0018 /* RX Q Base Address */
33 #define MACB_TBQP 0x001c /* TX Q Base Address */
34 #define MACB_RSR 0x0020 /* Receive Status */
35 #define MACB_ISR 0x0024 /* Interrupt Status */
36 #define MACB_IER 0x0028 /* Interrupt Enable */
37 #define MACB_IDR 0x002c /* Interrupt Disable */
38 #define MACB_IMR 0x0030 /* Interrupt Mask */
39 #define MACB_MAN 0x0034 /* PHY Maintenance */
40 #define MACB_PTR 0x0038
41 #define MACB_PFR 0x003c
42 #define MACB_FTO 0x0040
43 #define MACB_SCF 0x0044
44 #define MACB_MCF 0x0048
45 #define MACB_FRO 0x004c
46 #define MACB_FCSE 0x0050
47 #define MACB_ALE 0x0054
48 #define MACB_DTF 0x0058
49 #define MACB_LCOL 0x005c
50 #define MACB_EXCOL 0x0060
51 #define MACB_TUND 0x0064
52 #define MACB_CSE 0x0068
53 #define MACB_RRE 0x006c
54 #define MACB_ROVR 0x0070
55 #define MACB_RSE 0x0074
56 #define MACB_ELE 0x0078
57 #define MACB_RJA 0x007c
58 #define MACB_USF 0x0080
59 #define MACB_STE 0x0084
60 #define MACB_RLE 0x0088
61 #define MACB_TPF 0x008c
62 #define MACB_HRB 0x0090
63 #define MACB_HRT 0x0094
64 #define MACB_SA1B 0x0098
65 #define MACB_SA1T 0x009c
66 #define MACB_SA2B 0x00a0
67 #define MACB_SA2T 0x00a4
68 #define MACB_SA3B 0x00a8
69 #define MACB_SA3T 0x00ac
70 #define MACB_SA4B 0x00b0
71 #define MACB_SA4T 0x00b4
72 #define MACB_TID 0x00b8
73 #define MACB_TPQ 0x00bc
74 #define MACB_USRIO 0x00c0
75 #define MACB_WOL 0x00c4
76 #define MACB_MID 0x00fc
77 #define MACB_TBQPH 0x04C8
78 #define MACB_RBQPH 0x04D4
79
80 /* GEM register offsets. */
81 #define GEM_NCR 0x0000 /* Network Control */
82 #define GEM_NCFGR 0x0004 /* Network Config */
83 #define GEM_USRIO 0x000c /* User IO */
84 #define GEM_DMACFG 0x0010 /* DMA Configuration */
85 #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
86 #define GEM_JML 0x0048 /* Jumbo Max Length */
87 #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
88 #define GEM_HRB 0x0080 /* Hash Bottom */
89 #define GEM_HRT 0x0084 /* Hash Top */
90 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
91 #define GEM_SA1T 0x008C /* Specific1 Top */
92 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
93 #define GEM_SA2T 0x0094 /* Specific2 Top */
94 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
95 #define GEM_SA3T 0x009C /* Specific3 Top */
96 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
97 #define GEM_SA4T 0x00A4 /* Specific4 Top */
98 #define GEM_WOL 0x00b8 /* Wake on LAN */
99 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
100 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
101 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
102 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
103 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
104 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
105 #define GEM_OTX 0x0100 /* Octets transmitted */
106 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
107 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
108 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
109 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
110 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
111 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
112 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
113 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
114 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
115 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
116 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
117 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
118 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
119 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
120 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
121 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
122 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
123 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
124 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
125 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
126 #define GEM_ORX 0x0150 /* Octets received */
127 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
128 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
129 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
130 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
131 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
132 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
133 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
134 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
135 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
136 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
137 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
138 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
139 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
140 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
141 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
142 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
143 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
144 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
145 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
146 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
147 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
148 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
149 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
150 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
151 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
152 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
153 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
154 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
155 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
156 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
157 #define GEM_TI 0x01dc /* 1588 Timer Increment */
158 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
159 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
160 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
161 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
162 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
163 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
164 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
165 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
166 #define GEM_PCSCNTRL 0x0200 /* PCS Control */
167 #define GEM_PCSSTS 0x0204 /* PCS Status */
168 #define GEM_PCSPHYTOPID 0x0208 /* PCS PHY Top ID */
169 #define GEM_PCSPHYBOTID 0x020c /* PCS PHY Bottom ID */
170 #define GEM_PCSANADV 0x0210 /* PCS AN Advertisement */
171 #define GEM_PCSANLPBASE 0x0214 /* PCS AN Link Partner Base */
172 #define GEM_PCSANEXP 0x0218 /* PCS AN Expansion */
173 #define GEM_PCSANNPTX 0x021c /* PCS AN Next Page TX */
174 #define GEM_PCSANNPLP 0x0220 /* PCS AN Next Page LP */
175 #define GEM_PCSANEXTSTS 0x023c /* PCS AN Extended Status */
176 #define GEM_DCFG1 0x0280 /* Design Config 1 */
177 #define GEM_DCFG2 0x0284 /* Design Config 2 */
178 #define GEM_DCFG3 0x0288 /* Design Config 3 */
179 #define GEM_DCFG4 0x028c /* Design Config 4 */
180 #define GEM_DCFG5 0x0290 /* Design Config 5 */
181 #define GEM_DCFG6 0x0294 /* Design Config 6 */
182 #define GEM_DCFG7 0x0298 /* Design Config 7 */
183 #define GEM_DCFG8 0x029C /* Design Config 8 */
184 #define GEM_DCFG10 0x02A4 /* Design Config 10 */
185 #define GEM_DCFG12 0x02AC /* Design Config 12 */
186 #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */
187 #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */
188
189 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
190 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
191
192 /* Screener Type 2 match registers */
193 #define GEM_SCRT2 0x540
194
195 /* EtherType registers */
196 #define GEM_ETHT 0x06E0
197
198 /* Type 2 compare registers */
199 #define GEM_T2CMPW0 0x0700
200 #define GEM_T2CMPW1 0x0704
201 #define T2CMP_OFST(t2idx) (t2idx * 2)
202
203 /* type 2 compare registers
204 * each location requires 3 compare regs
205 */
206 #define GEM_IP4SRC_CMP(idx) (idx * 3)
207 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
208 #define GEM_PORT_CMP(idx) (idx * 3 + 2)
209
210 /* Which screening type 2 EtherType register will be used (0 - 7) */
211 #define SCRT2_ETHT 0
212
213 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
214 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
215 #define GEM_TBQPH(hw_q) (0x04C8)
216 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
217 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
218 #define GEM_RBQPH(hw_q) (0x04D4)
219 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
220 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
221 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
222
223 /* Bitfields in NCR */
224 #define MACB_LB_OFFSET 0 /* reserved */
225 #define MACB_LB_SIZE 1
226 #define MACB_LLB_OFFSET 1 /* Loop back local */
227 #define MACB_LLB_SIZE 1
228 #define MACB_RE_OFFSET 2 /* Receive enable */
229 #define MACB_RE_SIZE 1
230 #define MACB_TE_OFFSET 3 /* Transmit enable */
231 #define MACB_TE_SIZE 1
232 #define MACB_MPE_OFFSET 4 /* Management port enable */
233 #define MACB_MPE_SIZE 1
234 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
235 #define MACB_CLRSTAT_SIZE 1
236 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
237 #define MACB_INCSTAT_SIZE 1
238 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
239 #define MACB_WESTAT_SIZE 1
240 #define MACB_BP_OFFSET 8 /* Back pressure */
241 #define MACB_BP_SIZE 1
242 #define MACB_TSTART_OFFSET 9 /* Start transmission */
243 #define MACB_TSTART_SIZE 1
244 #define MACB_THALT_OFFSET 10 /* Transmit halt */
245 #define MACB_THALT_SIZE 1
246 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
247 #define MACB_NCR_TPF_SIZE 1
248 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
249 #define MACB_TZQ_SIZE 1
250 #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */
251 #define MACB_PTPUNI_OFFSET 20 /* PTP Unicast packet enable */
252 #define MACB_PTPUNI_SIZE 1
253 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
254 #define MACB_OSSMODE_SIZE 1
255 #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */
256 #define MACB_MIIONRGMII_SIZE 1
257
258 /* Bitfields in NCFGR */
259 #define MACB_SPD_OFFSET 0 /* Speed */
260 #define MACB_SPD_SIZE 1
261 #define MACB_FD_OFFSET 1 /* Full duplex */
262 #define MACB_FD_SIZE 1
263 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
264 #define MACB_BIT_RATE_SIZE 1
265 #define MACB_JFRAME_OFFSET 3 /* reserved */
266 #define MACB_JFRAME_SIZE 1
267 #define MACB_CAF_OFFSET 4 /* Copy all frames */
268 #define MACB_CAF_SIZE 1
269 #define MACB_NBC_OFFSET 5 /* No broadcast */
270 #define MACB_NBC_SIZE 1
271 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
272 #define MACB_NCFGR_MTI_SIZE 1
273 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
274 #define MACB_UNI_SIZE 1
275 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
276 #define MACB_BIG_SIZE 1
277 #define MACB_EAE_OFFSET 9 /* External address match enable */
278 #define MACB_EAE_SIZE 1
279 #define MACB_CLK_OFFSET 10
280 #define MACB_CLK_SIZE 2
281 #define MACB_RTY_OFFSET 12 /* Retry test */
282 #define MACB_RTY_SIZE 1
283 #define MACB_PAE_OFFSET 13 /* Pause enable */
284 #define MACB_PAE_SIZE 1
285 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
286 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
287 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
288 #define MACB_RBOF_SIZE 2
289 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
290 #define MACB_RLCE_SIZE 1
291 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
292 #define MACB_DRFCS_SIZE 1
293 #define MACB_EFRHD_OFFSET 18
294 #define MACB_EFRHD_SIZE 1
295 #define MACB_IRXFCS_OFFSET 19
296 #define MACB_IRXFCS_SIZE 1
297
298 /* GEM specific NCR bitfields. */
299 #define GEM_ENABLE_HS_MAC_OFFSET 31
300 #define GEM_ENABLE_HS_MAC_SIZE 1
301
302 /* GEM specific NCFGR bitfields. */
303 #define GEM_FD_OFFSET 1 /* Full duplex */
304 #define GEM_FD_SIZE 1
305 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
306 #define GEM_GBE_SIZE 1
307 #define GEM_PCSSEL_OFFSET 11
308 #define GEM_PCSSEL_SIZE 1
309 #define GEM_PAE_OFFSET 13 /* Pause enable */
310 #define GEM_PAE_SIZE 1
311 #define GEM_CLK_OFFSET 18 /* MDC clock division */
312 #define GEM_CLK_SIZE 3
313 #define GEM_DBW_OFFSET 21 /* Data bus width */
314 #define GEM_DBW_SIZE 2
315 #define GEM_RXCOEN_OFFSET 24
316 #define GEM_RXCOEN_SIZE 1
317 #define GEM_SGMIIEN_OFFSET 27
318 #define GEM_SGMIIEN_SIZE 1
319
320
321 /* Constants for data bus width. */
322 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
323 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
324 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
325
326 /* Bitfields in DMACFG. */
327 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
328 #define GEM_FBLDO_SIZE 5
329 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
330 #define GEM_ENDIA_DESC_SIZE 1
331 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
332 #define GEM_ENDIA_PKT_SIZE 1
333 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
334 #define GEM_RXBMS_SIZE 2
335 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
336 #define GEM_TXPBMS_SIZE 1
337 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
338 #define GEM_TXCOEN_SIZE 1
339 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
340 #define GEM_RXBS_SIZE 8
341 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
342 #define GEM_DDRP_SIZE 1
343 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
344 #define GEM_RXEXT_SIZE 1
345 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
346 #define GEM_TXEXT_SIZE 1
347 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
348 #define GEM_ADDR64_SIZE 1
349
350
351 /* Bitfields in PBUFRXCUT */
352 #define GEM_ENCUTTHRU_OFFSET 31 /* Enable RX partial store and forward */
353 #define GEM_ENCUTTHRU_SIZE 1
354
355 /* Bitfields in NSR */
356 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
357 #define MACB_NSR_LINK_SIZE 1
358 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
359 #define MACB_MDIO_SIZE 1
360 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
361 #define MACB_IDLE_SIZE 1
362
363 /* Bitfields in TSR */
364 #define MACB_UBR_OFFSET 0 /* Used bit read */
365 #define MACB_UBR_SIZE 1
366 #define MACB_COL_OFFSET 1 /* Collision occurred */
367 #define MACB_COL_SIZE 1
368 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
369 #define MACB_TSR_RLE_SIZE 1
370 #define MACB_TGO_OFFSET 3 /* Transmit go */
371 #define MACB_TGO_SIZE 1
372 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
373 #define MACB_BEX_SIZE 1
374 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
375 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
376 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
377 #define MACB_COMP_SIZE 1
378 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
379 #define MACB_UND_SIZE 1
380
381 /* Bitfields in RSR */
382 #define MACB_BNA_OFFSET 0 /* Buffer not available */
383 #define MACB_BNA_SIZE 1
384 #define MACB_REC_OFFSET 1 /* Frame received */
385 #define MACB_REC_SIZE 1
386 #define MACB_OVR_OFFSET 2 /* Receive overrun */
387 #define MACB_OVR_SIZE 1
388
389 /* Bitfields in ISR/IER/IDR/IMR */
390 #define MACB_MFD_OFFSET 0 /* Management frame sent */
391 #define MACB_MFD_SIZE 1
392 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
393 #define MACB_RCOMP_SIZE 1
394 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
395 #define MACB_RXUBR_SIZE 1
396 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
397 #define MACB_TXUBR_SIZE 1
398 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
399 #define MACB_ISR_TUND_SIZE 1
400 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
401 #define MACB_ISR_RLE_SIZE 1
402 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
403 #define MACB_TXERR_SIZE 1
404 #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */
405 #define MACB_RM9200_TBRE_SIZE 1
406 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
407 #define MACB_TCOMP_SIZE 1
408 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
409 #define MACB_ISR_LINK_SIZE 1
410 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
411 #define MACB_ISR_ROVR_SIZE 1
412 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
413 #define MACB_HRESP_SIZE 1
414 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
415 #define MACB_PFR_SIZE 1
416 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
417 #define MACB_PTZ_SIZE 1
418 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
419 #define MACB_WOL_SIZE 1
420 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
421 #define MACB_DRQFR_SIZE 1
422 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
423 #define MACB_SFR_SIZE 1
424 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
425 #define MACB_DRQFT_SIZE 1
426 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
427 #define MACB_SFT_SIZE 1
428 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
429 #define MACB_PDRQFR_SIZE 1
430 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
431 #define MACB_PDRSFR_SIZE 1
432 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
433 #define MACB_PDRQFT_SIZE 1
434 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
435 #define MACB_PDRSFT_SIZE 1
436 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
437 #define MACB_SRI_SIZE 1
438 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
439 #define GEM_WOL_SIZE 1
440
441 /* Timer increment fields */
442 #define MACB_TI_CNS_OFFSET 0
443 #define MACB_TI_CNS_SIZE 8
444 #define MACB_TI_ACNS_OFFSET 8
445 #define MACB_TI_ACNS_SIZE 8
446 #define MACB_TI_NIT_OFFSET 16
447 #define MACB_TI_NIT_SIZE 8
448
449 /* Bitfields in MAN */
450 #define MACB_DATA_OFFSET 0 /* data */
451 #define MACB_DATA_SIZE 16
452 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
453 #define MACB_CODE_SIZE 2
454 #define MACB_REGA_OFFSET 18 /* Register address */
455 #define MACB_REGA_SIZE 5
456 #define MACB_PHYA_OFFSET 23 /* PHY address */
457 #define MACB_PHYA_SIZE 5
458 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
459 #define MACB_RW_SIZE 2
460 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
461 #define MACB_SOF_SIZE 2
462
463 /* Bitfields in USRIO (AVR32) */
464 #define MACB_MII_OFFSET 0
465 #define MACB_MII_SIZE 1
466 #define MACB_EAM_OFFSET 1
467 #define MACB_EAM_SIZE 1
468 #define MACB_TX_PAUSE_OFFSET 2
469 #define MACB_TX_PAUSE_SIZE 1
470 #define MACB_TX_PAUSE_ZERO_OFFSET 3
471 #define MACB_TX_PAUSE_ZERO_SIZE 1
472
473 /* Bitfields in USRIO (AT91) */
474 #define MACB_RMII_OFFSET 0
475 #define MACB_RMII_SIZE 1
476 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
477 #define GEM_RGMII_SIZE 1
478 #define MACB_CLKEN_OFFSET 1
479 #define MACB_CLKEN_SIZE 1
480
481 /* Bitfields in WOL */
482 #define MACB_IP_OFFSET 0
483 #define MACB_IP_SIZE 16
484 #define MACB_MAG_OFFSET 16
485 #define MACB_MAG_SIZE 1
486 #define MACB_ARP_OFFSET 17
487 #define MACB_ARP_SIZE 1
488 #define MACB_SA1_OFFSET 18
489 #define MACB_SA1_SIZE 1
490 #define MACB_WOL_MTI_OFFSET 19
491 #define MACB_WOL_MTI_SIZE 1
492
493 /* Bitfields in MID */
494 #define MACB_IDNUM_OFFSET 16
495 #define MACB_IDNUM_SIZE 12
496 #define MACB_REV_OFFSET 0
497 #define MACB_REV_SIZE 16
498
499 /* Bitfield in HS_MAC_CONFIG */
500 #define GEM_HS_MAC_SPEED_OFFSET 0
501 #define GEM_HS_MAC_SPEED_SIZE 3
502
503 /* Bitfields in PCSCNTRL */
504 #define GEM_PCSAUTONEG_OFFSET 12
505 #define GEM_PCSAUTONEG_SIZE 1
506
507 /* Bitfields in DCFG1. */
508 #define GEM_IRQCOR_OFFSET 23
509 #define GEM_IRQCOR_SIZE 1
510 #define GEM_DBWDEF_OFFSET 25
511 #define GEM_DBWDEF_SIZE 3
512 #define GEM_NO_PCS_OFFSET 0
513 #define GEM_NO_PCS_SIZE 1
514
515 /* Bitfields in DCFG2. */
516 #define GEM_RX_PKT_BUFF_OFFSET 20
517 #define GEM_RX_PKT_BUFF_SIZE 1
518 #define GEM_TX_PKT_BUFF_OFFSET 21
519 #define GEM_TX_PKT_BUFF_SIZE 1
520
521 #define GEM_RX_PBUF_ADDR_OFFSET 22
522 #define GEM_RX_PBUF_ADDR_SIZE 4
523
524 /* Bitfields in DCFG5. */
525 #define GEM_TSU_OFFSET 8
526 #define GEM_TSU_SIZE 1
527
528 /* Bitfields in DCFG6. */
529 #define GEM_PBUF_LSO_OFFSET 27
530 #define GEM_PBUF_LSO_SIZE 1
531 #define GEM_PBUF_CUTTHRU_OFFSET 25
532 #define GEM_PBUF_CUTTHRU_SIZE 1
533 #define GEM_DAW64_OFFSET 23
534 #define GEM_DAW64_SIZE 1
535
536 /* Bitfields in DCFG8. */
537 #define GEM_T1SCR_OFFSET 24
538 #define GEM_T1SCR_SIZE 8
539 #define GEM_T2SCR_OFFSET 16
540 #define GEM_T2SCR_SIZE 8
541 #define GEM_SCR2ETH_OFFSET 8
542 #define GEM_SCR2ETH_SIZE 8
543 #define GEM_SCR2CMP_OFFSET 0
544 #define GEM_SCR2CMP_SIZE 8
545
546 /* Bitfields in DCFG10 */
547 #define GEM_TXBD_RDBUFF_OFFSET 12
548 #define GEM_TXBD_RDBUFF_SIZE 4
549 #define GEM_RXBD_RDBUFF_OFFSET 8
550 #define GEM_RXBD_RDBUFF_SIZE 4
551
552 /* Bitfields in DCFG12. */
553 #define GEM_HIGH_SPEED_OFFSET 26
554 #define GEM_HIGH_SPEED_SIZE 1
555
556 /* Bitfields in USX_CONTROL. */
557 #define GEM_USX_CTRL_SPEED_OFFSET 14
558 #define GEM_USX_CTRL_SPEED_SIZE 3
559 #define GEM_SERDES_RATE_OFFSET 12
560 #define GEM_SERDES_RATE_SIZE 2
561 #define GEM_RX_SCR_BYPASS_OFFSET 9
562 #define GEM_RX_SCR_BYPASS_SIZE 1
563 #define GEM_TX_SCR_BYPASS_OFFSET 8
564 #define GEM_TX_SCR_BYPASS_SIZE 1
565 #define GEM_TX_EN_OFFSET 1
566 #define GEM_TX_EN_SIZE 1
567 #define GEM_SIGNAL_OK_OFFSET 0
568 #define GEM_SIGNAL_OK_SIZE 1
569
570 /* Bitfields in USX_STATUS. */
571 #define GEM_USX_BLOCK_LOCK_OFFSET 0
572 #define GEM_USX_BLOCK_LOCK_SIZE 1
573
574 /* Bitfields in TISUBN */
575 #define GEM_SUBNSINCR_OFFSET 0
576 #define GEM_SUBNSINCRL_OFFSET 24
577 #define GEM_SUBNSINCRL_SIZE 8
578 #define GEM_SUBNSINCRH_OFFSET 0
579 #define GEM_SUBNSINCRH_SIZE 16
580 #define GEM_SUBNSINCR_SIZE 24
581
582 /* Bitfields in TI */
583 #define GEM_NSINCR_OFFSET 0
584 #define GEM_NSINCR_SIZE 8
585
586 /* Bitfields in TSH */
587 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
588 #define GEM_TSH_SIZE 16
589
590 /* Bitfields in TSL */
591 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
592 #define GEM_TSL_SIZE 32
593
594 /* Bitfields in TN */
595 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
596 #define GEM_TN_SIZE 30
597
598 /* Bitfields in TXBDCTRL */
599 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
600 #define GEM_TXTSMODE_SIZE 2
601
602 /* Bitfields in RXBDCTRL */
603 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
604 #define GEM_RXTSMODE_SIZE 2
605
606 /* Bitfields in SCRT2 */
607 #define GEM_QUEUE_OFFSET 0 /* Queue Number */
608 #define GEM_QUEUE_SIZE 4
609 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
610 #define GEM_VLANPR_SIZE 3
611 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
612 #define GEM_VLANEN_SIZE 1
613 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
614 #define GEM_ETHT2IDX_SIZE 3
615 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
616 #define GEM_ETHTEN_SIZE 1
617 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
618 #define GEM_CMPA_SIZE 5
619 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
620 #define GEM_CMPAEN_SIZE 1
621 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
622 #define GEM_CMPB_SIZE 5
623 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
624 #define GEM_CMPBEN_SIZE 1
625 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
626 #define GEM_CMPC_SIZE 5
627 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
628 #define GEM_CMPCEN_SIZE 1
629
630 /* Bitfields in ETHT */
631 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
632 #define GEM_ETHTCMP_SIZE 16
633
634 /* Bitfields in T2CMPW0 */
635 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
636 #define GEM_T2CMP_SIZE 16
637 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
638 #define GEM_T2MASK_SIZE 16
639
640 /* Bitfields in T2CMPW1 */
641 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
642 #define GEM_T2DISMSK_SIZE 1
643 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
644 #define GEM_T2CMPOFST_SIZE 2
645 #define GEM_T2OFST_OFFSET 0 /* offset value */
646 #define GEM_T2OFST_SIZE 7
647
648 /* Offset for screener type 2 compare values (T2CMPOFST).
649 * Note the offset is applied after the specified point,
650 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
651 * of 12 bytes from this would be the source IP address in an IP header
652 */
653 #define GEM_T2COMPOFST_SOF 0
654 #define GEM_T2COMPOFST_ETYPE 1
655 #define GEM_T2COMPOFST_IPHDR 2
656 #define GEM_T2COMPOFST_TCPUDP 3
657
658 /* offset from EtherType to IP address */
659 #define ETYPE_SRCIP_OFFSET 12
660 #define ETYPE_DSTIP_OFFSET 16
661
662 /* offset from IP header to port */
663 #define IPHDR_SRCPORT_OFFSET 0
664 #define IPHDR_DSTPORT_OFFSET 2
665
666 /* Transmit DMA buffer descriptor Word 1 */
667 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
668 #define GEM_DMA_TXVALID_SIZE 1
669
670 /* Receive DMA buffer descriptor Word 0 */
671 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
672 #define GEM_DMA_RXVALID_SIZE 1
673
674 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
675 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
676 #define GEM_DMA_SECL_SIZE 2
677 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
678 #define GEM_DMA_NSEC_SIZE 30
679
680 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
681
682 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
683 * Old hardware supports only 6 bit precision but it is enough for PTP.
684 * Less accuracy is used always instead of checking hardware version.
685 */
686 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
687 #define GEM_DMA_SECH_SIZE 4
688 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
689 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
690 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
691
692 /* Bitfields in ADJ */
693 #define GEM_ADDSUB_OFFSET 31
694 #define GEM_ADDSUB_SIZE 1
695 /* Constants for CLK */
696 #define MACB_CLK_DIV8 0
697 #define MACB_CLK_DIV16 1
698 #define MACB_CLK_DIV32 2
699 #define MACB_CLK_DIV64 3
700
701 /* GEM specific constants for CLK. */
702 #define GEM_CLK_DIV8 0
703 #define GEM_CLK_DIV16 1
704 #define GEM_CLK_DIV32 2
705 #define GEM_CLK_DIV48 3
706 #define GEM_CLK_DIV64 4
707 #define GEM_CLK_DIV96 5
708 #define GEM_CLK_DIV128 6
709 #define GEM_CLK_DIV224 7
710
711 /* Constants for MAN register */
712 #define MACB_MAN_C22_SOF 1
713 #define MACB_MAN_C22_WRITE 1
714 #define MACB_MAN_C22_READ 2
715 #define MACB_MAN_C22_CODE 2
716
717 #define MACB_MAN_C45_SOF 0
718 #define MACB_MAN_C45_ADDR 0
719 #define MACB_MAN_C45_WRITE 1
720 #define MACB_MAN_C45_POST_READ_INCR 2
721 #define MACB_MAN_C45_READ 3
722 #define MACB_MAN_C45_CODE 2
723
724 /* Capability mask bits */
725 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
726 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
727 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
728 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
729 #define MACB_CAPS_USRIO_DISABLED 0x00000010
730 #define MACB_CAPS_JUMBO 0x00000020
731 #define MACB_CAPS_GEM_HAS_PTP 0x00000040
732 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
733 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
734 #define MACB_CAPS_MIIONRGMII 0x00000200
735 #define MACB_CAPS_NEED_TSUCLK 0x00000400
736 #define MACB_CAPS_PCS 0x01000000
737 #define MACB_CAPS_HIGH_SPEED 0x02000000
738 #define MACB_CAPS_CLK_HW_CHG 0x04000000
739 #define MACB_CAPS_MACB_IS_EMAC 0x08000000
740 #define MACB_CAPS_FIFO_MODE 0x10000000
741 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
742 #define MACB_CAPS_SG_DISABLED 0x40000000
743 #define MACB_CAPS_MACB_IS_GEM 0x80000000
744
745 /* LSO settings */
746 #define MACB_LSO_UFO_ENABLE 0x01
747 #define MACB_LSO_TSO_ENABLE 0x02
748
749 /* Bit manipulation macros */
750 #define MACB_BIT(name) \
751 (1 << MACB_##name##_OFFSET)
752 #define MACB_BF(name,value) \
753 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
754 << MACB_##name##_OFFSET)
755 #define MACB_BFEXT(name,value)\
756 (((value) >> MACB_##name##_OFFSET) \
757 & ((1 << MACB_##name##_SIZE) - 1))
758 #define MACB_BFINS(name,value,old) \
759 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
760 << MACB_##name##_OFFSET)) \
761 | MACB_BF(name,value))
762
763 #define GEM_BIT(name) \
764 (1 << GEM_##name##_OFFSET)
765 #define GEM_BF(name, value) \
766 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
767 << GEM_##name##_OFFSET)
768 #define GEM_BFEXT(name, value)\
769 (((value) >> GEM_##name##_OFFSET) \
770 & ((1 << GEM_##name##_SIZE) - 1))
771 #define GEM_BFINS(name, value, old) \
772 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
773 << GEM_##name##_OFFSET)) \
774 | GEM_BF(name, value))
775
776 /* Register access macros */
777 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
778 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
779 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
780 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
781 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
782 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
783 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
784 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
785
786 /* Conditional GEM/MACB macros. These perform the operation to the correct
787 * register dependent on whether the device is a GEM or a MACB. For registers
788 * and bitfields that are common across both devices, use macb_{read,write}l
789 * to avoid the cost of the conditional.
790 */
791 #define macb_or_gem_writel(__bp, __reg, __value) \
792 ({ \
793 if (macb_is_gem((__bp))) \
794 gem_writel((__bp), __reg, __value); \
795 else \
796 macb_writel((__bp), __reg, __value); \
797 })
798
799 #define macb_or_gem_readl(__bp, __reg) \
800 ({ \
801 u32 __v; \
802 if (macb_is_gem((__bp))) \
803 __v = gem_readl((__bp), __reg); \
804 else \
805 __v = macb_readl((__bp), __reg); \
806 __v; \
807 })
808
809 #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
810
811 /* struct macb_dma_desc - Hardware DMA descriptor
812 * @addr: DMA address of data buffer
813 * @ctrl: Control and status bits
814 */
815 struct macb_dma_desc {
816 u32 addr;
817 u32 ctrl;
818 };
819
820 #ifdef MACB_EXT_DESC
821 #define HW_DMA_CAP_32B 0
822 #define HW_DMA_CAP_64B (1 << 0)
823 #define HW_DMA_CAP_PTP (1 << 1)
824 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
825
826 struct macb_dma_desc_64 {
827 u32 addrh;
828 u32 resvd;
829 };
830
831 struct macb_dma_desc_ptp {
832 u32 ts_1;
833 u32 ts_2;
834 };
835 #endif
836
837 /* DMA descriptor bitfields */
838 #define MACB_RX_USED_OFFSET 0
839 #define MACB_RX_USED_SIZE 1
840 #define MACB_RX_WRAP_OFFSET 1
841 #define MACB_RX_WRAP_SIZE 1
842 #define MACB_RX_WADDR_OFFSET 2
843 #define MACB_RX_WADDR_SIZE 30
844
845 #define MACB_RX_FRMLEN_OFFSET 0
846 #define MACB_RX_FRMLEN_SIZE 12
847 #define MACB_RX_OFFSET_OFFSET 12
848 #define MACB_RX_OFFSET_SIZE 2
849 #define MACB_RX_SOF_OFFSET 14
850 #define MACB_RX_SOF_SIZE 1
851 #define MACB_RX_EOF_OFFSET 15
852 #define MACB_RX_EOF_SIZE 1
853 #define MACB_RX_CFI_OFFSET 16
854 #define MACB_RX_CFI_SIZE 1
855 #define MACB_RX_VLAN_PRI_OFFSET 17
856 #define MACB_RX_VLAN_PRI_SIZE 3
857 #define MACB_RX_PRI_TAG_OFFSET 20
858 #define MACB_RX_PRI_TAG_SIZE 1
859 #define MACB_RX_VLAN_TAG_OFFSET 21
860 #define MACB_RX_VLAN_TAG_SIZE 1
861 #define MACB_RX_TYPEID_MATCH_OFFSET 22
862 #define MACB_RX_TYPEID_MATCH_SIZE 1
863 #define MACB_RX_SA4_MATCH_OFFSET 23
864 #define MACB_RX_SA4_MATCH_SIZE 1
865 #define MACB_RX_SA3_MATCH_OFFSET 24
866 #define MACB_RX_SA3_MATCH_SIZE 1
867 #define MACB_RX_SA2_MATCH_OFFSET 25
868 #define MACB_RX_SA2_MATCH_SIZE 1
869 #define MACB_RX_SA1_MATCH_OFFSET 26
870 #define MACB_RX_SA1_MATCH_SIZE 1
871 #define MACB_RX_EXT_MATCH_OFFSET 28
872 #define MACB_RX_EXT_MATCH_SIZE 1
873 #define MACB_RX_UHASH_MATCH_OFFSET 29
874 #define MACB_RX_UHASH_MATCH_SIZE 1
875 #define MACB_RX_MHASH_MATCH_OFFSET 30
876 #define MACB_RX_MHASH_MATCH_SIZE 1
877 #define MACB_RX_BROADCAST_OFFSET 31
878 #define MACB_RX_BROADCAST_SIZE 1
879
880 #define MACB_RX_FRMLEN_MASK 0xFFF
881 #define MACB_RX_JFRMLEN_MASK 0x3FFF
882
883 /* RX checksum offload disabled: bit 24 clear in NCFGR */
884 #define GEM_RX_TYPEID_MATCH_OFFSET 22
885 #define GEM_RX_TYPEID_MATCH_SIZE 2
886
887 /* RX checksum offload enabled: bit 24 set in NCFGR */
888 #define GEM_RX_CSUM_OFFSET 22
889 #define GEM_RX_CSUM_SIZE 2
890
891 #define MACB_TX_FRMLEN_OFFSET 0
892 #define MACB_TX_FRMLEN_SIZE 11
893 #define MACB_TX_LAST_OFFSET 15
894 #define MACB_TX_LAST_SIZE 1
895 #define MACB_TX_NOCRC_OFFSET 16
896 #define MACB_TX_NOCRC_SIZE 1
897 #define MACB_MSS_MFS_OFFSET 16
898 #define MACB_MSS_MFS_SIZE 14
899 #define MACB_TX_LSO_OFFSET 17
900 #define MACB_TX_LSO_SIZE 2
901 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
902 #define MACB_TX_TCP_SEQ_SRC_SIZE 1
903 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
904 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
905 #define MACB_TX_UNDERRUN_OFFSET 28
906 #define MACB_TX_UNDERRUN_SIZE 1
907 #define MACB_TX_ERROR_OFFSET 29
908 #define MACB_TX_ERROR_SIZE 1
909 #define MACB_TX_WRAP_OFFSET 30
910 #define MACB_TX_WRAP_SIZE 1
911 #define MACB_TX_USED_OFFSET 31
912 #define MACB_TX_USED_SIZE 1
913
914 #define GEM_TX_FRMLEN_OFFSET 0
915 #define GEM_TX_FRMLEN_SIZE 14
916
917 /* Buffer descriptor constants */
918 #define GEM_RX_CSUM_NONE 0
919 #define GEM_RX_CSUM_IP_ONLY 1
920 #define GEM_RX_CSUM_IP_TCP 2
921 #define GEM_RX_CSUM_IP_UDP 3
922
923 /* limit RX checksum offload to TCP and UDP packets */
924 #define GEM_RX_CSUM_CHECKED_MASK 2
925
926 /* Scaled PPM fraction */
927 #define PPM_FRACTION 16
928
929 /* struct macb_tx_skb - data about an skb which is being transmitted
930 * @skb: skb currently being transmitted, only set for the last buffer
931 * of the frame
932 * @mapping: DMA address of the skb's fragment buffer
933 * @size: size of the DMA mapped buffer
934 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
935 * false when buffer was mapped with dma_map_single()
936 */
937 struct macb_tx_skb {
938 struct sk_buff *skb;
939 dma_addr_t mapping;
940 size_t size;
941 bool mapped_as_page;
942 };
943
944 /* Hardware-collected statistics. Used when updating the network
945 * device stats by a periodic timer.
946 */
947 struct macb_stats {
948 u32 rx_pause_frames;
949 u32 tx_ok;
950 u32 tx_single_cols;
951 u32 tx_multiple_cols;
952 u32 rx_ok;
953 u32 rx_fcs_errors;
954 u32 rx_align_errors;
955 u32 tx_deferred;
956 u32 tx_late_cols;
957 u32 tx_excessive_cols;
958 u32 tx_underruns;
959 u32 tx_carrier_errors;
960 u32 rx_resource_errors;
961 u32 rx_overruns;
962 u32 rx_symbol_errors;
963 u32 rx_oversize_pkts;
964 u32 rx_jabbers;
965 u32 rx_undersize_pkts;
966 u32 sqe_test_errors;
967 u32 rx_length_mismatch;
968 u32 tx_pause_frames;
969 };
970
971 struct gem_stats {
972 u32 tx_octets_31_0;
973 u32 tx_octets_47_32;
974 u32 tx_frames;
975 u32 tx_broadcast_frames;
976 u32 tx_multicast_frames;
977 u32 tx_pause_frames;
978 u32 tx_64_byte_frames;
979 u32 tx_65_127_byte_frames;
980 u32 tx_128_255_byte_frames;
981 u32 tx_256_511_byte_frames;
982 u32 tx_512_1023_byte_frames;
983 u32 tx_1024_1518_byte_frames;
984 u32 tx_greater_than_1518_byte_frames;
985 u32 tx_underrun;
986 u32 tx_single_collision_frames;
987 u32 tx_multiple_collision_frames;
988 u32 tx_excessive_collisions;
989 u32 tx_late_collisions;
990 u32 tx_deferred_frames;
991 u32 tx_carrier_sense_errors;
992 u32 rx_octets_31_0;
993 u32 rx_octets_47_32;
994 u32 rx_frames;
995 u32 rx_broadcast_frames;
996 u32 rx_multicast_frames;
997 u32 rx_pause_frames;
998 u32 rx_64_byte_frames;
999 u32 rx_65_127_byte_frames;
1000 u32 rx_128_255_byte_frames;
1001 u32 rx_256_511_byte_frames;
1002 u32 rx_512_1023_byte_frames;
1003 u32 rx_1024_1518_byte_frames;
1004 u32 rx_greater_than_1518_byte_frames;
1005 u32 rx_undersized_frames;
1006 u32 rx_oversize_frames;
1007 u32 rx_jabbers;
1008 u32 rx_frame_check_sequence_errors;
1009 u32 rx_length_field_frame_errors;
1010 u32 rx_symbol_errors;
1011 u32 rx_alignment_errors;
1012 u32 rx_resource_errors;
1013 u32 rx_overruns;
1014 u32 rx_ip_header_checksum_errors;
1015 u32 rx_tcp_checksum_errors;
1016 u32 rx_udp_checksum_errors;
1017 };
1018
1019 /* Describes the name and offset of an individual statistic register, as
1020 * returned by `ethtool -S`. Also describes which net_device_stats statistics
1021 * this register should contribute to.
1022 */
1023 struct gem_statistic {
1024 char stat_string[ETH_GSTRING_LEN];
1025 int offset;
1026 u32 stat_bits;
1027 };
1028
1029 /* Bitfield defs for net_device_stat statistics */
1030 #define GEM_NDS_RXERR_OFFSET 0
1031 #define GEM_NDS_RXLENERR_OFFSET 1
1032 #define GEM_NDS_RXOVERERR_OFFSET 2
1033 #define GEM_NDS_RXCRCERR_OFFSET 3
1034 #define GEM_NDS_RXFRAMEERR_OFFSET 4
1035 #define GEM_NDS_RXFIFOERR_OFFSET 5
1036 #define GEM_NDS_TXERR_OFFSET 6
1037 #define GEM_NDS_TXABORTEDERR_OFFSET 7
1038 #define GEM_NDS_TXCARRIERERR_OFFSET 8
1039 #define GEM_NDS_TXFIFOERR_OFFSET 9
1040 #define GEM_NDS_COLLISIONS_OFFSET 10
1041
1042 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
1043 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
1044 .stat_string = title, \
1045 .offset = GEM_##name, \
1046 .stat_bits = bits \
1047 }
1048
1049 /* list of gem statistic registers. The names MUST match the
1050 * corresponding GEM_* definitions.
1051 */
1052 static const struct gem_statistic gem_statistics[] = {
1053 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
1054 GEM_STAT_TITLE(TXCNT, "tx_frames"),
1055 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
1056 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
1057 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
1058 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
1059 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
1060 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
1061 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
1062 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
1063 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
1064 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
1065 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
1066 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
1067 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
1068 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1069 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
1070 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1071 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
1072 GEM_BIT(NDS_TXERR)|
1073 GEM_BIT(NDS_TXABORTEDERR)|
1074 GEM_BIT(NDS_COLLISIONS)),
1075 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
1076 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1077 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
1078 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
1079 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1080 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
1081 GEM_STAT_TITLE(RXCNT, "rx_frames"),
1082 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
1083 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
1084 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1085 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1086 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1087 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1088 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1089 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1090 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1091 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1092 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1093 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1094 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1095 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1096 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1097 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1098 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1099 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1100 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1101 GEM_BIT(NDS_RXERR)),
1102 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1103 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1104 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1105 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1106 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1107 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1108 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1109 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1110 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1111 GEM_BIT(NDS_RXERR)),
1112 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1113 GEM_BIT(NDS_RXERR)),
1114 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1115 GEM_BIT(NDS_RXERR)),
1116 };
1117
1118 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1119
1120 #define QUEUE_STAT_TITLE(title) { \
1121 .stat_string = title, \
1122 }
1123
1124 /* per queue statistics, each should be unsigned long type */
1125 struct queue_stats {
1126 union {
1127 unsigned long first;
1128 unsigned long rx_packets;
1129 };
1130 unsigned long rx_bytes;
1131 unsigned long rx_dropped;
1132 unsigned long tx_packets;
1133 unsigned long tx_bytes;
1134 unsigned long tx_dropped;
1135 };
1136
1137 static const struct gem_statistic queue_statistics[] = {
1138 QUEUE_STAT_TITLE("rx_packets"),
1139 QUEUE_STAT_TITLE("rx_bytes"),
1140 QUEUE_STAT_TITLE("rx_dropped"),
1141 QUEUE_STAT_TITLE("tx_packets"),
1142 QUEUE_STAT_TITLE("tx_bytes"),
1143 QUEUE_STAT_TITLE("tx_dropped"),
1144 };
1145
1146 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1147
1148 struct macb;
1149 struct macb_queue;
1150
1151 struct macb_or_gem_ops {
1152 int (*mog_alloc_rx_buffers)(struct macb *bp);
1153 void (*mog_free_rx_buffers)(struct macb *bp);
1154 void (*mog_init_rings)(struct macb *bp);
1155 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1156 int budget);
1157 };
1158
1159 /* MACB-PTP interface: adapt to platform needs. */
1160 struct macb_ptp_info {
1161 void (*ptp_init)(struct net_device *ndev);
1162 void (*ptp_remove)(struct net_device *ndev);
1163 s32 (*get_ptp_max_adj)(void);
1164 unsigned int (*get_tsu_rate)(struct macb *bp);
1165 int (*get_ts_info)(struct net_device *dev,
1166 struct ethtool_ts_info *info);
1167 int (*get_hwtst)(struct net_device *netdev,
1168 struct ifreq *ifr);
1169 int (*set_hwtst)(struct net_device *netdev,
1170 struct ifreq *ifr, int cmd);
1171 };
1172
1173 struct macb_pm_data {
1174 u32 scrt2;
1175 u32 usrio;
1176 };
1177
1178 struct macb_usrio_config {
1179 u32 mii;
1180 u32 rmii;
1181 u32 rgmii;
1182 u32 refclk;
1183 u32 hdfctlen;
1184 };
1185
1186 struct macb_config {
1187 u32 caps;
1188 unsigned int dma_burst_length;
1189 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1190 struct clk **hclk, struct clk **tx_clk,
1191 struct clk **rx_clk, struct clk **tsu_clk);
1192 int (*init)(struct platform_device *pdev);
1193 unsigned int max_tx_length;
1194 int jumbo_max_len;
1195 const struct macb_usrio_config *usrio;
1196 };
1197
1198 struct tsu_incr {
1199 u32 sub_ns;
1200 u32 ns;
1201 };
1202
1203 struct macb_queue {
1204 struct macb *bp;
1205 int irq;
1206
1207 unsigned int ISR;
1208 unsigned int IER;
1209 unsigned int IDR;
1210 unsigned int IMR;
1211 unsigned int TBQP;
1212 unsigned int TBQPH;
1213 unsigned int RBQS;
1214 unsigned int RBQP;
1215 unsigned int RBQPH;
1216
1217 /* Lock to protect tx_head and tx_tail */
1218 spinlock_t tx_ptr_lock;
1219 unsigned int tx_head, tx_tail;
1220 struct macb_dma_desc *tx_ring;
1221 struct macb_tx_skb *tx_skb;
1222 dma_addr_t tx_ring_dma;
1223 struct work_struct tx_error_task;
1224 bool txubr_pending;
1225 struct napi_struct napi_tx;
1226
1227 dma_addr_t rx_ring_dma;
1228 dma_addr_t rx_buffers_dma;
1229 unsigned int rx_tail;
1230 unsigned int rx_prepared_head;
1231 struct macb_dma_desc *rx_ring;
1232 struct sk_buff **rx_skbuff;
1233 void *rx_buffers;
1234 struct napi_struct napi_rx;
1235 struct queue_stats stats;
1236 };
1237
1238 struct ethtool_rx_fs_item {
1239 struct ethtool_rx_flow_spec fs;
1240 struct list_head list;
1241 };
1242
1243 struct ethtool_rx_fs_list {
1244 struct list_head list;
1245 unsigned int count;
1246 };
1247
1248 struct macb {
1249 void __iomem *regs;
1250 bool native_io;
1251
1252 /* hardware IO accessors */
1253 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1254 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1255
1256 size_t rx_buffer_size;
1257
1258 unsigned int rx_ring_size;
1259 unsigned int tx_ring_size;
1260
1261 unsigned int num_queues;
1262 unsigned int queue_mask;
1263 struct macb_queue queues[MACB_MAX_QUEUES];
1264
1265 spinlock_t lock;
1266 struct platform_device *pdev;
1267 struct clk *pclk;
1268 struct clk *hclk;
1269 struct clk *tx_clk;
1270 struct clk *rx_clk;
1271 struct clk *tsu_clk;
1272 struct net_device *dev;
1273 /* Protects hw_stats and ethtool_stats */
1274 spinlock_t stats_lock;
1275 union {
1276 struct macb_stats macb;
1277 struct gem_stats gem;
1278 } hw_stats;
1279
1280 struct macb_or_gem_ops macbgem_ops;
1281
1282 struct mii_bus *mii_bus;
1283 struct phylink *phylink;
1284 struct phylink_config phylink_config;
1285 struct phylink_pcs phylink_usx_pcs;
1286 struct phylink_pcs phylink_sgmii_pcs;
1287
1288 u32 caps;
1289 unsigned int dma_burst_length;
1290
1291 phy_interface_t phy_interface;
1292
1293 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
1294 struct macb_tx_skb rm9200_txq[2];
1295 unsigned int max_tx_length;
1296
1297 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1298
1299 unsigned int rx_frm_len_mask;
1300 unsigned int jumbo_max_len;
1301
1302 u32 wol;
1303
1304 /* holds value of rx watermark value for pbuf_rxcutthru register */
1305 u32 rx_watermark;
1306
1307 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1308
1309 struct phy *sgmii_phy; /* for ZynqMP SGMII mode */
1310
1311 #ifdef MACB_EXT_DESC
1312 uint8_t hw_dma_cap;
1313 #endif
1314 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1315 unsigned int tsu_rate;
1316 struct ptp_clock *ptp_clock;
1317 struct ptp_clock_info ptp_clock_info;
1318 struct tsu_incr tsu_incr;
1319 struct hwtstamp_config tstamp_config;
1320
1321 /* RX queue filer rule set*/
1322 struct ethtool_rx_fs_list rx_fs_list;
1323 spinlock_t rx_fs_lock;
1324 unsigned int max_tuples;
1325
1326 struct tasklet_struct hresp_err_tasklet;
1327
1328 int rx_bd_rd_prefetch;
1329 int tx_bd_rd_prefetch;
1330
1331 u32 rx_intr_mask;
1332
1333 struct macb_pm_data pm_data;
1334 const struct macb_usrio_config *usrio;
1335 };
1336
1337 #ifdef CONFIG_MACB_USE_HWSTAMP
1338 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1339 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1340 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1341
1342 enum macb_bd_control {
1343 TSTAMP_DISABLED,
1344 TSTAMP_FRAME_PTP_EVENT_ONLY,
1345 TSTAMP_ALL_PTP_FRAMES,
1346 TSTAMP_ALL_FRAMES,
1347 };
1348
1349 void gem_ptp_init(struct net_device *ndev);
1350 void gem_ptp_remove(struct net_device *ndev);
1351 void gem_ptp_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1352 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
gem_ptp_do_txstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1353 static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1354 {
1355 if (bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1356 return;
1357
1358 gem_ptp_txstamp(bp, skb, desc);
1359 }
1360
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1361 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1362 {
1363 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1364 return;
1365
1366 gem_ptp_rxstamp(bp, skb, desc);
1367 }
1368 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1369 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1370 #else
gem_ptp_init(struct net_device * ndev)1371 static inline void gem_ptp_init(struct net_device *ndev) { }
gem_ptp_remove(struct net_device * ndev)1372 static inline void gem_ptp_remove(struct net_device *ndev) { }
1373
gem_ptp_do_txstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1374 static inline void gem_ptp_do_txstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1375 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1376 #endif
1377
macb_is_gem(struct macb * bp)1378 static inline bool macb_is_gem(struct macb *bp)
1379 {
1380 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1381 }
1382
gem_has_ptp(struct macb * bp)1383 static inline bool gem_has_ptp(struct macb *bp)
1384 {
1385 return IS_ENABLED(CONFIG_MACB_USE_HWSTAMP) && (bp->caps & MACB_CAPS_GEM_HAS_PTP);
1386 }
1387
1388 /**
1389 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
1390 * @pclk: platform clock
1391 * @hclk: AHB clock
1392 */
1393 struct macb_platform_data {
1394 struct clk *pclk;
1395 struct clk *hclk;
1396 };
1397
1398 #endif /* _MACB_H */
1399