1 /* 2 * ARM kernel loader. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/datadir.h" 12 #include "qemu/error-report.h" 13 #include "qapi/error.h" 14 #include <libfdt.h> 15 #include "hw/arm/boot.h" 16 #include "hw/arm/linux-boot-if.h" 17 #include "cpu.h" 18 #include "exec/tswap.h" 19 #include "exec/target_page.h" 20 #include "system/kvm.h" 21 #include "system/tcg.h" 22 #include "system/system.h" 23 #include "system/memory.h" 24 #include "system/numa.h" 25 #include "hw/boards.h" 26 #include "system/reset.h" 27 #include "hw/loader.h" 28 #include "hw/mem/memory-device.h" 29 #include "elf.h" 30 #include "system/device_tree.h" 31 #include "qemu/config-file.h" 32 #include "qemu/option.h" 33 #include "qemu/units.h" 34 #include "qemu/bswap.h" 35 36 /* Kernel boot protocol is specified in the kernel docs 37 * Documentation/arm/Booting and Documentation/arm64/booting.txt 38 * They have different preferred image load offsets from system RAM base. 39 */ 40 #define KERNEL_ARGS_ADDR 0x100 41 #define KERNEL_NOLOAD_ADDR 0x02000000 42 #define KERNEL_LOAD_ADDR 0x00010000 43 #define KERNEL64_LOAD_ADDR 0x00080000 44 45 #define ARM64_TEXT_OFFSET_OFFSET 8 46 #define ARM64_MAGIC_OFFSET 56 47 48 #define BOOTLOADER_MAX_SIZE (4 * KiB) 49 50 AddressSpace *arm_boot_address_space(ARMCPU *cpu, 51 const struct arm_boot_info *info) 52 { 53 /* Return the address space to use for bootloader reads and writes. 54 * We prefer the secure address space if the CPU has it and we're 55 * going to boot the guest into it. 56 */ 57 int asidx; 58 CPUState *cs = CPU(cpu); 59 60 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { 61 asidx = ARMASIdx_S; 62 } else { 63 asidx = ARMASIdx_NS; 64 } 65 66 return cpu_get_address_space(cs, asidx); 67 } 68 69 static const ARMInsnFixup bootloader_aarch64[] = { 70 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ 71 { 0xaa1f03e1 }, /* mov x1, xzr */ 72 { 0xaa1f03e2 }, /* mov x2, xzr */ 73 { 0xaa1f03e3 }, /* mov x3, xzr */ 74 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */ 75 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */ 76 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */ 77 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */ 78 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */ 79 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */ 80 { 0, FIXUP_TERMINATOR } 81 }; 82 83 /* A very small bootloader: call the board-setup code (if needed), 84 * set r0-r2, then jump to the kernel. 85 * If we're not calling boot setup code then we don't copy across 86 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array. 87 */ 88 89 static const ARMInsnFixup bootloader[] = { 90 { 0xe28fe004 }, /* add lr, pc, #4 */ 91 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */ 92 { 0, FIXUP_BOARD_SETUP }, 93 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3 94 { 0xe3a00000 }, /* mov r0, #0 */ 95 { 0xe59f1004 }, /* ldr r1, [pc, #4] */ 96 { 0xe59f2004 }, /* ldr r2, [pc, #4] */ 97 { 0xe59ff004 }, /* ldr pc, [pc, #4] */ 98 { 0, FIXUP_BOARDID }, 99 { 0, FIXUP_ARGPTR_LO }, 100 { 0, FIXUP_ENTRYPOINT_LO }, 101 { 0, FIXUP_TERMINATOR } 102 }; 103 104 /* Handling for secondary CPU boot in a multicore system. 105 * Unlike the uniprocessor/primary CPU boot, this is platform 106 * dependent. The default code here is based on the secondary 107 * CPU boot protocol used on realview/vexpress boards, with 108 * some parameterisation to increase its flexibility. 109 * QEMU platform models for which this code is not appropriate 110 * should override write_secondary_boot and secondary_cpu_reset_hook 111 * instead. 112 * 113 * This code enables the interrupt controllers for the secondary 114 * CPUs and then puts all the secondary CPUs into a loop waiting 115 * for an interprocessor interrupt and polling a configurable 116 * location for the kernel secondary CPU entry point. 117 */ 118 #define DSB_INSN 0xf57ff04f 119 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ 120 121 static const ARMInsnFixup smpboot[] = { 122 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */ 123 { 0xe59f0028 }, /* ldr r0, bootreg_addr */ 124 { 0xe3a01001 }, /* mov r1, #1 */ 125 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */ 126 { 0xe3a010ff }, /* mov r1, #0xff */ 127 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */ 128 { 0, FIXUP_DSB }, /* dsb */ 129 { 0xe320f003 }, /* wfi */ 130 { 0xe5901000 }, /* ldr r1, [r0] */ 131 { 0xe1110001 }, /* tst r1, r1 */ 132 { 0x0afffffb }, /* beq <wfi> */ 133 { 0xe12fff11 }, /* bx r1 */ 134 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */ 135 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */ 136 { 0, FIXUP_TERMINATOR } 137 }; 138 139 void arm_write_bootloader(const char *name, 140 AddressSpace *as, hwaddr addr, 141 const ARMInsnFixup *insns, 142 const uint32_t *fixupcontext) 143 { 144 /* Fix up the specified bootloader fragment and write it into 145 * guest memory using rom_add_blob_fixed(). fixupcontext is 146 * an array giving the values to write in for the fixup types 147 * which write a value into the code array. 148 */ 149 int i, len; 150 uint32_t *code; 151 152 len = 0; 153 while (insns[len].fixup != FIXUP_TERMINATOR) { 154 len++; 155 } 156 157 code = g_new0(uint32_t, len); 158 159 for (i = 0; i < len; i++) { 160 uint32_t insn = insns[i].insn; 161 FixupType fixup = insns[i].fixup; 162 163 switch (fixup) { 164 case FIXUP_NONE: 165 break; 166 case FIXUP_BOARDID: 167 case FIXUP_BOARD_SETUP: 168 case FIXUP_ARGPTR_LO: 169 case FIXUP_ARGPTR_HI: 170 case FIXUP_ENTRYPOINT_LO: 171 case FIXUP_ENTRYPOINT_HI: 172 case FIXUP_GIC_CPU_IF: 173 case FIXUP_BOOTREG: 174 case FIXUP_DSB: 175 insn = fixupcontext[fixup]; 176 break; 177 default: 178 abort(); 179 } 180 code[i] = tswap32(insn); 181 } 182 183 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); 184 185 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as); 186 187 g_free(code); 188 } 189 190 static void default_write_secondary(ARMCPU *cpu, 191 const struct arm_boot_info *info) 192 { 193 uint32_t fixupcontext[FIXUP_MAX]; 194 AddressSpace *as = arm_boot_address_space(cpu, info); 195 196 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr; 197 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr; 198 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 199 fixupcontext[FIXUP_DSB] = DSB_INSN; 200 } else { 201 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN; 202 } 203 204 arm_write_bootloader("smpboot", as, info->smp_loader_start, 205 smpboot, fixupcontext); 206 } 207 208 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, 209 const struct arm_boot_info *info, 210 hwaddr mvbar_addr) 211 { 212 AddressSpace *as = arm_boot_address_space(cpu, info); 213 int n; 214 uint32_t mvbar_blob[] = { 215 /* mvbar_addr: secure monitor vectors 216 * Default unimplemented and unused vectors to spin. Makes it 217 * easier to debug (as opposed to the CPU running away). 218 */ 219 0xeafffffe, /* (spin) */ 220 0xeafffffe, /* (spin) */ 221 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ 222 0xeafffffe, /* (spin) */ 223 0xeafffffe, /* (spin) */ 224 0xeafffffe, /* (spin) */ 225 0xeafffffe, /* (spin) */ 226 0xeafffffe, /* (spin) */ 227 }; 228 uint32_t board_setup_blob[] = { 229 /* board setup addr */ 230 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ 231 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ 232 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 233 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 234 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 235 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ 236 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ 237 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ 238 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ 239 0xe1600070, /* smc #0 ;call monitor to flush SCR */ 240 0xe1a0f001, /* mov pc, r1 ;return */ 241 }; 242 243 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ 244 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100); 245 246 /* check that these blobs don't overlap */ 247 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) 248 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); 249 250 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { 251 mvbar_blob[n] = tswap32(mvbar_blob[n]); 252 } 253 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), 254 mvbar_addr, as); 255 256 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { 257 board_setup_blob[n] = tswap32(board_setup_blob[n]); 258 } 259 rom_add_blob_fixed_as("board-setup", board_setup_blob, 260 sizeof(board_setup_blob), info->board_setup_addr, as); 261 } 262 263 static void default_reset_secondary(ARMCPU *cpu, 264 const struct arm_boot_info *info) 265 { 266 AddressSpace *as = arm_boot_address_space(cpu, info); 267 CPUState *cs = CPU(cpu); 268 269 address_space_stl_notdirty(as, info->smp_bootreg_addr, 270 0, MEMTXATTRS_UNSPECIFIED, NULL); 271 cpu_set_pc(cs, info->smp_loader_start); 272 } 273 274 static inline bool have_dtb(const struct arm_boot_info *info) 275 { 276 return info->dtb_filename || info->get_dtb; 277 } 278 279 #define WRITE_WORD(p, value) do { \ 280 address_space_stl_notdirty(as, p, value, \ 281 MEMTXATTRS_UNSPECIFIED, NULL); \ 282 p += 4; \ 283 } while (0) 284 285 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) 286 { 287 int initrd_size = info->initrd_size; 288 hwaddr base = info->loader_start; 289 hwaddr p; 290 291 p = base + KERNEL_ARGS_ADDR; 292 /* ATAG_CORE */ 293 WRITE_WORD(p, 5); 294 WRITE_WORD(p, 0x54410001); 295 WRITE_WORD(p, 1); 296 WRITE_WORD(p, 0x1000); 297 WRITE_WORD(p, 0); 298 /* ATAG_MEM */ 299 /* TODO: handle multiple chips on one ATAG list */ 300 WRITE_WORD(p, 4); 301 WRITE_WORD(p, 0x54410002); 302 WRITE_WORD(p, info->ram_size); 303 WRITE_WORD(p, info->loader_start); 304 if (initrd_size) { 305 /* ATAG_INITRD2 */ 306 WRITE_WORD(p, 4); 307 WRITE_WORD(p, 0x54420005); 308 WRITE_WORD(p, info->initrd_start); 309 WRITE_WORD(p, initrd_size); 310 } 311 if (info->kernel_cmdline && *info->kernel_cmdline) { 312 /* ATAG_CMDLINE */ 313 int cmdline_size; 314 315 cmdline_size = strlen(info->kernel_cmdline); 316 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 317 info->kernel_cmdline, cmdline_size + 1); 318 cmdline_size = (cmdline_size >> 2) + 1; 319 WRITE_WORD(p, cmdline_size + 2); 320 WRITE_WORD(p, 0x54410009); 321 p += cmdline_size * 4; 322 } 323 if (info->atag_board) { 324 /* ATAG_BOARD */ 325 int atag_board_len; 326 uint8_t atag_board_buf[0x1000]; 327 328 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; 329 WRITE_WORD(p, (atag_board_len + 8) >> 2); 330 WRITE_WORD(p, 0x414f4d50); 331 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 332 atag_board_buf, atag_board_len); 333 p += atag_board_len; 334 } 335 /* ATAG_END */ 336 WRITE_WORD(p, 0); 337 WRITE_WORD(p, 0); 338 } 339 340 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, 341 uint32_t scells, hwaddr mem_len, 342 int numa_node_id) 343 { 344 char *nodename; 345 int ret; 346 347 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); 348 qemu_fdt_add_subnode(fdt, nodename); 349 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 350 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, 351 scells, mem_len); 352 if (ret < 0) { 353 goto out; 354 } 355 356 /* only set the NUMA ID if it is specified */ 357 if (numa_node_id >= 0) { 358 ret = qemu_fdt_setprop_cell(fdt, nodename, 359 "numa-node-id", numa_node_id); 360 } 361 out: 362 g_free(nodename); 363 return ret; 364 } 365 366 static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu) 367 { 368 uint32_t cpu_suspend_fn; 369 uint32_t cpu_off_fn; 370 uint32_t cpu_on_fn; 371 uint32_t migrate_fn; 372 const char *psci_method; 373 int64_t psci_conduit; 374 int rc; 375 376 psci_conduit = object_property_get_int(OBJECT(armcpu), 377 "psci-conduit", 378 &error_abort); 379 switch (psci_conduit) { 380 case QEMU_PSCI_CONDUIT_DISABLED: 381 return; 382 case QEMU_PSCI_CONDUIT_HVC: 383 psci_method = "hvc"; 384 break; 385 case QEMU_PSCI_CONDUIT_SMC: 386 psci_method = "smc"; 387 break; 388 default: 389 g_assert_not_reached(); 390 } 391 392 /* 393 * A pre-existing /psci node might specify function ID values 394 * that don't match QEMU's PSCI implementation. Delete the whole 395 * node and put our own in instead. 396 */ 397 rc = fdt_path_offset(fdt, "/psci"); 398 if (rc >= 0) { 399 qemu_fdt_nop_node(fdt, "/psci"); 400 } 401 402 qemu_fdt_add_subnode(fdt, "/psci"); 403 if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) { 404 if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) { 405 const char comp[] = "arm,psci-0.2\0arm,psci"; 406 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 407 } else { 408 const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci"; 409 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); 410 } 411 412 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; 413 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { 414 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; 415 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; 416 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; 417 } else { 418 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; 419 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; 420 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; 421 } 422 } else { 423 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); 424 425 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; 426 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; 427 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; 428 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; 429 } 430 431 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer 432 * to the instruction that should be used to invoke PSCI functions. 433 * However, the device tree binding uses 'method' instead, so that is 434 * what we should use here. 435 */ 436 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method); 437 438 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); 439 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); 440 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); 441 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); 442 } 443 444 static int fdt_add_pmem_node(void *fdt, uint32_t acells, uint32_t scells, 445 int64_t mem_base, int64_t size, int64_t node) 446 { 447 int ret; 448 449 g_autofree char *nodename = g_strdup_printf("/pmem@%" PRIx64, mem_base); 450 451 qemu_fdt_add_subnode(fdt, nodename); 452 qemu_fdt_setprop_string(fdt, nodename, "compatible", "pmem-region"); 453 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, 454 mem_base, scells, size); 455 if (ret) { 456 return ret; 457 } 458 459 if (node >= 0) { 460 return qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", 461 node); 462 } 463 464 return 0; 465 } 466 467 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, 468 hwaddr addr_limit, AddressSpace *as, MachineState *ms, 469 ARMCPU *cpu) 470 { 471 void *fdt = NULL; 472 int size, rc, n = 0; 473 uint32_t acells, scells; 474 unsigned int i; 475 hwaddr mem_base, mem_len; 476 char **node_path; 477 g_autoptr(MemoryDeviceInfoList) md_list = NULL; 478 Error *err = NULL; 479 480 if (binfo->dtb_filename) { 481 char *filename; 482 filename = qemu_find_file(QEMU_FILE_TYPE_DTB, binfo->dtb_filename); 483 if (!filename) { 484 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); 485 goto fail; 486 } 487 488 fdt = load_device_tree(filename, &size); 489 if (!fdt) { 490 fprintf(stderr, "Couldn't open dtb file %s\n", filename); 491 g_free(filename); 492 goto fail; 493 } 494 g_free(filename); 495 } else { 496 fdt = binfo->get_dtb(binfo, &size); 497 if (!fdt) { 498 fprintf(stderr, "Board was unable to create a dtb blob\n"); 499 goto fail; 500 } 501 } 502 503 if (addr_limit > addr && size > (addr_limit - addr)) { 504 /* Installing the device tree blob at addr would exceed addr_limit. 505 * Whether this constitutes failure is up to the caller to decide, 506 * so just return 0 as size, i.e., no error. 507 */ 508 g_free(fdt); 509 return 0; 510 } 511 512 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 513 NULL, &error_fatal); 514 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 515 NULL, &error_fatal); 516 if (acells == 0 || scells == 0) { 517 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); 518 goto fail; 519 } 520 521 if (scells < 2 && binfo->ram_size >= 4 * GiB) { 522 /* This is user error so deserves a friendlier error message 523 * than the failure of setprop_sized_cells would provide 524 */ 525 fprintf(stderr, "qemu: dtb file not compatible with " 526 "RAM size > 4GB\n"); 527 goto fail; 528 } 529 530 /* nop all root nodes matching /memory or /memory@unit-address */ 531 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 532 if (err) { 533 error_report_err(err); 534 goto fail; 535 } 536 while (node_path[n]) { 537 if (g_str_has_prefix(node_path[n], "/memory")) { 538 qemu_fdt_nop_node(fdt, node_path[n]); 539 } 540 n++; 541 } 542 g_strfreev(node_path); 543 544 /* 545 * We drop all the memory nodes which correspond to empty NUMA nodes 546 * from the device tree, because the Linux NUMA binding document 547 * states they should not be generated. Linux will get the NUMA node 548 * IDs of the empty NUMA nodes from the distance map if they are needed. 549 * This means QEMU users may be obliged to provide command lines which 550 * configure distance maps when the empty NUMA node IDs are needed and 551 * Linux's default distance map isn't sufficient. 552 */ 553 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) { 554 mem_base = binfo->loader_start; 555 for (i = 0; i < ms->numa_state->num_nodes; i++) { 556 mem_len = ms->numa_state->nodes[i].node_mem; 557 if (!mem_len) { 558 continue; 559 } 560 561 rc = fdt_add_memory_node(fdt, acells, mem_base, 562 scells, mem_len, i); 563 if (rc < 0) { 564 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 565 mem_base); 566 goto fail; 567 } 568 569 mem_base += mem_len; 570 } 571 } else { 572 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, 573 scells, binfo->ram_size, -1); 574 if (rc < 0) { 575 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", 576 binfo->loader_start); 577 goto fail; 578 } 579 } 580 581 md_list = qmp_memory_device_list(); 582 for (MemoryDeviceInfoList *m = md_list; m != NULL; m = m->next) { 583 MemoryDeviceInfo *mi = m->value; 584 585 if (mi->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) { 586 PCDIMMDeviceInfo *di = mi->u.nvdimm.data; 587 588 rc = fdt_add_pmem_node(fdt, acells, scells, 589 di->addr, di->size, di->node); 590 if (rc < 0) { 591 fprintf(stderr, "couldn't add NVDIMM /pmem@%"PRIx64" node\n", 592 di->addr); 593 goto fail; 594 } 595 } 596 } 597 598 rc = fdt_path_offset(fdt, "/chosen"); 599 if (rc < 0) { 600 qemu_fdt_add_subnode(fdt, "/chosen"); 601 } 602 603 if (ms->kernel_cmdline && *ms->kernel_cmdline) { 604 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 605 ms->kernel_cmdline); 606 if (rc < 0) { 607 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 608 goto fail; 609 } 610 } 611 612 if (binfo->initrd_size) { 613 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", 614 acells, binfo->initrd_start); 615 if (rc < 0) { 616 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 617 goto fail; 618 } 619 620 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", 621 acells, 622 binfo->initrd_start + 623 binfo->initrd_size); 624 if (rc < 0) { 625 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 626 goto fail; 627 } 628 } 629 630 fdt_add_psci_node(fdt, cpu); 631 632 if (binfo->modify_dtb) { 633 binfo->modify_dtb(binfo, fdt); 634 } 635 636 /* Put the DTB into the memory map as a ROM image: this will ensure 637 * the DTB is copied again upon reset, even if addr points into RAM. 638 */ 639 rom_add_blob_fixed_as("dtb", fdt, size, addr, as); 640 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 641 rom_ptr_for_as(as, addr, size)); 642 643 if (fdt != ms->fdt) { 644 g_free(ms->fdt); 645 ms->fdt = fdt; 646 } 647 648 return size; 649 650 fail: 651 g_free(fdt); 652 return -1; 653 } 654 655 static void do_cpu_reset(void *opaque) 656 { 657 ARMCPU *cpu = opaque; 658 CPUState *cs = CPU(cpu); 659 CPUARMState *env = &cpu->env; 660 const struct arm_boot_info *info = env->boot_info; 661 662 cpu_reset(cs); 663 if (info) { 664 if (!info->is_linux) { 665 int i; 666 /* Jump to the entry point. */ 667 uint64_t entry = info->entry; 668 669 switch (info->endianness) { 670 case ARM_ENDIANNESS_LE: 671 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; 672 for (i = 1; i < 4; ++i) { 673 env->cp15.sctlr_el[i] &= ~SCTLR_EE; 674 } 675 env->uncached_cpsr &= ~CPSR_E; 676 break; 677 case ARM_ENDIANNESS_BE8: 678 env->cp15.sctlr_el[1] |= SCTLR_E0E; 679 for (i = 1; i < 4; ++i) { 680 env->cp15.sctlr_el[i] |= SCTLR_EE; 681 } 682 env->uncached_cpsr |= CPSR_E; 683 break; 684 case ARM_ENDIANNESS_BE32: 685 env->cp15.sctlr_el[1] |= SCTLR_B; 686 break; 687 case ARM_ENDIANNESS_UNKNOWN: 688 break; /* Board's decision */ 689 default: 690 g_assert_not_reached(); 691 } 692 693 cpu_set_pc(cs, entry); 694 } else { 695 /* 696 * If we are booting Linux then we might need to do so at: 697 * - AArch64 NS EL2 or NS EL1 698 * - AArch32 Secure SVC (EL3) 699 * - AArch32 NS Hyp (EL2) 700 * - AArch32 NS SVC (EL1) 701 * Configure the CPU in the way boot firmware would do to 702 * drop us down to the appropriate level. 703 */ 704 int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 705 706 if (env->aarch64) { 707 /* 708 * AArch64 kernels never boot in secure mode, and we don't 709 * support the secure_board_setup hook for AArch64. 710 */ 711 assert(!info->secure_boot); 712 assert(!info->secure_board_setup); 713 } else { 714 if (arm_feature(env, ARM_FEATURE_EL3) && 715 (info->secure_boot || 716 (info->secure_board_setup && cpu == info->primary_cpu))) { 717 /* Start this CPU in Secure SVC */ 718 target_el = 3; 719 } 720 } 721 722 arm_emulate_firmware_reset(cs, target_el); 723 724 if (cpu == info->primary_cpu) { 725 AddressSpace *as = arm_boot_address_space(cpu, info); 726 727 cpu_set_pc(cs, info->loader_start); 728 729 if (!have_dtb(info)) { 730 set_kernel_args(info, as); 731 } 732 } else if (info->secondary_cpu_reset_hook) { 733 info->secondary_cpu_reset_hook(cpu, info); 734 } 735 } 736 737 if (tcg_enabled()) { 738 arm_rebuild_hflags(env); 739 } 740 } 741 } 742 743 static int do_arm_linux_init(Object *obj, void *opaque) 744 { 745 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) { 746 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj); 747 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj); 748 struct arm_boot_info *info = opaque; 749 750 if (albifc->arm_linux_init) { 751 albifc->arm_linux_init(albif, info->secure_boot); 752 } 753 } 754 return 0; 755 } 756 757 static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry, 758 uint64_t *lowaddr, uint64_t *highaddr, 759 int elf_machine, AddressSpace *as) 760 { 761 bool elf_is64; 762 union { 763 Elf32_Ehdr h32; 764 Elf64_Ehdr h64; 765 } elf_header; 766 int data_swab = 0; 767 int elf_data_order; 768 ssize_t ret; 769 Error *err = NULL; 770 771 772 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err); 773 if (err) { 774 /* 775 * If the file is not an ELF file we silently return. 776 * The caller will fall back to try other formats. 777 */ 778 error_free(err); 779 return -1; 780 } 781 782 if (elf_is64) { 783 elf_data_order = elf_header.h64.e_ident[EI_DATA]; 784 info->endianness = elf_data_order == ELFDATA2MSB ? ARM_ENDIANNESS_BE8 785 : ARM_ENDIANNESS_LE; 786 } else { 787 elf_data_order = elf_header.h32.e_ident[EI_DATA]; 788 if (elf_data_order == ELFDATA2MSB) { 789 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) { 790 info->endianness = ARM_ENDIANNESS_BE8; 791 } else { 792 info->endianness = ARM_ENDIANNESS_BE32; 793 /* In BE32, the CPU has a different view of the per-byte 794 * address map than the rest of the system. BE32 ELF files 795 * are organised such that they can be programmed through 796 * the CPU's per-word byte-reversed view of the world. QEMU 797 * however loads ELF files independently of the CPU. So 798 * tell the ELF loader to byte reverse the data for us. 799 */ 800 data_swab = 2; 801 } 802 } else { 803 info->endianness = ARM_ENDIANNESS_LE; 804 } 805 } 806 807 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL, 808 pentry, lowaddr, highaddr, NULL, elf_data_order, 809 elf_machine, 1, data_swab, as); 810 if (ret <= 0) { 811 /* The header loaded but the image didn't */ 812 error_report("Couldn't load elf '%s': %s", 813 info->kernel_filename, load_elf_strerror(ret)); 814 exit(1); 815 } 816 817 return ret; 818 } 819 820 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, 821 hwaddr *entry, AddressSpace *as) 822 { 823 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; 824 uint64_t kernel_size = 0; 825 uint8_t *buffer; 826 ssize_t size; 827 828 /* On aarch64, it's the bootloader's job to uncompress the kernel. */ 829 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES, 830 &buffer); 831 832 if (size < 0) { 833 gsize len; 834 835 /* Load as raw file otherwise */ 836 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) { 837 return -1; 838 } 839 size = len; 840 841 /* Unpack the image if it is a EFI zboot image */ 842 if (unpack_efi_zboot_image(&buffer, &size) < 0) { 843 g_free(buffer); 844 return -1; 845 } 846 } 847 848 /* check the arm64 magic header value -- very old kernels may not have it */ 849 if (size > ARM64_MAGIC_OFFSET + 4 && 850 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) { 851 uint64_t hdrvals[2]; 852 853 /* The arm64 Image header has text_offset and image_size fields at 8 and 854 * 16 bytes into the Image header, respectively. The text_offset field 855 * is only valid if the image_size is non-zero. 856 */ 857 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); 858 859 kernel_size = le64_to_cpu(hdrvals[1]); 860 861 if (kernel_size != 0) { 862 kernel_load_offset = le64_to_cpu(hdrvals[0]); 863 864 /* 865 * We write our startup "bootloader" at the very bottom of RAM, 866 * so that bit can't be used for the image. Luckily the Image 867 * format specification is that the image requests only an offset 868 * from a 2MB boundary, not an absolute load address. So if the 869 * image requests an offset that might mean it overlaps with the 870 * bootloader, we can just load it starting at 2MB+offset rather 871 * than 0MB + offset. 872 */ 873 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) { 874 kernel_load_offset += 2 * MiB; 875 } 876 } 877 } 878 879 /* 880 * Kernels before v3.17 don't populate the image_size field, and 881 * raw images have no header. For those our best guess at the size 882 * is the size of the Image file itself. 883 */ 884 if (kernel_size == 0) { 885 kernel_size = size; 886 } 887 888 *entry = mem_base + kernel_load_offset; 889 rom_add_blob_fixed_as(filename, buffer, size, *entry, as); 890 891 g_free(buffer); 892 893 return kernel_size; 894 } 895 896 static void arm_setup_direct_kernel_boot(ARMCPU *cpu, 897 struct arm_boot_info *info) 898 { 899 /* Set up for a direct boot of a kernel image file. */ 900 CPUState *cs; 901 AddressSpace *as = arm_boot_address_space(cpu, info); 902 ssize_t kernel_size; 903 int initrd_size; 904 int is_linux = 0; 905 uint64_t elf_entry; 906 /* Addresses of first byte used and first byte not used by the image */ 907 uint64_t image_low_addr = 0, image_high_addr = 0; 908 int elf_machine; 909 hwaddr entry; 910 static const ARMInsnFixup *primary_loader; 911 uint64_t ram_end = info->loader_start + info->ram_size; 912 913 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 914 primary_loader = bootloader_aarch64; 915 elf_machine = EM_AARCH64; 916 } else { 917 primary_loader = bootloader; 918 if (!info->write_board_setup) { 919 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET; 920 } 921 elf_machine = EM_ARM; 922 } 923 924 /* Assume that raw images are linux kernels, and ELF images are not. */ 925 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, 926 &image_high_addr, elf_machine, as); 927 if (kernel_size > 0 && have_dtb(info)) { 928 /* 929 * If there is still some room left at the base of RAM, try and put 930 * the DTB there like we do for images loaded with -bios or -pflash. 931 */ 932 if (image_low_addr > info->loader_start 933 || image_high_addr < info->loader_start) { 934 /* 935 * Set image_low_addr as address limit for arm_load_dtb if it may be 936 * pointing into RAM, otherwise pass '0' (no limit) 937 */ 938 if (image_low_addr < info->loader_start) { 939 image_low_addr = 0; 940 } 941 info->dtb_start = info->loader_start; 942 info->dtb_limit = image_low_addr; 943 } 944 } 945 entry = elf_entry; 946 if (kernel_size < 0) { 947 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; 948 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, 949 &is_linux, NULL, NULL, as); 950 if (kernel_size >= 0) { 951 image_low_addr = loadaddr; 952 image_high_addr = image_low_addr + kernel_size; 953 } 954 } 955 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { 956 kernel_size = load_aarch64_image(info->kernel_filename, 957 info->loader_start, &entry, as); 958 is_linux = 1; 959 if (kernel_size >= 0) { 960 image_low_addr = entry; 961 image_high_addr = image_low_addr + kernel_size; 962 } 963 } else if (kernel_size < 0) { 964 /* 32-bit ARM */ 965 entry = info->loader_start + KERNEL_LOAD_ADDR; 966 kernel_size = load_image_targphys_as(info->kernel_filename, entry, 967 ram_end - KERNEL_LOAD_ADDR, as, 968 NULL); 969 is_linux = 1; 970 if (kernel_size >= 0) { 971 image_low_addr = entry; 972 image_high_addr = image_low_addr + kernel_size; 973 } 974 } 975 if (kernel_size < 0) { 976 error_report("could not load kernel '%s'", info->kernel_filename); 977 exit(1); 978 } 979 980 if (kernel_size > info->ram_size) { 981 error_report("kernel '%s' is too large to fit in RAM " 982 "(kernel size %zd, RAM size %" PRId64 ")", 983 info->kernel_filename, kernel_size, info->ram_size); 984 exit(1); 985 } 986 987 info->entry = entry; 988 989 /* 990 * We want to put the initrd far enough into RAM that when the 991 * kernel is uncompressed it will not clobber the initrd. However 992 * on boards without much RAM we must ensure that we still leave 993 * enough room for a decent sized initrd, and on boards with large 994 * amounts of RAM we must avoid the initrd being so far up in RAM 995 * that it is outside lowmem and inaccessible to the kernel. 996 * So for boards with less than 256MB of RAM we put the initrd 997 * halfway into RAM, and for boards with 256MB of RAM or more we put 998 * the initrd at 128MB. 999 * We also refuse to put the initrd somewhere that will definitely 1000 * overlay the kernel we just loaded, though for kernel formats which 1001 * don't tell us their exact size (eg self-decompressing 32-bit kernels) 1002 * we might still make a bad choice here. 1003 */ 1004 info->initrd_start = info->loader_start + 1005 MIN(info->ram_size / 2, 128 * MiB); 1006 if (image_high_addr) { 1007 info->initrd_start = MAX(info->initrd_start, image_high_addr); 1008 } 1009 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); 1010 1011 if (is_linux) { 1012 uint32_t fixupcontext[FIXUP_MAX]; 1013 1014 if (info->initrd_filename) { 1015 1016 if (info->initrd_start >= ram_end) { 1017 error_report("not enough space after kernel to load initrd"); 1018 exit(1); 1019 } 1020 1021 initrd_size = load_ramdisk_as(info->initrd_filename, 1022 info->initrd_start, 1023 ram_end - info->initrd_start, as); 1024 if (initrd_size < 0) { 1025 initrd_size = load_image_targphys_as(info->initrd_filename, 1026 info->initrd_start, 1027 ram_end - 1028 info->initrd_start, 1029 as, NULL); 1030 } 1031 if (initrd_size < 0) { 1032 error_report("could not load initrd '%s'", 1033 info->initrd_filename); 1034 exit(1); 1035 } 1036 if (info->initrd_start + initrd_size > ram_end) { 1037 error_report("could not load initrd '%s': " 1038 "too big to fit into RAM after the kernel", 1039 info->initrd_filename); 1040 exit(1); 1041 } 1042 } else { 1043 initrd_size = 0; 1044 } 1045 info->initrd_size = initrd_size; 1046 1047 fixupcontext[FIXUP_BOARDID] = info->board_id; 1048 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; 1049 1050 /* 1051 * for device tree boot, we pass the DTB directly in r2. Otherwise 1052 * we point to the kernel args. 1053 */ 1054 if (have_dtb(info)) { 1055 hwaddr align; 1056 1057 if (elf_machine == EM_AARCH64) { 1058 /* 1059 * Some AArch64 kernels on early bootup map the fdt region as 1060 * 1061 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] 1062 * 1063 * Let's play safe and prealign it to 2MB to give us some space. 1064 */ 1065 align = 2 * MiB; 1066 } else { 1067 /* 1068 * Some 32bit kernels will trash anything in the 4K page the 1069 * initrd ends in, so make sure the DTB isn't caught up in that. 1070 */ 1071 align = 4 * KiB; 1072 } 1073 1074 /* Place the DTB after the initrd in memory with alignment. */ 1075 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, 1076 align); 1077 if (info->dtb_start >= ram_end) { 1078 error_report("Not enough space for DTB after kernel/initrd"); 1079 exit(1); 1080 } 1081 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; 1082 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; 1083 } else { 1084 fixupcontext[FIXUP_ARGPTR_LO] = 1085 info->loader_start + KERNEL_ARGS_ADDR; 1086 fixupcontext[FIXUP_ARGPTR_HI] = 1087 (info->loader_start + KERNEL_ARGS_ADDR) >> 32; 1088 if (info->ram_size >= 4 * GiB) { 1089 error_report("RAM size must be less than 4GB to boot" 1090 " Linux kernel using ATAGS (try passing a device tree" 1091 " using -dtb)"); 1092 exit(1); 1093 } 1094 } 1095 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry; 1096 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32; 1097 1098 arm_write_bootloader("bootloader", as, info->loader_start, 1099 primary_loader, fixupcontext); 1100 1101 if (info->write_board_setup) { 1102 info->write_board_setup(cpu, info); 1103 } 1104 1105 /* 1106 * Notify devices which need to fake up firmware initialization 1107 * that we're doing a direct kernel boot. 1108 */ 1109 object_child_foreach_recursive(object_get_root(), 1110 do_arm_linux_init, info); 1111 } 1112 info->is_linux = is_linux; 1113 1114 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1115 ARM_CPU(cs)->env.boot_info = info; 1116 } 1117 } 1118 1119 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) 1120 { 1121 /* Set up for booting firmware (which might load a kernel via fw_cfg) */ 1122 1123 if (have_dtb(info)) { 1124 /* 1125 * If we have a device tree blob, but no kernel to supply it to (or 1126 * the kernel is supposed to be loaded by the bootloader), copy the 1127 * DTB to the base of RAM for the bootloader to pick up. 1128 */ 1129 info->dtb_start = info->loader_start; 1130 } 1131 1132 if (info->kernel_filename) { 1133 FWCfgState *fw_cfg; 1134 bool try_decompressing_kernel; 1135 1136 fw_cfg = fw_cfg_find(); 1137 1138 if (!fw_cfg) { 1139 error_report("This machine type does not support loading both " 1140 "a guest firmware/BIOS image and a guest kernel at " 1141 "the same time. You should change your QEMU command " 1142 "line to specify one or the other, but not both."); 1143 exit(1); 1144 } 1145 1146 try_decompressing_kernel = arm_feature(&cpu->env, 1147 ARM_FEATURE_AARCH64); 1148 1149 /* 1150 * Expose the kernel, the command line, and the initrd in fw_cfg. 1151 * We don't process them here at all, it's all left to the 1152 * firmware. 1153 */ 1154 load_image_to_fw_cfg(fw_cfg, 1155 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 1156 info->kernel_filename, 1157 try_decompressing_kernel); 1158 load_image_to_fw_cfg(fw_cfg, 1159 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 1160 info->initrd_filename, false); 1161 1162 if (info->kernel_cmdline) { 1163 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1164 strlen(info->kernel_cmdline) + 1); 1165 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 1166 info->kernel_cmdline); 1167 } 1168 } 1169 1170 /* 1171 * We will start from address 0 (typically a boot ROM image) in the 1172 * same way as hardware. Leave env->boot_info NULL, so that 1173 * do_cpu_reset() knows it does not need to alter the PC on reset. 1174 */ 1175 } 1176 1177 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) 1178 { 1179 CPUState *cs; 1180 AddressSpace *as = arm_boot_address_space(cpu, info); 1181 int boot_el; 1182 CPUARMState *env = &cpu->env; 1183 int nb_cpus = 0; 1184 1185 /* 1186 * CPU objects (unlike devices) are not automatically reset on system 1187 * reset, so we must always register a handler to do so. If we're 1188 * actually loading a kernel, the handler is also responsible for 1189 * arranging that we start it correctly. 1190 */ 1191 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1192 qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); 1193 nb_cpus++; 1194 } 1195 1196 /* 1197 * The board code is not supposed to set secure_board_setup unless 1198 * running its code in secure mode is actually possible, and KVM 1199 * doesn't support secure. 1200 */ 1201 assert(!(info->secure_board_setup && kvm_enabled())); 1202 info->kernel_filename = ms->kernel_filename; 1203 info->kernel_cmdline = ms->kernel_cmdline; 1204 info->initrd_filename = ms->initrd_filename; 1205 info->dtb_filename = ms->dtb; 1206 info->dtb_limit = 0; 1207 1208 /* We assume the CPU passed as argument is the primary CPU. */ 1209 info->primary_cpu = cpu; 1210 1211 /* Load the kernel. */ 1212 if (!info->kernel_filename || info->firmware_loaded) { 1213 arm_setup_firmware_boot(cpu, info); 1214 } else { 1215 arm_setup_direct_kernel_boot(cpu, info); 1216 } 1217 1218 /* 1219 * Disable the PSCI conduit if it is set up to target the same 1220 * or a lower EL than the one we're going to start the guest code in. 1221 * This logic needs to agree with the code in do_cpu_reset() which 1222 * decides whether we're going to boot the guest in the highest 1223 * supported exception level or in a lower one. 1224 */ 1225 1226 /* 1227 * If PSCI is enabled, then SMC calls all go to the PSCI handler and 1228 * are never emulated to trap into guest code. It therefore does not 1229 * make sense for the board to have a setup code fragment that runs 1230 * in Secure, because this will probably need to itself issue an SMC of some 1231 * kind as part of its operation. 1232 */ 1233 assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED || 1234 !info->secure_board_setup); 1235 1236 /* Boot into highest supported EL ... */ 1237 if (arm_feature(env, ARM_FEATURE_EL3)) { 1238 boot_el = 3; 1239 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 1240 boot_el = 2; 1241 } else { 1242 boot_el = 1; 1243 } 1244 /* ...except that if we're booting Linux we adjust the EL we boot into */ 1245 if (info->is_linux && !info->secure_boot) { 1246 boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; 1247 } 1248 1249 if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) || 1250 (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) { 1251 info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 1252 } 1253 1254 if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1255 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 1256 Object *cpuobj = OBJECT(cs); 1257 1258 object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit, 1259 &error_abort); 1260 /* Secondary CPUs start in PSCI powered-down state. */ 1261 if (ARM_CPU(cs) != info->primary_cpu) { 1262 object_property_set_bool(cpuobj, "start-powered-off", true, 1263 &error_abort); 1264 } 1265 } 1266 } 1267 1268 if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && 1269 info->is_linux && nb_cpus > 1) { 1270 /* 1271 * We're booting Linux but not using PSCI, so for SMP we need 1272 * to write a custom secondary CPU boot loader stub, and arrange 1273 * for the secondary CPU reset to make the accompanying initialization. 1274 */ 1275 if (!info->secondary_cpu_reset_hook) { 1276 info->secondary_cpu_reset_hook = default_reset_secondary; 1277 } 1278 if (!info->write_secondary_boot) { 1279 info->write_secondary_boot = default_write_secondary; 1280 } 1281 info->write_secondary_boot(cpu, info); 1282 } else { 1283 /* 1284 * No secondary boot stub; don't use the reset hook that would 1285 * have set the CPU up to call it 1286 */ 1287 info->write_secondary_boot = NULL; 1288 info->secondary_cpu_reset_hook = NULL; 1289 } 1290 1291 /* 1292 * arm_load_dtb() may add a PSCI node so it must be called after we have 1293 * decided whether to enable PSCI and set the psci-conduit CPU properties. 1294 */ 1295 if (!info->skip_dtb_autoload && have_dtb(info)) { 1296 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, 1297 as, ms, cpu) < 0) { 1298 exit(1); 1299 } 1300 } 1301 } 1302 1303 static const TypeInfo arm_linux_boot_if_info = { 1304 .name = TYPE_ARM_LINUX_BOOT_IF, 1305 .parent = TYPE_INTERFACE, 1306 .class_size = sizeof(ARMLinuxBootIfClass), 1307 }; 1308 1309 static void arm_linux_boot_register_types(void) 1310 { 1311 type_register_static(&arm_linux_boot_if_info); 1312 } 1313 1314 type_init(arm_linux_boot_register_types) 1315