1 /*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * This provides the native debug support via the Trigger Module, as defined
10 * in the RISC-V Debug Specification:
11 * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/log.h"
28 #include "qapi/error.h"
29 #include "cpu.h"
30 #include "trace.h"
31 #include "exec/exec-all.h"
32 #include "exec/helper-proto.h"
33 #include "sysemu/cpu-timers.h"
34
35 /*
36 * The following M-mode trigger CSRs are implemented:
37 *
38 * - tselect
39 * - tdata1
40 * - tdata2
41 * - tdata3
42 * - tinfo
43 *
44 * The following triggers are initialized by default:
45 *
46 * Index | Type | tdata mapping | Description
47 * ------+------+------------------------+------------
48 * 0 | 2 | tdata1, tdata2 | Address / Data Match
49 * 1 | 2 | tdata1, tdata2 | Address / Data Match
50 */
51
52 /* tdata availability of a trigger */
53 typedef bool tdata_avail[TDATA_NUM];
54
55 static tdata_avail tdata_mapping[TRIGGER_TYPE_NUM] = {
56 [TRIGGER_TYPE_NO_EXIST] = { false, false, false },
57 [TRIGGER_TYPE_AD_MATCH] = { true, true, true },
58 [TRIGGER_TYPE_INST_CNT] = { true, false, true },
59 [TRIGGER_TYPE_INT] = { true, true, true },
60 [TRIGGER_TYPE_EXCP] = { true, true, true },
61 [TRIGGER_TYPE_AD_MATCH6] = { true, true, true },
62 [TRIGGER_TYPE_EXT_SRC] = { true, false, false },
63 [TRIGGER_TYPE_UNAVAIL] = { true, true, true }
64 };
65
66 /* only breakpoint size 1/2/4/8 supported */
67 static int access_size[SIZE_NUM] = {
68 [SIZE_ANY] = 0,
69 [SIZE_1B] = 1,
70 [SIZE_2B] = 2,
71 [SIZE_4B] = 4,
72 [SIZE_6B] = -1,
73 [SIZE_8B] = 8,
74 [6 ... 15] = -1,
75 };
76
extract_trigger_type(CPURISCVState * env,target_ulong tdata1)77 static inline target_ulong extract_trigger_type(CPURISCVState *env,
78 target_ulong tdata1)
79 {
80 switch (riscv_cpu_mxl(env)) {
81 case MXL_RV32:
82 return extract32(tdata1, 28, 4);
83 case MXL_RV64:
84 case MXL_RV128:
85 return extract64(tdata1, 60, 4);
86 default:
87 g_assert_not_reached();
88 }
89 }
90
get_trigger_type(CPURISCVState * env,target_ulong trigger_index)91 static inline target_ulong get_trigger_type(CPURISCVState *env,
92 target_ulong trigger_index)
93 {
94 return extract_trigger_type(env, env->tdata1[trigger_index]);
95 }
96
get_trigger_action(CPURISCVState * env,target_ulong trigger_index)97 static trigger_action_t get_trigger_action(CPURISCVState *env,
98 target_ulong trigger_index)
99 {
100 target_ulong tdata1 = env->tdata1[trigger_index];
101 int trigger_type = get_trigger_type(env, trigger_index);
102 trigger_action_t action = DBG_ACTION_NONE;
103
104 switch (trigger_type) {
105 case TRIGGER_TYPE_AD_MATCH:
106 action = (tdata1 & TYPE2_ACTION) >> 12;
107 break;
108 case TRIGGER_TYPE_AD_MATCH6:
109 action = (tdata1 & TYPE6_ACTION) >> 12;
110 break;
111 case TRIGGER_TYPE_INST_CNT:
112 case TRIGGER_TYPE_INT:
113 case TRIGGER_TYPE_EXCP:
114 case TRIGGER_TYPE_EXT_SRC:
115 qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
116 trigger_type);
117 break;
118 case TRIGGER_TYPE_NO_EXIST:
119 case TRIGGER_TYPE_UNAVAIL:
120 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
121 trigger_type);
122 break;
123 default:
124 g_assert_not_reached();
125 }
126
127 return action;
128 }
129
build_tdata1(CPURISCVState * env,trigger_type_t type,bool dmode,target_ulong data)130 static inline target_ulong build_tdata1(CPURISCVState *env,
131 trigger_type_t type,
132 bool dmode, target_ulong data)
133 {
134 target_ulong tdata1;
135
136 switch (riscv_cpu_mxl(env)) {
137 case MXL_RV32:
138 tdata1 = RV32_TYPE(type) |
139 (dmode ? RV32_DMODE : 0) |
140 (data & RV32_DATA_MASK);
141 break;
142 case MXL_RV64:
143 case MXL_RV128:
144 tdata1 = RV64_TYPE(type) |
145 (dmode ? RV64_DMODE : 0) |
146 (data & RV64_DATA_MASK);
147 break;
148 default:
149 g_assert_not_reached();
150 }
151
152 return tdata1;
153 }
154
tdata_available(CPURISCVState * env,int tdata_index)155 bool tdata_available(CPURISCVState *env, int tdata_index)
156 {
157 int trigger_type = get_trigger_type(env, env->trigger_cur);
158
159 if (unlikely(tdata_index >= TDATA_NUM)) {
160 return false;
161 }
162
163 return tdata_mapping[trigger_type][tdata_index];
164 }
165
tselect_csr_read(CPURISCVState * env)166 target_ulong tselect_csr_read(CPURISCVState *env)
167 {
168 return env->trigger_cur;
169 }
170
tselect_csr_write(CPURISCVState * env,target_ulong val)171 void tselect_csr_write(CPURISCVState *env, target_ulong val)
172 {
173 if (val < RV_MAX_TRIGGERS) {
174 env->trigger_cur = val;
175 }
176 }
177
tdata1_validate(CPURISCVState * env,target_ulong val,trigger_type_t t)178 static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
179 trigger_type_t t)
180 {
181 uint32_t type, dmode;
182 target_ulong tdata1;
183
184 switch (riscv_cpu_mxl(env)) {
185 case MXL_RV32:
186 type = extract32(val, 28, 4);
187 dmode = extract32(val, 27, 1);
188 tdata1 = RV32_TYPE(t);
189 break;
190 case MXL_RV64:
191 case MXL_RV128:
192 type = extract64(val, 60, 4);
193 dmode = extract64(val, 59, 1);
194 tdata1 = RV64_TYPE(t);
195 break;
196 default:
197 g_assert_not_reached();
198 }
199
200 if (type != t) {
201 qemu_log_mask(LOG_GUEST_ERROR,
202 "ignoring type write to tdata1 register\n");
203 }
204
205 if (dmode != 0) {
206 qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n");
207 }
208
209 return tdata1;
210 }
211
warn_always_zero_bit(target_ulong val,target_ulong mask,const char * msg)212 static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
213 const char *msg)
214 {
215 if (val & mask) {
216 qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg);
217 }
218 }
219
textra_validate(CPURISCVState * env,target_ulong tdata3)220 static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3)
221 {
222 target_ulong mhvalue, mhselect;
223 target_ulong mhselect_new;
224 target_ulong textra;
225 const uint32_t mhselect_no_rvh[8] = { 0, 0, 0, 0, 4, 4, 4, 4 };
226
227 switch (riscv_cpu_mxl(env)) {
228 case MXL_RV32:
229 mhvalue = get_field(tdata3, TEXTRA32_MHVALUE);
230 mhselect = get_field(tdata3, TEXTRA32_MHSELECT);
231 /* Validate unimplemented (always zero) bits */
232 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SBYTEMASK,
233 "sbytemask");
234 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SVALUE,
235 "svalue");
236 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SSELECT,
237 "sselect");
238 break;
239 case MXL_RV64:
240 case MXL_RV128:
241 mhvalue = get_field(tdata3, TEXTRA64_MHVALUE);
242 mhselect = get_field(tdata3, TEXTRA64_MHSELECT);
243 /* Validate unimplemented (always zero) bits */
244 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SBYTEMASK,
245 "sbytemask");
246 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SVALUE,
247 "svalue");
248 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SSELECT,
249 "sselect");
250 break;
251 default:
252 g_assert_not_reached();
253 }
254
255 /* Validate mhselect. */
256 mhselect_new = mhselect_no_rvh[mhselect];
257 if (mhselect != mhselect_new) {
258 qemu_log_mask(LOG_UNIMP, "mhselect only supports 0 or 4 for now\n");
259 }
260
261 /* Write legal values into textra */
262 textra = 0;
263 switch (riscv_cpu_mxl(env)) {
264 case MXL_RV32:
265 textra = set_field(textra, TEXTRA32_MHVALUE, mhvalue);
266 textra = set_field(textra, TEXTRA32_MHSELECT, mhselect_new);
267 break;
268 case MXL_RV64:
269 case MXL_RV128:
270 textra = set_field(textra, TEXTRA64_MHVALUE, mhvalue);
271 textra = set_field(textra, TEXTRA64_MHSELECT, mhselect_new);
272 break;
273 default:
274 g_assert_not_reached();
275 }
276
277 return textra;
278 }
279
do_trigger_action(CPURISCVState * env,target_ulong trigger_index)280 static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
281 {
282 trigger_action_t action = get_trigger_action(env, trigger_index);
283
284 switch (action) {
285 case DBG_ACTION_NONE:
286 break;
287 case DBG_ACTION_BP:
288 riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
289 break;
290 case DBG_ACTION_DBG_MODE:
291 case DBG_ACTION_TRACE0:
292 case DBG_ACTION_TRACE1:
293 case DBG_ACTION_TRACE2:
294 case DBG_ACTION_TRACE3:
295 case DBG_ACTION_EXT_DBG0:
296 case DBG_ACTION_EXT_DBG1:
297 qemu_log_mask(LOG_UNIMP, "action: %d is not supported\n", action);
298 break;
299 default:
300 g_assert_not_reached();
301 }
302 }
303
304 /*
305 * Check the privilege level of specific trigger matches CPU's current privilege
306 * level.
307 */
trigger_priv_match(CPURISCVState * env,trigger_type_t type,int trigger_index)308 static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
309 int trigger_index)
310 {
311 target_ulong ctrl = env->tdata1[trigger_index];
312
313 switch (type) {
314 case TRIGGER_TYPE_AD_MATCH:
315 /* type 2 trigger cannot be fired in VU/VS mode */
316 if (env->virt_enabled) {
317 return false;
318 }
319 /* check U/S/M bit against current privilege level */
320 if ((ctrl >> 3) & BIT(env->priv)) {
321 return true;
322 }
323 break;
324 case TRIGGER_TYPE_AD_MATCH6:
325 if (env->virt_enabled) {
326 /* check VU/VS bit against current privilege level */
327 if ((ctrl >> 23) & BIT(env->priv)) {
328 return true;
329 }
330 } else {
331 /* check U/S/M bit against current privilege level */
332 if ((ctrl >> 3) & BIT(env->priv)) {
333 return true;
334 }
335 }
336 break;
337 case TRIGGER_TYPE_INST_CNT:
338 if (env->virt_enabled) {
339 /* check VU/VS bit against current privilege level */
340 if ((ctrl >> 25) & BIT(env->priv)) {
341 return true;
342 }
343 } else {
344 /* check U/S/M bit against current privilege level */
345 if ((ctrl >> 6) & BIT(env->priv)) {
346 return true;
347 }
348 }
349 break;
350 case TRIGGER_TYPE_INT:
351 case TRIGGER_TYPE_EXCP:
352 case TRIGGER_TYPE_EXT_SRC:
353 qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", type);
354 break;
355 case TRIGGER_TYPE_NO_EXIST:
356 case TRIGGER_TYPE_UNAVAIL:
357 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exist\n",
358 type);
359 break;
360 default:
361 g_assert_not_reached();
362 }
363
364 return false;
365 }
366
trigger_textra_match(CPURISCVState * env,trigger_type_t type,int trigger_index)367 static bool trigger_textra_match(CPURISCVState *env, trigger_type_t type,
368 int trigger_index)
369 {
370 target_ulong textra = env->tdata3[trigger_index];
371 target_ulong mhvalue, mhselect;
372
373 if (type < TRIGGER_TYPE_AD_MATCH || type > TRIGGER_TYPE_AD_MATCH6) {
374 /* textra checking is only applicable when type is 2, 3, 4, 5, or 6 */
375 return true;
376 }
377
378 switch (riscv_cpu_mxl(env)) {
379 case MXL_RV32:
380 mhvalue = get_field(textra, TEXTRA32_MHVALUE);
381 mhselect = get_field(textra, TEXTRA32_MHSELECT);
382 break;
383 case MXL_RV64:
384 case MXL_RV128:
385 mhvalue = get_field(textra, TEXTRA64_MHVALUE);
386 mhselect = get_field(textra, TEXTRA64_MHSELECT);
387 break;
388 default:
389 g_assert_not_reached();
390 }
391
392 /* Check mhvalue and mhselect. */
393 switch (mhselect) {
394 case MHSELECT_IGNORE:
395 break;
396 case MHSELECT_MCONTEXT:
397 /* Match if the low bits of mcontext/hcontext equal mhvalue. */
398 if (mhvalue != env->mcontext) {
399 return false;
400 }
401 break;
402 default:
403 break;
404 }
405
406 return true;
407 }
408
409 /* Common matching conditions for all types of the triggers. */
trigger_common_match(CPURISCVState * env,trigger_type_t type,int trigger_index)410 static bool trigger_common_match(CPURISCVState *env, trigger_type_t type,
411 int trigger_index)
412 {
413 return trigger_priv_match(env, type, trigger_index) &&
414 trigger_textra_match(env, type, trigger_index);
415 }
416
417 /* type 2 trigger */
418
type2_breakpoint_size(CPURISCVState * env,target_ulong ctrl)419 static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
420 {
421 uint32_t sizelo, sizehi = 0;
422
423 if (riscv_cpu_mxl(env) == MXL_RV64) {
424 sizehi = extract32(ctrl, 21, 2);
425 }
426 sizelo = extract32(ctrl, 16, 2);
427 return (sizehi << 2) | sizelo;
428 }
429
type2_breakpoint_enabled(target_ulong ctrl)430 static inline bool type2_breakpoint_enabled(target_ulong ctrl)
431 {
432 bool mode = !!(ctrl & (TYPE2_U | TYPE2_S | TYPE2_M));
433 bool rwx = !!(ctrl & (TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
434
435 return mode && rwx;
436 }
437
type2_mcontrol_validate(CPURISCVState * env,target_ulong ctrl)438 static target_ulong type2_mcontrol_validate(CPURISCVState *env,
439 target_ulong ctrl)
440 {
441 target_ulong val;
442 uint32_t size;
443
444 /* validate the generic part first */
445 val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH);
446
447 /* validate unimplemented (always zero) bits */
448 warn_always_zero_bit(ctrl, TYPE2_MATCH, "match");
449 warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain");
450 warn_always_zero_bit(ctrl, TYPE2_ACTION, "action");
451 warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing");
452 warn_always_zero_bit(ctrl, TYPE2_SELECT, "select");
453 warn_always_zero_bit(ctrl, TYPE2_HIT, "hit");
454
455 /* validate size encoding */
456 size = type2_breakpoint_size(env, ctrl);
457 if (access_size[size] == -1) {
458 qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
459 "SIZE_ANY\n", size);
460 } else {
461 val |= (ctrl & TYPE2_SIZELO);
462 if (riscv_cpu_mxl(env) == MXL_RV64) {
463 val |= (ctrl & TYPE2_SIZEHI);
464 }
465 }
466
467 /* keep the mode and attribute bits */
468 val |= (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M |
469 TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
470
471 return val;
472 }
473
type2_breakpoint_insert(CPURISCVState * env,target_ulong index)474 static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
475 {
476 target_ulong ctrl = env->tdata1[index];
477 target_ulong addr = env->tdata2[index];
478 bool enabled = type2_breakpoint_enabled(ctrl);
479 CPUState *cs = env_cpu(env);
480 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
481 uint32_t size;
482
483 if (!enabled) {
484 return;
485 }
486
487 if (ctrl & TYPE2_EXEC) {
488 cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
489 }
490
491 if (ctrl & TYPE2_LOAD) {
492 flags |= BP_MEM_READ;
493 }
494 if (ctrl & TYPE2_STORE) {
495 flags |= BP_MEM_WRITE;
496 }
497
498 if (flags & BP_MEM_ACCESS) {
499 size = type2_breakpoint_size(env, ctrl);
500 if (size != 0) {
501 cpu_watchpoint_insert(cs, addr, size, flags,
502 &env->cpu_watchpoint[index]);
503 } else {
504 cpu_watchpoint_insert(cs, addr, 8, flags,
505 &env->cpu_watchpoint[index]);
506 }
507 }
508 }
509
type2_breakpoint_remove(CPURISCVState * env,target_ulong index)510 static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index)
511 {
512 CPUState *cs = env_cpu(env);
513
514 if (env->cpu_breakpoint[index]) {
515 cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
516 env->cpu_breakpoint[index] = NULL;
517 }
518
519 if (env->cpu_watchpoint[index]) {
520 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
521 env->cpu_watchpoint[index] = NULL;
522 }
523 }
524
type2_reg_write(CPURISCVState * env,target_ulong index,int tdata_index,target_ulong val)525 static void type2_reg_write(CPURISCVState *env, target_ulong index,
526 int tdata_index, target_ulong val)
527 {
528 target_ulong new_val;
529
530 switch (tdata_index) {
531 case TDATA1:
532 new_val = type2_mcontrol_validate(env, val);
533 if (new_val != env->tdata1[index]) {
534 env->tdata1[index] = new_val;
535 type2_breakpoint_remove(env, index);
536 type2_breakpoint_insert(env, index);
537 }
538 break;
539 case TDATA2:
540 if (val != env->tdata2[index]) {
541 env->tdata2[index] = val;
542 type2_breakpoint_remove(env, index);
543 type2_breakpoint_insert(env, index);
544 }
545 break;
546 case TDATA3:
547 env->tdata3[index] = textra_validate(env, val);
548 break;
549 default:
550 g_assert_not_reached();
551 }
552
553 return;
554 }
555
556 /* type 6 trigger */
557
type6_breakpoint_enabled(target_ulong ctrl)558 static inline bool type6_breakpoint_enabled(target_ulong ctrl)
559 {
560 bool mode = !!(ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M));
561 bool rwx = !!(ctrl & (TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
562
563 return mode && rwx;
564 }
565
type6_mcontrol6_validate(CPURISCVState * env,target_ulong ctrl)566 static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
567 target_ulong ctrl)
568 {
569 target_ulong val;
570 uint32_t size;
571
572 /* validate the generic part first */
573 val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6);
574
575 /* validate unimplemented (always zero) bits */
576 warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
577 warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain");
578 warn_always_zero_bit(ctrl, TYPE6_ACTION, "action");
579 warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
580 warn_always_zero_bit(ctrl, TYPE6_SELECT, "select");
581 warn_always_zero_bit(ctrl, TYPE6_HIT, "hit");
582
583 /* validate size encoding */
584 size = extract32(ctrl, 16, 4);
585 if (access_size[size] == -1) {
586 qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
587 "SIZE_ANY\n", size);
588 } else {
589 val |= (ctrl & TYPE6_SIZE);
590 }
591
592 /* keep the mode and attribute bits */
593 val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M |
594 TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
595
596 return val;
597 }
598
type6_breakpoint_insert(CPURISCVState * env,target_ulong index)599 static void type6_breakpoint_insert(CPURISCVState *env, target_ulong index)
600 {
601 target_ulong ctrl = env->tdata1[index];
602 target_ulong addr = env->tdata2[index];
603 bool enabled = type6_breakpoint_enabled(ctrl);
604 CPUState *cs = env_cpu(env);
605 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
606 uint32_t size;
607
608 if (!enabled) {
609 return;
610 }
611
612 if (ctrl & TYPE6_EXEC) {
613 cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
614 }
615
616 if (ctrl & TYPE6_LOAD) {
617 flags |= BP_MEM_READ;
618 }
619
620 if (ctrl & TYPE6_STORE) {
621 flags |= BP_MEM_WRITE;
622 }
623
624 if (flags & BP_MEM_ACCESS) {
625 size = extract32(ctrl, 16, 4);
626 if (size != 0) {
627 cpu_watchpoint_insert(cs, addr, size, flags,
628 &env->cpu_watchpoint[index]);
629 } else {
630 cpu_watchpoint_insert(cs, addr, 8, flags,
631 &env->cpu_watchpoint[index]);
632 }
633 }
634 }
635
type6_breakpoint_remove(CPURISCVState * env,target_ulong index)636 static void type6_breakpoint_remove(CPURISCVState *env, target_ulong index)
637 {
638 type2_breakpoint_remove(env, index);
639 }
640
type6_reg_write(CPURISCVState * env,target_ulong index,int tdata_index,target_ulong val)641 static void type6_reg_write(CPURISCVState *env, target_ulong index,
642 int tdata_index, target_ulong val)
643 {
644 target_ulong new_val;
645
646 switch (tdata_index) {
647 case TDATA1:
648 new_val = type6_mcontrol6_validate(env, val);
649 if (new_val != env->tdata1[index]) {
650 env->tdata1[index] = new_val;
651 type6_breakpoint_remove(env, index);
652 type6_breakpoint_insert(env, index);
653 }
654 break;
655 case TDATA2:
656 if (val != env->tdata2[index]) {
657 env->tdata2[index] = val;
658 type6_breakpoint_remove(env, index);
659 type6_breakpoint_insert(env, index);
660 }
661 break;
662 case TDATA3:
663 env->tdata3[index] = textra_validate(env, val);
664 break;
665 default:
666 g_assert_not_reached();
667 }
668
669 return;
670 }
671
672 /* icount trigger type */
673 static inline int
itrigger_get_count(CPURISCVState * env,int index)674 itrigger_get_count(CPURISCVState *env, int index)
675 {
676 return get_field(env->tdata1[index], ITRIGGER_COUNT);
677 }
678
679 static inline void
itrigger_set_count(CPURISCVState * env,int index,int value)680 itrigger_set_count(CPURISCVState *env, int index, int value)
681 {
682 env->tdata1[index] = set_field(env->tdata1[index],
683 ITRIGGER_COUNT, value);
684 }
685
check_itrigger_priv(CPURISCVState * env,int index)686 static bool check_itrigger_priv(CPURISCVState *env, int index)
687 {
688 target_ulong tdata1 = env->tdata1[index];
689 if (env->virt_enabled) {
690 /* check VU/VS bit against current privilege level */
691 return (get_field(tdata1, ITRIGGER_VS) == env->priv) ||
692 (get_field(tdata1, ITRIGGER_VU) == env->priv);
693 } else {
694 /* check U/S/M bit against current privilege level */
695 return (get_field(tdata1, ITRIGGER_M) == env->priv) ||
696 (get_field(tdata1, ITRIGGER_S) == env->priv) ||
697 (get_field(tdata1, ITRIGGER_U) == env->priv);
698 }
699 }
700
riscv_itrigger_enabled(CPURISCVState * env)701 bool riscv_itrigger_enabled(CPURISCVState *env)
702 {
703 int count;
704 for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
705 if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
706 continue;
707 }
708 if (check_itrigger_priv(env, i)) {
709 continue;
710 }
711 count = itrigger_get_count(env, i);
712 if (!count) {
713 continue;
714 }
715 return true;
716 }
717
718 return false;
719 }
720
helper_itrigger_match(CPURISCVState * env)721 void helper_itrigger_match(CPURISCVState *env)
722 {
723 int count;
724 for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
725 if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
726 continue;
727 }
728 if (!trigger_common_match(env, TRIGGER_TYPE_INST_CNT, i)) {
729 continue;
730 }
731 count = itrigger_get_count(env, i);
732 if (!count) {
733 continue;
734 }
735 itrigger_set_count(env, i, count--);
736 if (!count) {
737 env->itrigger_enabled = riscv_itrigger_enabled(env);
738 do_trigger_action(env, i);
739 }
740 }
741 }
742
riscv_itrigger_update_count(CPURISCVState * env)743 static void riscv_itrigger_update_count(CPURISCVState *env)
744 {
745 int count, executed;
746 /*
747 * Record last icount, so that we can evaluate the executed instructions
748 * since last privilege mode change or timer expire.
749 */
750 int64_t last_icount = env->last_icount, current_icount;
751 current_icount = env->last_icount = icount_get_raw();
752
753 for (int i = 0; i < RV_MAX_TRIGGERS; i++) {
754 if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
755 continue;
756 }
757 count = itrigger_get_count(env, i);
758 if (!count) {
759 continue;
760 }
761 /*
762 * Only when privilege is changed or itrigger timer expires,
763 * the count field in itrigger tdata1 register is updated.
764 * And the count field in itrigger only contains remaining value.
765 */
766 if (check_itrigger_priv(env, i)) {
767 /*
768 * If itrigger enabled in this privilege mode, the number of
769 * executed instructions since last privilege change
770 * should be reduced from current itrigger count.
771 */
772 executed = current_icount - last_icount;
773 itrigger_set_count(env, i, count - executed);
774 if (count == executed) {
775 do_trigger_action(env, i);
776 }
777 } else {
778 /*
779 * If itrigger is not enabled in this privilege mode,
780 * the number of executed instructions will be discard and
781 * the count field in itrigger will not change.
782 */
783 timer_mod(env->itrigger_timer[i],
784 current_icount + count);
785 }
786 }
787 }
788
riscv_itrigger_timer_cb(void * opaque)789 static void riscv_itrigger_timer_cb(void *opaque)
790 {
791 riscv_itrigger_update_count((CPURISCVState *)opaque);
792 }
793
riscv_itrigger_update_priv(CPURISCVState * env)794 void riscv_itrigger_update_priv(CPURISCVState *env)
795 {
796 riscv_itrigger_update_count(env);
797 }
798
itrigger_validate(CPURISCVState * env,target_ulong ctrl)799 static target_ulong itrigger_validate(CPURISCVState *env,
800 target_ulong ctrl)
801 {
802 target_ulong val;
803
804 /* validate the generic part first */
805 val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
806
807 /* validate unimplemented (always zero) bits */
808 warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
809 warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit");
810 warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending");
811
812 /* keep the mode and attribute bits */
813 val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S |
814 ITRIGGER_M | ITRIGGER_COUNT);
815
816 return val;
817 }
818
itrigger_reg_write(CPURISCVState * env,target_ulong index,int tdata_index,target_ulong val)819 static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
820 int tdata_index, target_ulong val)
821 {
822 target_ulong new_val;
823
824 switch (tdata_index) {
825 case TDATA1:
826 /* set timer for icount */
827 new_val = itrigger_validate(env, val);
828 if (new_val != env->tdata1[index]) {
829 env->tdata1[index] = new_val;
830 if (icount_enabled()) {
831 env->last_icount = icount_get_raw();
832 /* set the count to timer */
833 timer_mod(env->itrigger_timer[index],
834 env->last_icount + itrigger_get_count(env, index));
835 } else {
836 env->itrigger_enabled = riscv_itrigger_enabled(env);
837 }
838 }
839 break;
840 case TDATA2:
841 qemu_log_mask(LOG_UNIMP,
842 "tdata2 is not supported for icount trigger\n");
843 break;
844 case TDATA3:
845 env->tdata3[index] = textra_validate(env, val);
846 break;
847 default:
848 g_assert_not_reached();
849 }
850
851 return;
852 }
853
itrigger_get_adjust_count(CPURISCVState * env)854 static int itrigger_get_adjust_count(CPURISCVState *env)
855 {
856 int count = itrigger_get_count(env, env->trigger_cur), executed;
857 if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) {
858 executed = icount_get_raw() - env->last_icount;
859 count += executed;
860 }
861 return count;
862 }
863
tdata_csr_read(CPURISCVState * env,int tdata_index)864 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
865 {
866 int trigger_type;
867 switch (tdata_index) {
868 case TDATA1:
869 trigger_type = extract_trigger_type(env,
870 env->tdata1[env->trigger_cur]);
871 if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
872 return deposit64(env->tdata1[env->trigger_cur], 10, 14,
873 itrigger_get_adjust_count(env));
874 }
875 return env->tdata1[env->trigger_cur];
876 case TDATA2:
877 return env->tdata2[env->trigger_cur];
878 case TDATA3:
879 return env->tdata3[env->trigger_cur];
880 default:
881 g_assert_not_reached();
882 }
883 }
884
tdata_csr_write(CPURISCVState * env,int tdata_index,target_ulong val)885 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
886 {
887 int trigger_type;
888
889 if (tdata_index == TDATA1) {
890 trigger_type = extract_trigger_type(env, val);
891 } else {
892 trigger_type = get_trigger_type(env, env->trigger_cur);
893 }
894
895 switch (trigger_type) {
896 case TRIGGER_TYPE_AD_MATCH:
897 type2_reg_write(env, env->trigger_cur, tdata_index, val);
898 break;
899 case TRIGGER_TYPE_AD_MATCH6:
900 type6_reg_write(env, env->trigger_cur, tdata_index, val);
901 break;
902 case TRIGGER_TYPE_INST_CNT:
903 itrigger_reg_write(env, env->trigger_cur, tdata_index, val);
904 break;
905 case TRIGGER_TYPE_INT:
906 case TRIGGER_TYPE_EXCP:
907 case TRIGGER_TYPE_EXT_SRC:
908 qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
909 trigger_type);
910 break;
911 case TRIGGER_TYPE_NO_EXIST:
912 case TRIGGER_TYPE_UNAVAIL:
913 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
914 trigger_type);
915 break;
916 default:
917 g_assert_not_reached();
918 }
919 }
920
tinfo_csr_read(CPURISCVState * env)921 target_ulong tinfo_csr_read(CPURISCVState *env)
922 {
923 /* assume all triggers support the same types of triggers */
924 return BIT(TRIGGER_TYPE_AD_MATCH) |
925 BIT(TRIGGER_TYPE_AD_MATCH6);
926 }
927
riscv_cpu_debug_excp_handler(CPUState * cs)928 void riscv_cpu_debug_excp_handler(CPUState *cs)
929 {
930 RISCVCPU *cpu = RISCV_CPU(cs);
931 CPURISCVState *env = &cpu->env;
932
933 if (cs->watchpoint_hit) {
934 if (cs->watchpoint_hit->flags & BP_CPU) {
935 do_trigger_action(env, DBG_ACTION_BP);
936 }
937 } else {
938 if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
939 do_trigger_action(env, DBG_ACTION_BP);
940 }
941 }
942 }
943
riscv_cpu_debug_check_breakpoint(CPUState * cs)944 bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
945 {
946 RISCVCPU *cpu = RISCV_CPU(cs);
947 CPURISCVState *env = &cpu->env;
948 CPUBreakpoint *bp;
949 target_ulong ctrl;
950 target_ulong pc;
951 int trigger_type;
952 int i;
953
954 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
955 for (i = 0; i < RV_MAX_TRIGGERS; i++) {
956 trigger_type = get_trigger_type(env, i);
957
958 if (!trigger_common_match(env, trigger_type, i)) {
959 continue;
960 }
961
962 switch (trigger_type) {
963 case TRIGGER_TYPE_AD_MATCH:
964 ctrl = env->tdata1[i];
965 pc = env->tdata2[i];
966
967 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
968 env->badaddr = pc;
969 return true;
970 }
971 break;
972 case TRIGGER_TYPE_AD_MATCH6:
973 ctrl = env->tdata1[i];
974 pc = env->tdata2[i];
975
976 if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
977 env->badaddr = pc;
978 return true;
979 }
980 break;
981 default:
982 /* other trigger types are not supported or irrelevant */
983 break;
984 }
985 }
986 }
987
988 return false;
989 }
990
riscv_cpu_debug_check_watchpoint(CPUState * cs,CPUWatchpoint * wp)991 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
992 {
993 RISCVCPU *cpu = RISCV_CPU(cs);
994 CPURISCVState *env = &cpu->env;
995 target_ulong ctrl;
996 target_ulong addr;
997 int trigger_type;
998 int flags;
999 int i;
1000
1001 for (i = 0; i < RV_MAX_TRIGGERS; i++) {
1002 trigger_type = get_trigger_type(env, i);
1003
1004 if (!trigger_common_match(env, trigger_type, i)) {
1005 continue;
1006 }
1007
1008 switch (trigger_type) {
1009 case TRIGGER_TYPE_AD_MATCH:
1010 ctrl = env->tdata1[i];
1011 addr = env->tdata2[i];
1012 flags = 0;
1013
1014 if (ctrl & TYPE2_LOAD) {
1015 flags |= BP_MEM_READ;
1016 }
1017 if (ctrl & TYPE2_STORE) {
1018 flags |= BP_MEM_WRITE;
1019 }
1020
1021 if ((wp->flags & flags) && (wp->vaddr == addr)) {
1022 return true;
1023 }
1024 break;
1025 case TRIGGER_TYPE_AD_MATCH6:
1026 ctrl = env->tdata1[i];
1027 addr = env->tdata2[i];
1028 flags = 0;
1029
1030 if (ctrl & TYPE6_LOAD) {
1031 flags |= BP_MEM_READ;
1032 }
1033 if (ctrl & TYPE6_STORE) {
1034 flags |= BP_MEM_WRITE;
1035 }
1036
1037 if ((wp->flags & flags) && (wp->vaddr == addr)) {
1038 return true;
1039 }
1040 break;
1041 default:
1042 /* other trigger types are not supported */
1043 break;
1044 }
1045 }
1046
1047 return false;
1048 }
1049
riscv_trigger_realize(CPURISCVState * env)1050 void riscv_trigger_realize(CPURISCVState *env)
1051 {
1052 int i;
1053
1054 for (i = 0; i < RV_MAX_TRIGGERS; i++) {
1055 env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1056 riscv_itrigger_timer_cb, env);
1057 }
1058 }
1059
riscv_trigger_reset_hold(CPURISCVState * env)1060 void riscv_trigger_reset_hold(CPURISCVState *env)
1061 {
1062 target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
1063 int i;
1064
1065 /* init to type 2 triggers */
1066 for (i = 0; i < RV_MAX_TRIGGERS; i++) {
1067 /*
1068 * type = TRIGGER_TYPE_AD_MATCH
1069 * dmode = 0 (both debug and M-mode can write tdata)
1070 * maskmax = 0 (unimplemented, always 0)
1071 * sizehi = 0 (match against any size, RV64 only)
1072 * hit = 0 (unimplemented, always 0)
1073 * select = 0 (always 0, perform match on address)
1074 * timing = 0 (always 0, trigger before instruction)
1075 * sizelo = 0 (match against any size)
1076 * action = 0 (always 0, raise a breakpoint exception)
1077 * chain = 0 (unimplemented, always 0)
1078 * match = 0 (always 0, when any compare value equals tdata2)
1079 */
1080 env->tdata1[i] = tdata1;
1081 env->tdata2[i] = 0;
1082 env->tdata3[i] = 0;
1083 env->cpu_breakpoint[i] = NULL;
1084 env->cpu_watchpoint[i] = NULL;
1085 timer_del(env->itrigger_timer[i]);
1086 }
1087
1088 env->mcontext = 0;
1089 }
1090