1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
7 * Author: Markus Niebel <markus.niebel@tq-group.com>
8 */
9
10 #include <asm/arch/clock.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/sys_proto.h>
15 #include <linux/errno.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/spi.h>
20 #include <common.h>
21 #include <fsl_esdhc.h>
22 #include <linux/libfdt.h>
23 #include <i2c.h>
24 #include <mmc.h>
25 #include <power/pfuze100_pmic.h>
26 #include <power/pmic.h>
27 #include <spi_flash.h>
28
29 #include "tqma6_bb.h"
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
41
42 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
44
45 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
46 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
47
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
dram_init(void)52 int dram_init(void)
53 {
54 gd->ram_size = imx_ddr_size();
55
56 return 0;
57 }
58
59 static const uint16_t tqma6_emmc_dsr = 0x0100;
60
61 /* eMMC on USDHCI3 always present */
62 static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
63 NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
64 NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
65 NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
66 NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
67 NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
68 NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
69 NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
70 NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
71 NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
72 NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
73 /* eMMC reset */
74 NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
75 };
76
77 /*
78 * According to board_mmc_init() the following map is done:
79 * (U-Boot device node) (Physical Port)
80 * mmc0 eMMC (SD3) on TQMa6
81 * mmc1 .. n optional slots used on baseboard
82 */
83 struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
84 .esdhc_base = USDHC3_BASE_ADDR,
85 .max_bus_width = 8,
86 };
87
board_mmc_getcd(struct mmc * mmc)88 int board_mmc_getcd(struct mmc *mmc)
89 {
90 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
91 int ret = 0;
92
93 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
94 /* eMMC/uSDHC3 is always present */
95 ret = 1;
96 else
97 ret = tqma6_bb_board_mmc_getcd(mmc);
98
99 return ret;
100 }
101
board_mmc_getwp(struct mmc * mmc)102 int board_mmc_getwp(struct mmc *mmc)
103 {
104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
105 int ret = 0;
106
107 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
108 /* eMMC/uSDHC3 is always present */
109 ret = 0;
110 else
111 ret = tqma6_bb_board_mmc_getwp(mmc);
112
113 return ret;
114 }
115
board_mmc_init(bd_t * bis)116 int board_mmc_init(bd_t *bis)
117 {
118 imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
119 ARRAY_SIZE(tqma6_usdhc3_pads));
120 tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
121 if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
122 puts("Warning: failed to initialize eMMC dev\n");
123 } else {
124 struct mmc *mmc = find_mmc_device(0);
125 if (mmc)
126 mmc_set_dsr(mmc, tqma6_emmc_dsr);
127 }
128
129 tqma6_bb_board_mmc_init(bis);
130
131 return 0;
132 }
133
134 static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
135 /* SS1 */
136 NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
137 NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
138 NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
139 NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
140 };
141
142 #define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
143
144 static unsigned const tqma6_ecspi1_cs[] = {
145 TQMA6_SF_CS_GPIO,
146 };
147
tqma6_iomuxc_spi(void)148 __weak void tqma6_iomuxc_spi(void)
149 {
150 unsigned i;
151
152 for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
153 gpio_direction_output(tqma6_ecspi1_cs[i], 1);
154 imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
155 ARRAY_SIZE(tqma6_ecspi1_pads));
156 }
157
158 #if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
board_spi_cs_gpio(unsigned bus,unsigned cs)159 int board_spi_cs_gpio(unsigned bus, unsigned cs)
160 {
161 return ((bus == CONFIG_SF_DEFAULT_BUS) &&
162 (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
163 }
164 #endif
165
166 static struct i2c_pads_info tqma6_i2c3_pads = {
167 /* I2C3: on board LM75, M24C64, */
168 .scl = {
169 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
170 I2C_PAD_CTRL),
171 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
172 I2C_PAD_CTRL),
173 .gp = IMX_GPIO_NR(1, 5)
174 },
175 .sda = {
176 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
177 I2C_PAD_CTRL),
178 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
179 I2C_PAD_CTRL),
180 .gp = IMX_GPIO_NR(1, 6)
181 }
182 };
183
tqma6_setup_i2c(void)184 static void tqma6_setup_i2c(void)
185 {
186 int ret;
187 /*
188 * use logical index for bus, e.g. I2C1 -> 0
189 * warn on error
190 */
191 ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
192 if (ret)
193 printf("setup I2C3 failed: %d\n", ret);
194 }
195
board_early_init_f(void)196 int board_early_init_f(void)
197 {
198 return tqma6_bb_board_early_init_f();
199 }
200
board_init(void)201 int board_init(void)
202 {
203 /* address of boot parameters */
204 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
205
206 tqma6_iomuxc_spi();
207 tqma6_setup_i2c();
208
209 tqma6_bb_board_init();
210
211 return 0;
212 }
213
tqma6_get_boardname(void)214 static const char *tqma6_get_boardname(void)
215 {
216 u32 cpurev = get_cpu_rev();
217
218 switch ((cpurev & 0xFF000) >> 12) {
219 case MXC_CPU_MX6SOLO:
220 return "TQMa6S";
221 break;
222 case MXC_CPU_MX6DL:
223 return "TQMa6DL";
224 break;
225 case MXC_CPU_MX6D:
226 return "TQMa6D";
227 break;
228 case MXC_CPU_MX6Q:
229 return "TQMa6Q";
230 break;
231 default:
232 return "??";
233 };
234 }
235
236 /* setup board specific PMIC */
power_init_board(void)237 int power_init_board(void)
238 {
239 struct pmic *p;
240 u32 reg, rev;
241
242 power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
243 p = pmic_get("PFUZE100");
244 if (p && !pmic_probe(p)) {
245 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
246 pmic_reg_read(p, PFUZE100_REVID, &rev);
247 printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
248 }
249
250 return 0;
251 }
252
board_late_init(void)253 int board_late_init(void)
254 {
255 env_set("board_name", tqma6_get_boardname());
256
257 tqma6_bb_board_late_init();
258
259 return 0;
260 }
261
checkboard(void)262 int checkboard(void)
263 {
264 printf("Board: %s on a %s\n", tqma6_get_boardname(),
265 tqma6_bb_get_boardname());
266 return 0;
267 }
268
269 /*
270 * Device Tree Support
271 */
272 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
273 #define MODELSTRLEN 32u
ft_board_setup(void * blob,bd_t * bd)274 int ft_board_setup(void *blob, bd_t *bd)
275 {
276 char modelstr[MODELSTRLEN];
277
278 snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
279 tqma6_bb_get_boardname());
280 do_fixup_by_path_string(blob, "/", "model", modelstr);
281 fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
282 /* bring in eMMC dsr settings */
283 do_fixup_by_path_u32(blob,
284 "/soc/aips-bus@02100000/usdhc@02198000",
285 "dsr", tqma6_emmc_dsr, 2);
286 tqma6_bb_ft_board_setup(blob, bd);
287
288 return 0;
289 }
290 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
291