1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * This file contains driver for the Cadence Triple Timer Counter Rev 06
4  *
5  *  Copyright (C) 2011-2013 Xilinx
6  *
7  * based on arch/mips/kernel/time.c timer driver
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
12 #include <linux/clockchips.h>
13 #include <linux/clocksource.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/sched_clock.h>
19 #include <linux/module.h>
20 #include <linux/of_platform.h>
21 
22 /*
23  * This driver configures the 2 16/32-bit count-up timers as follows:
24  *
25  * T1: Timer 1, clocksource for generic timekeeping
26  * T2: Timer 2, clockevent source for hrtimers
27  * T3: Timer 3, <unused>
28  *
29  * The input frequency to the timer module for emulation is 2.5MHz which is
30  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
31  * the timers are clocked at 78.125KHz (12.8 us resolution).
32 
33  * The input frequency to the timer module in silicon is configurable and
34  * obtained from device tree. The pre-scaler of 32 is used.
35  */
36 
37 /*
38  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
39  * and use same offsets for Timer 2
40  */
41 #define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
42 #define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
43 #define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
44 #define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
45 #define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
46 #define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */
47 
48 #define TTC_CNT_CNTRL_DISABLE_MASK	0x1
49 
50 #define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */
51 #define TTC_CLK_CNTRL_PSV_MASK		0x1e
52 #define TTC_CLK_CNTRL_PSV_SHIFT		1
53 
54 /*
55  * Setup the timers to use pre-scaling, using a fixed value for now that will
56  * work across most input frequency, but it may need to be more dynamic
57  */
58 #define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
59 #define PRESCALE		2048	/* The exponent must match this */
60 #define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
61 #define CLK_CNTRL_PRESCALE_EN	1
62 #define CNT_CNTRL_RESET		(1 << 4)
63 
64 #define MAX_F_ERR 50
65 
66 /**
67  * struct ttc_timer - This definition defines local timer structure
68  *
69  * @base_addr:	Base address of timer
70  * @freq:	Timer input clock frequency
71  * @clk:	Associated clock source
72  * @clk_rate_change_nb	Notifier block for clock rate changes
73  */
74 struct ttc_timer {
75 	void __iomem *base_addr;
76 	unsigned long freq;
77 	struct clk *clk;
78 	struct notifier_block clk_rate_change_nb;
79 };
80 
81 #define to_ttc_timer(x) \
82 		container_of(x, struct ttc_timer, clk_rate_change_nb)
83 
84 struct ttc_timer_clocksource {
85 	u32			scale_clk_ctrl_reg_old;
86 	u32			scale_clk_ctrl_reg_new;
87 	struct ttc_timer	ttc;
88 	struct clocksource	cs;
89 };
90 
91 #define to_ttc_timer_clksrc(x) \
92 		container_of(x, struct ttc_timer_clocksource, cs)
93 
94 struct ttc_timer_clockevent {
95 	struct ttc_timer		ttc;
96 	struct clock_event_device	ce;
97 };
98 
99 #define to_ttc_timer_clkevent(x) \
100 		container_of(x, struct ttc_timer_clockevent, ce)
101 
102 static void __iomem *ttc_sched_clock_val_reg;
103 
104 /**
105  * ttc_set_interval - Set the timer interval value
106  *
107  * @timer:	Pointer to the timer instance
108  * @cycles:	Timer interval ticks
109  **/
ttc_set_interval(struct ttc_timer * timer,unsigned long cycles)110 static void ttc_set_interval(struct ttc_timer *timer,
111 					unsigned long cycles)
112 {
113 	u32 ctrl_reg;
114 
115 	/* Disable the counter, set the counter value  and re-enable counter */
116 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
117 	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
118 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
119 
120 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
121 
122 	/*
123 	 * Reset the counter (0x10) so that it starts from 0, one-shot
124 	 * mode makes this needed for timing to be right.
125 	 */
126 	ctrl_reg |= CNT_CNTRL_RESET;
127 	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
128 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
129 }
130 
131 /**
132  * ttc_clock_event_interrupt - Clock event timer interrupt handler
133  *
134  * @irq:	IRQ number of the Timer
135  * @dev_id:	void pointer to the ttc_timer instance
136  *
137  * returns: Always IRQ_HANDLED - success
138  **/
ttc_clock_event_interrupt(int irq,void * dev_id)139 static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
140 {
141 	struct ttc_timer_clockevent *ttce = dev_id;
142 	struct ttc_timer *timer = &ttce->ttc;
143 
144 	/* Acknowledge the interrupt and call event handler */
145 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
146 
147 	ttce->ce.event_handler(&ttce->ce);
148 
149 	return IRQ_HANDLED;
150 }
151 
152 /**
153  * __ttc_clocksource_read - Reads the timer counter register
154  *
155  * returns: Current timer counter register value
156  **/
__ttc_clocksource_read(struct clocksource * cs)157 static u64 __ttc_clocksource_read(struct clocksource *cs)
158 {
159 	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
160 
161 	return (u64)readl_relaxed(timer->base_addr +
162 				TTC_COUNT_VAL_OFFSET);
163 }
164 
ttc_sched_clock_read(void)165 static u64 notrace ttc_sched_clock_read(void)
166 {
167 	return readl_relaxed(ttc_sched_clock_val_reg);
168 }
169 
170 /**
171  * ttc_set_next_event - Sets the time interval for next event
172  *
173  * @cycles:	Timer interval ticks
174  * @evt:	Address of clock event instance
175  *
176  * returns: Always 0 - success
177  **/
ttc_set_next_event(unsigned long cycles,struct clock_event_device * evt)178 static int ttc_set_next_event(unsigned long cycles,
179 					struct clock_event_device *evt)
180 {
181 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
182 	struct ttc_timer *timer = &ttce->ttc;
183 
184 	ttc_set_interval(timer, cycles);
185 	return 0;
186 }
187 
188 /**
189  * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
190  *
191  * @evt:	Address of clock event instance
192  **/
ttc_shutdown(struct clock_event_device * evt)193 static int ttc_shutdown(struct clock_event_device *evt)
194 {
195 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
196 	struct ttc_timer *timer = &ttce->ttc;
197 	u32 ctrl_reg;
198 
199 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
200 	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
201 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
202 	return 0;
203 }
204 
ttc_set_periodic(struct clock_event_device * evt)205 static int ttc_set_periodic(struct clock_event_device *evt)
206 {
207 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
208 	struct ttc_timer *timer = &ttce->ttc;
209 
210 	ttc_set_interval(timer,
211 			 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
212 	return 0;
213 }
214 
ttc_resume(struct clock_event_device * evt)215 static int ttc_resume(struct clock_event_device *evt)
216 {
217 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
218 	struct ttc_timer *timer = &ttce->ttc;
219 	u32 ctrl_reg;
220 
221 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
222 	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
223 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
224 	return 0;
225 }
226 
ttc_rate_change_clocksource_cb(struct notifier_block * nb,unsigned long event,void * data)227 static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
228 		unsigned long event, void *data)
229 {
230 	struct clk_notifier_data *ndata = data;
231 	struct ttc_timer *ttc = to_ttc_timer(nb);
232 	struct ttc_timer_clocksource *ttccs = container_of(ttc,
233 			struct ttc_timer_clocksource, ttc);
234 
235 	switch (event) {
236 	case PRE_RATE_CHANGE:
237 	{
238 		u32 psv;
239 		unsigned long factor, rate_low, rate_high;
240 
241 		if (ndata->new_rate > ndata->old_rate) {
242 			factor = DIV_ROUND_CLOSEST(ndata->new_rate,
243 					ndata->old_rate);
244 			rate_low = ndata->old_rate;
245 			rate_high = ndata->new_rate;
246 		} else {
247 			factor = DIV_ROUND_CLOSEST(ndata->old_rate,
248 					ndata->new_rate);
249 			rate_low = ndata->new_rate;
250 			rate_high = ndata->old_rate;
251 		}
252 
253 		if (!is_power_of_2(factor))
254 				return NOTIFY_BAD;
255 
256 		if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
257 			return NOTIFY_BAD;
258 
259 		factor = __ilog2_u32(factor);
260 
261 		/*
262 		 * store timer clock ctrl register so we can restore it in case
263 		 * of an abort.
264 		 */
265 		ttccs->scale_clk_ctrl_reg_old =
266 			readl_relaxed(ttccs->ttc.base_addr +
267 			TTC_CLK_CNTRL_OFFSET);
268 
269 		psv = (ttccs->scale_clk_ctrl_reg_old &
270 				TTC_CLK_CNTRL_PSV_MASK) >>
271 				TTC_CLK_CNTRL_PSV_SHIFT;
272 		if (ndata->new_rate < ndata->old_rate)
273 			psv -= factor;
274 		else
275 			psv += factor;
276 
277 		/* prescaler within legal range? */
278 		if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
279 			return NOTIFY_BAD;
280 
281 		ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
282 			~TTC_CLK_CNTRL_PSV_MASK;
283 		ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
284 
285 
286 		/* scale down: adjust divider in post-change notification */
287 		if (ndata->new_rate < ndata->old_rate)
288 			return NOTIFY_DONE;
289 
290 		/* scale up: adjust divider now - before frequency change */
291 		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
292 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
293 		break;
294 	}
295 	case POST_RATE_CHANGE:
296 		/* scale up: pre-change notification did the adjustment */
297 		if (ndata->new_rate > ndata->old_rate)
298 			return NOTIFY_OK;
299 
300 		/* scale down: adjust divider now - after frequency change */
301 		writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
302 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
303 		break;
304 
305 	case ABORT_RATE_CHANGE:
306 		/* we have to undo the adjustment in case we scale up */
307 		if (ndata->new_rate < ndata->old_rate)
308 			return NOTIFY_OK;
309 
310 		/* restore original register value */
311 		writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
312 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
313 		fallthrough;
314 	default:
315 		return NOTIFY_DONE;
316 	}
317 
318 	return NOTIFY_DONE;
319 }
320 
ttc_setup_clocksource(struct clk * clk,void __iomem * base,u32 timer_width)321 static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
322 					 u32 timer_width)
323 {
324 	struct ttc_timer_clocksource *ttccs;
325 	int err;
326 
327 	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
328 	if (!ttccs)
329 		return -ENOMEM;
330 
331 	ttccs->ttc.clk = clk;
332 
333 	err = clk_prepare_enable(ttccs->ttc.clk);
334 	if (err) {
335 		kfree(ttccs);
336 		return err;
337 	}
338 
339 	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
340 
341 	ttccs->ttc.clk_rate_change_nb.notifier_call =
342 		ttc_rate_change_clocksource_cb;
343 	ttccs->ttc.clk_rate_change_nb.next = NULL;
344 
345 	err = clk_notifier_register(ttccs->ttc.clk,
346 				    &ttccs->ttc.clk_rate_change_nb);
347 	if (err)
348 		pr_warn("Unable to register clock notifier.\n");
349 
350 	ttccs->ttc.base_addr = base;
351 	ttccs->cs.name = "ttc_clocksource";
352 	ttccs->cs.rating = 200;
353 	ttccs->cs.read = __ttc_clocksource_read;
354 	ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
355 	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
356 
357 	/*
358 	 * Setup the clock source counter to be an incrementing counter
359 	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
360 	 * it by 32 also. Let it start running now.
361 	 */
362 	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
363 	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
364 		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
365 	writel_relaxed(CNT_CNTRL_RESET,
366 		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
367 
368 	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
369 	if (err) {
370 		kfree(ttccs);
371 		return err;
372 	}
373 
374 	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
375 	sched_clock_register(ttc_sched_clock_read, timer_width,
376 			     ttccs->ttc.freq / PRESCALE);
377 
378 	return 0;
379 }
380 
ttc_rate_change_clockevent_cb(struct notifier_block * nb,unsigned long event,void * data)381 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
382 		unsigned long event, void *data)
383 {
384 	struct clk_notifier_data *ndata = data;
385 	struct ttc_timer *ttc = to_ttc_timer(nb);
386 	struct ttc_timer_clockevent *ttcce = container_of(ttc,
387 			struct ttc_timer_clockevent, ttc);
388 
389 	switch (event) {
390 	case POST_RATE_CHANGE:
391 		/* update cached frequency */
392 		ttc->freq = ndata->new_rate;
393 
394 		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
395 
396 		fallthrough;
397 	case PRE_RATE_CHANGE:
398 	case ABORT_RATE_CHANGE:
399 	default:
400 		return NOTIFY_DONE;
401 	}
402 }
403 
ttc_setup_clockevent(struct clk * clk,void __iomem * base,u32 irq)404 static int __init ttc_setup_clockevent(struct clk *clk,
405 				       void __iomem *base, u32 irq)
406 {
407 	struct ttc_timer_clockevent *ttcce;
408 	int err;
409 
410 	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
411 	if (!ttcce)
412 		return -ENOMEM;
413 
414 	ttcce->ttc.clk = clk;
415 
416 	err = clk_prepare_enable(ttcce->ttc.clk);
417 	if (err)
418 		goto out_kfree;
419 
420 	ttcce->ttc.clk_rate_change_nb.notifier_call =
421 		ttc_rate_change_clockevent_cb;
422 	ttcce->ttc.clk_rate_change_nb.next = NULL;
423 
424 	err = clk_notifier_register(ttcce->ttc.clk,
425 				    &ttcce->ttc.clk_rate_change_nb);
426 	if (err) {
427 		pr_warn("Unable to register clock notifier.\n");
428 		goto out_kfree;
429 	}
430 
431 	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
432 
433 	ttcce->ttc.base_addr = base;
434 	ttcce->ce.name = "ttc_clockevent";
435 	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
436 	ttcce->ce.set_next_event = ttc_set_next_event;
437 	ttcce->ce.set_state_shutdown = ttc_shutdown;
438 	ttcce->ce.set_state_periodic = ttc_set_periodic;
439 	ttcce->ce.set_state_oneshot = ttc_shutdown;
440 	ttcce->ce.tick_resume = ttc_resume;
441 	ttcce->ce.rating = 200;
442 	ttcce->ce.irq = irq;
443 	ttcce->ce.cpumask = cpu_possible_mask;
444 
445 	/*
446 	 * Setup the clock event timer to be an interval timer which
447 	 * is prescaled by 32 using the interval interrupt. Leave it
448 	 * disabled for now.
449 	 */
450 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
451 	writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
452 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
453 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
454 
455 	err = request_irq(irq, ttc_clock_event_interrupt,
456 			  IRQF_TIMER, ttcce->ce.name, ttcce);
457 	if (err)
458 		goto out_kfree;
459 
460 	clockevents_config_and_register(&ttcce->ce,
461 			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
462 
463 	return 0;
464 
465 out_kfree:
466 	kfree(ttcce);
467 	return err;
468 }
469 
ttc_timer_probe(struct platform_device * pdev)470 static int __init ttc_timer_probe(struct platform_device *pdev)
471 {
472 	unsigned int irq;
473 	void __iomem *timer_baseaddr;
474 	struct clk *clk_cs, *clk_ce;
475 	static int initialized;
476 	int clksel, ret;
477 	u32 timer_width = 16;
478 	struct device_node *timer = pdev->dev.of_node;
479 
480 	if (initialized)
481 		return 0;
482 
483 	initialized = 1;
484 
485 	/*
486 	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
487 	 * and use it. Note that the event timer uses the interrupt and it's the
488 	 * 2nd TTC hence the irq_of_parse_and_map(,1)
489 	 */
490 	timer_baseaddr = devm_of_iomap(&pdev->dev, timer, 0, NULL);
491 	if (IS_ERR(timer_baseaddr)) {
492 		pr_err("ERROR: invalid timer base address\n");
493 		return PTR_ERR(timer_baseaddr);
494 	}
495 
496 	irq = irq_of_parse_and_map(timer, 1);
497 	if (irq <= 0) {
498 		pr_err("ERROR: invalid interrupt number\n");
499 		return -EINVAL;
500 	}
501 
502 	of_property_read_u32(timer, "timer-width", &timer_width);
503 
504 	clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
505 	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
506 	clk_cs = of_clk_get(timer, clksel);
507 	if (IS_ERR(clk_cs)) {
508 		pr_err("ERROR: timer input clock not found\n");
509 		return PTR_ERR(clk_cs);
510 	}
511 
512 	clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
513 	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
514 	clk_ce = of_clk_get(timer, clksel);
515 	if (IS_ERR(clk_ce)) {
516 		pr_err("ERROR: timer input clock not found\n");
517 		ret = PTR_ERR(clk_ce);
518 		goto put_clk_cs;
519 	}
520 
521 	ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
522 	if (ret)
523 		goto put_clk_ce;
524 
525 	ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
526 	if (ret)
527 		goto put_clk_ce;
528 
529 	pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
530 
531 	return 0;
532 
533 put_clk_ce:
534 	clk_put(clk_ce);
535 put_clk_cs:
536 	clk_put(clk_cs);
537 	return ret;
538 }
539 
540 static const struct of_device_id ttc_timer_of_match[] = {
541 	{.compatible = "cdns,ttc"},
542 	{},
543 };
544 
545 MODULE_DEVICE_TABLE(of, ttc_timer_of_match);
546 
547 static struct platform_driver ttc_timer_driver = {
548 	.driver = {
549 		.name	= "cdns_ttc_timer",
550 		.of_match_table = ttc_timer_of_match,
551 	},
552 };
553 builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);
554