1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2008 4 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 5 * 6 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. 7 */ 8 9 #ifndef __LINUX_DMA_IPU_DMA_H 10 #define __LINUX_DMA_IPU_DMA_H 11 12 #include <linux/types.h> 13 #include <linux/dmaengine.h> 14 15 /* IPU DMA Controller channel definitions. */ 16 enum ipu_channel { 17 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ 18 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ 19 IDMAC_ADC_0 = 1, 20 IDMAC_IC_2 = 2, 21 IDMAC_ADC_1 = 2, 22 IDMAC_IC_3 = 3, 23 IDMAC_IC_4 = 4, 24 IDMAC_IC_5 = 5, 25 IDMAC_IC_6 = 6, 26 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ 27 IDMAC_IC_8 = 8, 28 IDMAC_IC_9 = 9, 29 IDMAC_IC_10 = 10, 30 IDMAC_IC_11 = 11, 31 IDMAC_IC_12 = 12, 32 IDMAC_IC_13 = 13, 33 IDMAC_SDC_0 = 14, /* Background synchronous display data */ 34 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ 35 IDMAC_SDC_2 = 16, 36 IDMAC_SDC_3 = 17, 37 IDMAC_ADC_2 = 18, 38 IDMAC_ADC_3 = 19, 39 IDMAC_ADC_4 = 20, 40 IDMAC_ADC_5 = 21, 41 IDMAC_ADC_6 = 22, 42 IDMAC_ADC_7 = 23, 43 IDMAC_PF_0 = 24, 44 IDMAC_PF_1 = 25, 45 IDMAC_PF_2 = 26, 46 IDMAC_PF_3 = 27, 47 IDMAC_PF_4 = 28, 48 IDMAC_PF_5 = 29, 49 IDMAC_PF_6 = 30, 50 IDMAC_PF_7 = 31, 51 }; 52 53 /* Order significant! */ 54 enum ipu_channel_status { 55 IPU_CHANNEL_FREE, 56 IPU_CHANNEL_INITIALIZED, 57 IPU_CHANNEL_READY, 58 IPU_CHANNEL_ENABLED, 59 }; 60 61 #define IPU_CHANNELS_NUM 32 62 63 enum pixel_fmt { 64 /* 1 byte */ 65 IPU_PIX_FMT_GENERIC, 66 IPU_PIX_FMT_RGB332, 67 IPU_PIX_FMT_YUV420P, 68 IPU_PIX_FMT_YUV422P, 69 IPU_PIX_FMT_YUV420P2, 70 IPU_PIX_FMT_YVU422P, 71 /* 2 bytes */ 72 IPU_PIX_FMT_RGB565, 73 IPU_PIX_FMT_RGB666, 74 IPU_PIX_FMT_BGR666, 75 IPU_PIX_FMT_YUYV, 76 IPU_PIX_FMT_UYVY, 77 /* 3 bytes */ 78 IPU_PIX_FMT_RGB24, 79 IPU_PIX_FMT_BGR24, 80 /* 4 bytes */ 81 IPU_PIX_FMT_GENERIC_32, 82 IPU_PIX_FMT_RGB32, 83 IPU_PIX_FMT_BGR32, 84 IPU_PIX_FMT_ABGR32, 85 IPU_PIX_FMT_BGRA32, 86 IPU_PIX_FMT_RGBA32, 87 }; 88 89 enum ipu_color_space { 90 IPU_COLORSPACE_RGB, 91 IPU_COLORSPACE_YCBCR, 92 IPU_COLORSPACE_YUV 93 }; 94 95 /* 96 * Enumeration of IPU rotation modes 97 */ 98 enum ipu_rotate_mode { 99 /* Note the enum values correspond to BAM value */ 100 IPU_ROTATE_NONE = 0, 101 IPU_ROTATE_VERT_FLIP = 1, 102 IPU_ROTATE_HORIZ_FLIP = 2, 103 IPU_ROTATE_180 = 3, 104 IPU_ROTATE_90_RIGHT = 4, 105 IPU_ROTATE_90_RIGHT_VFLIP = 5, 106 IPU_ROTATE_90_RIGHT_HFLIP = 6, 107 IPU_ROTATE_90_LEFT = 7, 108 }; 109 110 /* 111 * Enumeration of DI ports for ADC. 112 */ 113 enum display_port { 114 DISP0, 115 DISP1, 116 DISP2, 117 DISP3 118 }; 119 120 struct idmac_video_param { 121 unsigned short in_width; 122 unsigned short in_height; 123 uint32_t in_pixel_fmt; 124 unsigned short out_width; 125 unsigned short out_height; 126 uint32_t out_pixel_fmt; 127 unsigned short out_stride; 128 bool graphics_combine_en; 129 bool global_alpha_en; 130 bool key_color_en; 131 enum display_port disp; 132 unsigned short out_left; 133 unsigned short out_top; 134 }; 135 136 /* 137 * Union of initialization parameters for a logical channel. So far only video 138 * parameters are used. 139 */ 140 union ipu_channel_param { 141 struct idmac_video_param video; 142 }; 143 144 struct idmac_tx_desc { 145 struct dma_async_tx_descriptor txd; 146 struct scatterlist *sg; /* scatterlist for this */ 147 unsigned int sg_len; /* tx-descriptor. */ 148 struct list_head list; 149 }; 150 151 struct idmac_channel { 152 struct dma_chan dma_chan; 153 dma_cookie_t completed; /* last completed cookie */ 154 union ipu_channel_param params; 155 enum ipu_channel link; /* input channel, linked to the output */ 156 enum ipu_channel_status status; 157 void *client; /* Only one client per channel */ 158 unsigned int n_tx_desc; 159 struct idmac_tx_desc *desc; /* allocated tx-descriptors */ 160 struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */ 161 struct list_head free_list; /* free tx-descriptors */ 162 struct list_head queue; /* queued tx-descriptors */ 163 spinlock_t lock; /* protects sg[0,1], queue */ 164 struct mutex chan_mutex; /* protects status, cookie, free_list */ 165 bool sec_chan_en; 166 int active_buffer; 167 unsigned int eof_irq; 168 char eof_name[16]; /* EOF IRQ name for request_irq() */ 169 }; 170 171 #define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd) 172 #define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan) 173 174 #endif /* __LINUX_DMA_IPU_DMA_H */ 175