1 /*
2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef HEXAGON_CPU_H
19 #define HEXAGON_CPU_H
20
21 #include "fpu/softfloat-types.h"
22
23 #include "cpu-qom.h"
24 #include "exec/cpu-defs.h"
25 #include "hex_regs.h"
26 #include "mmvec/mmvec.h"
27 #include "hw/registerfields.h"
28
29 #ifndef CONFIG_USER_ONLY
30 #error "Hexagon does not support system emulation"
31 #endif
32
33 #define NUM_PREGS 4
34 #define TOTAL_PER_THREAD_REGS 64
35
36 #define SLOTS_MAX 4
37 #define STORES_MAX 2
38 #define REG_WRITES_MAX 32
39 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */
40 #define VSTORES_MAX 2
41
42 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
43
44 #define MMU_USER_IDX 0
45
46 typedef struct {
47 target_ulong va;
48 uint8_t width;
49 uint32_t data32;
50 uint64_t data64;
51 } MemLog;
52
53 typedef struct {
54 target_ulong va;
55 int size;
56 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16);
57 MMVector data QEMU_ALIGNED(16);
58 } VStoreLog;
59
60 #define EXEC_STATUS_OK 0x0000
61 #define EXEC_STATUS_STOP 0x0002
62 #define EXEC_STATUS_REPLAY 0x0010
63 #define EXEC_STATUS_LOCKED 0x0020
64 #define EXEC_STATUS_EXCEPTION 0x0100
65
66
67 #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION)
68 #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY)
69 #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION))
70 #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION)
71
72 /* Maximum number of vector temps in a packet */
73 #define VECTOR_TEMPS_MAX 4
74
75 typedef struct CPUArchState {
76 target_ulong gpr[TOTAL_PER_THREAD_REGS];
77 target_ulong pred[NUM_PREGS];
78
79 /* For comparing with LLDB on target - see adjust_stack_ptrs function */
80 target_ulong last_pc_dumped;
81 target_ulong stack_start;
82
83 uint8_t slot_cancelled;
84 target_ulong new_value_usr;
85
86 MemLog mem_log_stores[STORES_MAX];
87
88 float_status fp_status;
89
90 target_ulong llsc_addr;
91 target_ulong llsc_val;
92 uint64_t llsc_val_i64;
93
94 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16);
95 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
96 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
97
98 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
99 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
100
101 /* Temporaries used within instructions */
102 MMVectorPair VuuV QEMU_ALIGNED(16);
103 MMVectorPair VvvV QEMU_ALIGNED(16);
104 MMVectorPair VxxV QEMU_ALIGNED(16);
105 MMVector vtmp QEMU_ALIGNED(16);
106 MMQReg qtmp QEMU_ALIGNED(16);
107
108 VStoreLog vstore[VSTORES_MAX];
109 target_ulong vstore_pending[VSTORES_MAX];
110 bool vtcm_pending;
111 VTCMStoreLog vtcm_log;
112 } CPUHexagonState;
113
114 typedef struct HexagonCPUClass {
115 CPUClass parent_class;
116
117 DeviceRealize parent_realize;
118 ResettablePhases parent_phases;
119 } HexagonCPUClass;
120
121 struct ArchCPU {
122 CPUState parent_obj;
123
124 CPUHexagonState env;
125
126 bool lldb_compat;
127 target_ulong lldb_stack_adjust;
128 bool short_circuit;
129 };
130
131 #include "cpu_bits.h"
132
133 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
134
135 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
136 uint32_t exception,
137 uintptr_t pc);
138
cpu_get_tb_cpu_state(CPUHexagonState * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)139 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
140 uint64_t *cs_base, uint32_t *flags)
141 {
142 uint32_t hex_flags = 0;
143 *pc = env->gpr[HEX_REG_PC];
144 *cs_base = 0;
145 if (*pc == env->gpr[HEX_REG_SA0]) {
146 hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
147 }
148 *flags = hex_flags;
149 if (*pc & PCALIGN_MASK) {
150 hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);
151 }
152 }
153
154 typedef HexagonCPU ArchCPU;
155
156 void hexagon_translate_init(void);
157 void hexagon_translate_code(CPUState *cs, TranslationBlock *tb,
158 int *max_insns, vaddr pc, void *host_pc);
159
160 #include "exec/cpu-all.h"
161
162 #endif /* HEXAGON_CPU_H */
163