xref: /openbmc/linux/drivers/net/wireless/ath/ath12k/dp.h (revision afb522b3)
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef ATH12K_DP_H
8 #define ATH12K_DP_H
9 
10 #include "hal_rx.h"
11 #include "hw.h"
12 
13 #define MAX_RXDMA_PER_PDEV     2
14 
15 struct ath12k_base;
16 struct ath12k_peer;
17 struct ath12k_dp;
18 struct ath12k_vif;
19 struct hal_tcl_status_ring;
20 struct ath12k_ext_irq_grp;
21 
22 #define DP_MON_PURGE_TIMEOUT_MS     100
23 #define DP_MON_SERVICE_BUDGET       128
24 
25 struct dp_srng {
26 	u32 *vaddr_unaligned;
27 	u32 *vaddr;
28 	dma_addr_t paddr_unaligned;
29 	dma_addr_t paddr;
30 	int size;
31 	u32 ring_id;
32 };
33 
34 struct dp_rxdma_ring {
35 	struct dp_srng refill_buf_ring;
36 	struct idr bufs_idr;
37 	/* Protects bufs_idr */
38 	spinlock_t idr_lock;
39 	int bufs_max;
40 };
41 
42 #define ATH12K_TX_COMPL_NEXT(x)	(((x) + 1) % DP_TX_COMP_RING_SIZE)
43 
44 struct dp_tx_ring {
45 	u8 tcl_data_ring_id;
46 	struct dp_srng tcl_data_ring;
47 	struct dp_srng tcl_comp_ring;
48 	struct hal_wbm_completion_ring_tx *tx_status;
49 	int tx_status_head;
50 	int tx_status_tail;
51 };
52 
53 struct ath12k_pdev_mon_stats {
54 	u32 status_ppdu_state;
55 	u32 status_ppdu_start;
56 	u32 status_ppdu_end;
57 	u32 status_ppdu_compl;
58 	u32 status_ppdu_start_mis;
59 	u32 status_ppdu_end_mis;
60 	u32 status_ppdu_done;
61 	u32 dest_ppdu_done;
62 	u32 dest_mpdu_done;
63 	u32 dest_mpdu_drop;
64 	u32 dup_mon_linkdesc_cnt;
65 	u32 dup_mon_buf_cnt;
66 };
67 
68 struct dp_link_desc_bank {
69 	void *vaddr_unaligned;
70 	void *vaddr;
71 	dma_addr_t paddr_unaligned;
72 	dma_addr_t paddr;
73 	u32 size;
74 };
75 
76 /* Size to enforce scatter idle list mode */
77 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
78 #define DP_LINK_DESC_BANKS_MAX 8
79 
80 #define DP_LINK_DESC_START	0x4000
81 #define DP_LINK_DESC_SHIFT	3
82 
83 #define DP_LINK_DESC_COOKIE_SET(id, page) \
84 	((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page))
85 
86 #define DP_LINK_DESC_BANK_MASK	GENMASK(2, 0)
87 
88 #define DP_RX_DESC_COOKIE_INDEX_MAX		0x3ffff
89 #define DP_RX_DESC_COOKIE_POOL_ID_MAX		0x1c0000
90 #define DP_RX_DESC_COOKIE_MAX	\
91 	(DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
92 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
93 
94 enum ath12k_dp_ppdu_state {
95 	DP_PPDU_STATUS_START,
96 	DP_PPDU_STATUS_DONE,
97 };
98 
99 struct dp_mon_mpdu {
100 	struct list_head list;
101 	struct sk_buff *head;
102 	struct sk_buff *tail;
103 };
104 
105 #define DP_MON_MAX_STATUS_BUF 32
106 
107 struct ath12k_mon_data {
108 	struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
109 	struct hal_rx_mon_ppdu_info mon_ppdu_info;
110 
111 	u32 mon_ppdu_status;
112 	u32 mon_last_buf_cookie;
113 	u64 mon_last_linkdesc_paddr;
114 	u16 chan_noise_floor;
115 
116 	struct ath12k_pdev_mon_stats rx_mon_stats;
117 	/* lock for monitor data */
118 	spinlock_t mon_lock;
119 	struct sk_buff_head rx_status_q;
120 	struct dp_mon_mpdu *mon_mpdu;
121 	struct list_head dp_rx_mon_mpdu_list;
122 	struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF];
123 	struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info;
124 	struct dp_mon_tx_ppdu_info *tx_data_ppdu_info;
125 };
126 
127 struct ath12k_pdev_dp {
128 	u32 mac_id;
129 	atomic_t num_tx_pending;
130 	wait_queue_head_t tx_empty_waitq;
131 	struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV];
132 	struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV];
133 
134 	struct ieee80211_rx_status rx_status;
135 	struct ath12k_mon_data mon_data;
136 };
137 
138 #define DP_NUM_CLIENTS_MAX 64
139 #define DP_AVG_TIDS_PER_CLIENT 2
140 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
141 #define DP_AVG_MSDUS_PER_FLOW 128
142 #define DP_AVG_FLOWS_PER_TID 2
143 #define DP_AVG_MPDUS_PER_TID_MAX 128
144 #define DP_AVG_MSDUS_PER_MPDU 4
145 
146 #define DP_RX_HASH_ENABLE	1 /* Enable hash based Rx steering */
147 
148 #define DP_BA_WIN_SZ_MAX	256
149 
150 #define DP_TCL_NUM_RING_MAX	4
151 
152 #define DP_IDLE_SCATTER_BUFS_MAX 16
153 
154 #define DP_WBM_RELEASE_RING_SIZE	64
155 #define DP_TCL_DATA_RING_SIZE		512
156 #define DP_TX_COMP_RING_SIZE		32768
157 #define DP_TX_IDR_SIZE			DP_TX_COMP_RING_SIZE
158 #define DP_TCL_CMD_RING_SIZE		32
159 #define DP_TCL_STATUS_RING_SIZE		32
160 #define DP_REO_DST_RING_MAX		8
161 #define DP_REO_DST_RING_SIZE		2048
162 #define DP_REO_REINJECT_RING_SIZE	32
163 #define DP_RX_RELEASE_RING_SIZE		1024
164 #define DP_REO_EXCEPTION_RING_SIZE	128
165 #define DP_REO_CMD_RING_SIZE		128
166 #define DP_REO_STATUS_RING_SIZE		2048
167 #define DP_RXDMA_BUF_RING_SIZE		4096
168 #define DP_RXDMA_REFILL_RING_SIZE	2048
169 #define DP_RXDMA_ERR_DST_RING_SIZE	1024
170 #define DP_RXDMA_MON_STATUS_RING_SIZE	1024
171 #define DP_RXDMA_MONITOR_BUF_RING_SIZE	4096
172 #define DP_RXDMA_MONITOR_DST_RING_SIZE	2048
173 #define DP_RXDMA_MONITOR_DESC_RING_SIZE	4096
174 #define DP_TX_MONITOR_BUF_RING_SIZE	4096
175 #define DP_TX_MONITOR_DEST_RING_SIZE	2048
176 
177 #define DP_TX_MONITOR_BUF_SIZE		2048
178 #define DP_TX_MONITOR_BUF_SIZE_MIN	48
179 #define DP_TX_MONITOR_BUF_SIZE_MAX	8192
180 
181 #define DP_RX_BUFFER_SIZE	2048
182 #define DP_RX_BUFFER_SIZE_LITE	1024
183 #define DP_RX_BUFFER_ALIGN_SIZE	128
184 
185 #define DP_RXDMA_BUF_COOKIE_BUF_ID	GENMASK(17, 0)
186 #define DP_RXDMA_BUF_COOKIE_PDEV_ID	GENMASK(19, 18)
187 
188 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
189 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
190 
191 #define DP_TX_DESC_ID_MAC_ID  GENMASK(1, 0)
192 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
193 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
194 
195 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20
196 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10
197 
198 #define ATH12K_NUM_POOL_TX_DESC	32768
199 
200 /* TODO: revisit this count during testing */
201 #define ATH12K_RX_DESC_COUNT	(12288)
202 
203 #define ATH12K_PAGE_SIZE	PAGE_SIZE
204 
205 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned
206  * SPT pages which makes lower 12bits 0
207  */
208 #define ATH12K_MAX_PPT_ENTRIES	1024
209 
210 /* Total 512 entries in a SPT, i.e 4K Page/8 */
211 #define ATH12K_MAX_SPT_ENTRIES	512
212 
213 #define ATH12K_NUM_RX_SPT_PAGES	((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES)
214 
215 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \
216 					  ATH12K_MAX_SPT_ENTRIES)
217 #define ATH12K_NUM_TX_SPT_PAGES	(ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES)
218 #define ATH12K_NUM_SPT_PAGES	(ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES)
219 
220 /* The SPT pages are divided for RX and TX, first block for RX
221  * and remaining for TX
222  */
223 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES
224 
225 #define ATH12K_DP_RX_DESC_MAGIC	0xBABABABA
226 
227 /* 4K aligned address have last 12 bits set to 0, this check is done
228  * so that two spt pages address can be stored per 8bytes
229  * of CMEM (PPT)
230  */
231 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF
232 #define ATH12K_SPT_4K_ALIGN_OFFSET 12
233 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index))
234 
235 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
236 #define ATH12K_CMEM_ADDR_MSB 0x10
237 
238 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
239 #define ATH12K_CC_SPT_MSB 8
240 #define ATH12K_CC_PPT_MSB 19
241 #define ATH12K_CC_PPT_SHIFT 9
242 #define ATH12k_DP_CC_COOKIE_SPT	GENMASK(8, 0)
243 #define ATH12K_DP_CC_COOKIE_PPT	GENMASK(19, 9)
244 
245 #define DP_REO_QREF_NUM		GENMASK(31, 16)
246 #define DP_MAX_PEER_ID		2047
247 
248 /* Total size of the LUT is based on 2K peers, each having reference
249  * for 17tids, note each entry is of type ath12k_reo_queue_ref
250  * hence total size is 2048 * 17 * 8 = 278528
251  */
252 #define DP_REOQ_LUT_SIZE	278528
253 
254 /* Invalid TX Bank ID value */
255 #define DP_INVALID_BANK_ID -1
256 
257 struct ath12k_dp_tx_bank_profile {
258 	u8 is_configured;
259 	u32 num_users;
260 	u32 bank_config;
261 };
262 
263 struct ath12k_hp_update_timer {
264 	struct timer_list timer;
265 	bool started;
266 	bool init;
267 	u32 tx_num;
268 	u32 timer_tx_num;
269 	u32 ring_id;
270 	u32 interval;
271 	struct ath12k_base *ab;
272 };
273 
274 struct ath12k_rx_desc_info {
275 	struct list_head list;
276 	struct sk_buff *skb;
277 	u32 cookie;
278 	u32 magic;
279 };
280 
281 struct ath12k_tx_desc_info {
282 	struct list_head list;
283 	struct sk_buff *skb;
284 	u32 desc_id; /* Cookie */
285 	u8 mac_id;
286 	u8 pool_id;
287 };
288 
289 struct ath12k_spt_info {
290 	dma_addr_t paddr;
291 	u64 *vaddr;
292 	struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES];
293 	struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES];
294 };
295 
296 struct ath12k_reo_queue_ref {
297 	u32 info0;
298 	u32 info1;
299 } __packed;
300 
301 struct ath12k_reo_q_addr_lut {
302 	dma_addr_t paddr;
303 	u32 *vaddr;
304 };
305 
306 struct ath12k_dp {
307 	struct ath12k_base *ab;
308 	u8 num_bank_profiles;
309 	/* protects the access and update of bank_profiles */
310 	spinlock_t tx_bank_lock;
311 	struct ath12k_dp_tx_bank_profile *bank_profiles;
312 	enum ath12k_htc_ep_id eid;
313 	struct completion htt_tgt_version_received;
314 	u8 htt_tgt_ver_major;
315 	u8 htt_tgt_ver_minor;
316 	struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
317 	struct dp_srng wbm_idle_ring;
318 	struct dp_srng wbm_desc_rel_ring;
319 	struct dp_srng tcl_cmd_ring;
320 	struct dp_srng tcl_status_ring;
321 	struct dp_srng reo_reinject_ring;
322 	struct dp_srng rx_rel_ring;
323 	struct dp_srng reo_except_ring;
324 	struct dp_srng reo_cmd_ring;
325 	struct dp_srng reo_status_ring;
326 	struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
327 	struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
328 	struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
329 	struct list_head reo_cmd_list;
330 	struct list_head reo_cmd_cache_flush_list;
331 	u32 reo_cmd_cache_flush_count;
332 
333 	/* protects access to below fields,
334 	 * - reo_cmd_list
335 	 * - reo_cmd_cache_flush_list
336 	 * - reo_cmd_cache_flush_count
337 	 */
338 	spinlock_t reo_cmd_lock;
339 	struct ath12k_hp_update_timer reo_cmd_timer;
340 	struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
341 	struct ath12k_spt_info *spt_info;
342 	u32 num_spt_pages;
343 	struct list_head rx_desc_free_list;
344 	struct list_head rx_desc_used_list;
345 	/* protects the free and used desc list */
346 	spinlock_t rx_desc_lock;
347 
348 	struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES];
349 	struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES];
350 	/* protects the free and used desc lists */
351 	spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES];
352 
353 	struct dp_rxdma_ring rx_refill_buf_ring;
354 	struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
355 	struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
356 	struct dp_rxdma_ring rxdma_mon_buf_ring;
357 	struct dp_rxdma_ring tx_mon_buf_ring;
358 	struct ath12k_reo_q_addr_lut reoq_lut;
359 };
360 
361 /* HTT definitions */
362 
363 #define HTT_TCL_META_DATA_TYPE			BIT(0)
364 #define HTT_TCL_META_DATA_VALID_HTT		BIT(1)
365 
366 /* vdev meta data */
367 #define HTT_TCL_META_DATA_VDEV_ID		GENMASK(9, 2)
368 #define HTT_TCL_META_DATA_PDEV_ID		GENMASK(11, 10)
369 #define HTT_TCL_META_DATA_HOST_INSPECTED	BIT(12)
370 
371 /* peer meta data */
372 #define HTT_TCL_META_DATA_PEER_ID		GENMASK(15, 2)
373 
374 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
375 
376 /* HTT tx completion is overlaid in wbm_release_ring */
377 #define HTT_TX_WBM_COMP_INFO0_STATUS		GENMASK(16, 13)
378 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON	GENMASK(3, 0)
379 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME	BIT(4)
380 
381 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI		GENMASK(31, 24)
382 
383 struct htt_tx_wbm_completion {
384 	__le32 rsvd0[2];
385 	__le32 info0;
386 	__le32 info1;
387 	__le32 info2;
388 	__le32 info3;
389 	__le32 info4;
390 	__le32 rsvd1;
391 
392 } __packed;
393 
394 enum htt_h2t_msg_type {
395 	HTT_H2T_MSG_TYPE_VERSION_REQ		= 0,
396 	HTT_H2T_MSG_TYPE_SRING_SETUP		= 0xb,
397 	HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG	= 0xc,
398 	HTT_H2T_MSG_TYPE_EXT_STATS_CFG		= 0x10,
399 	HTT_H2T_MSG_TYPE_PPDU_STATS_CFG		= 0x11,
400 	HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG	= 0x1a,
401 	HTT_H2T_MSG_TYPE_TX_MONITOR_CFG		= 0x1b,
402 };
403 
404 #define HTT_VER_REQ_INFO_MSG_ID		GENMASK(7, 0)
405 
406 struct htt_ver_req_cmd {
407 	__le32 ver_reg_info;
408 } __packed;
409 
410 enum htt_srng_ring_type {
411 	HTT_HW_TO_SW_RING,
412 	HTT_SW_TO_HW_RING,
413 	HTT_SW_TO_SW_RING,
414 };
415 
416 enum htt_srng_ring_id {
417 	HTT_RXDMA_HOST_BUF_RING,
418 	HTT_RXDMA_MONITOR_STATUS_RING,
419 	HTT_RXDMA_MONITOR_BUF_RING,
420 	HTT_RXDMA_MONITOR_DESC_RING,
421 	HTT_RXDMA_MONITOR_DEST_RING,
422 	HTT_HOST1_TO_FW_RXBUF_RING,
423 	HTT_HOST2_TO_FW_RXBUF_RING,
424 	HTT_RXDMA_NON_MONITOR_DEST_RING,
425 	HTT_TX_MON_HOST2MON_BUF_RING,
426 	HTT_TX_MON_MON2HOST_DEST_RING,
427 };
428 
429 /* host -> target  HTT_SRING_SETUP message
430  *
431  * After target is booted up, Host can send SRING setup message for
432  * each host facing LMAC SRING. Target setups up HW registers based
433  * on setup message and confirms back to Host if response_required is set.
434  * Host should wait for confirmation message before sending new SRING
435  * setup message
436  *
437  * The message would appear as follows:
438  *
439  * |31            24|23    20|19|18 16|15|14          8|7                0|
440  * |--------------- +-----------------+----------------+------------------|
441  * |    ring_type   |      ring_id    |    pdev_id     |     msg_type     |
442  * |----------------------------------------------------------------------|
443  * |                          ring_base_addr_lo                           |
444  * |----------------------------------------------------------------------|
445  * |                         ring_base_addr_hi                            |
446  * |----------------------------------------------------------------------|
447  * |ring_misc_cfg_flag|ring_entry_size|            ring_size              |
448  * |----------------------------------------------------------------------|
449  * |                         ring_head_offset32_remote_addr_lo            |
450  * |----------------------------------------------------------------------|
451  * |                         ring_head_offset32_remote_addr_hi            |
452  * |----------------------------------------------------------------------|
453  * |                         ring_tail_offset32_remote_addr_lo            |
454  * |----------------------------------------------------------------------|
455  * |                         ring_tail_offset32_remote_addr_hi            |
456  * |----------------------------------------------------------------------|
457  * |                          ring_msi_addr_lo                            |
458  * |----------------------------------------------------------------------|
459  * |                          ring_msi_addr_hi                            |
460  * |----------------------------------------------------------------------|
461  * |                          ring_msi_data                               |
462  * |----------------------------------------------------------------------|
463  * |         intr_timer_th            |IM|      intr_batch_counter_th     |
464  * |----------------------------------------------------------------------|
465  * |          reserved        |RR|PTCF|        intr_low_threshold         |
466  * |----------------------------------------------------------------------|
467  * Where
468  *     IM = sw_intr_mode
469  *     RR = response_required
470  *     PTCF = prefetch_timer_cfg
471  *
472  * The message is interpreted as follows:
473  * dword0  - b'0:7   - msg_type: This will be set to
474  *                     HTT_H2T_MSG_TYPE_SRING_SETUP
475  *           b'8:15  - pdev_id:
476  *                     0 (for rings at SOC/UMAC level),
477  *                     1/2/3 mac id (for rings at LMAC level)
478  *           b'16:23 - ring_id: identify which ring is to setup,
479  *                     more details can be got from enum htt_srng_ring_id
480  *           b'24:31 - ring_type: identify type of host rings,
481  *                     more details can be got from enum htt_srng_ring_type
482  * dword1  - b'0:31  - ring_base_addr_lo: Lower 32bits of ring base address
483  * dword2  - b'0:31  - ring_base_addr_hi: Upper 32bits of ring base address
484  * dword3  - b'0:15  - ring_size: size of the ring in unit of 4-bytes words
485  *           b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
486  *           b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
487  *                     SW_TO_HW_RING.
488  *                     Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
489  * dword4  - b'0:31  - ring_head_off32_remote_addr_lo:
490  *                     Lower 32 bits of memory address of the remote variable
491  *                     storing the 4-byte word offset that identifies the head
492  *                     element within the ring.
493  *                     (The head offset variable has type u32.)
494  *                     Valid for HW_TO_SW and SW_TO_SW rings.
495  * dword5  - b'0:31  - ring_head_off32_remote_addr_hi:
496  *                     Upper 32 bits of memory address of the remote variable
497  *                     storing the 4-byte word offset that identifies the head
498  *                     element within the ring.
499  *                     (The head offset variable has type u32.)
500  *                     Valid for HW_TO_SW and SW_TO_SW rings.
501  * dword6  - b'0:31  - ring_tail_off32_remote_addr_lo:
502  *                     Lower 32 bits of memory address of the remote variable
503  *                     storing the 4-byte word offset that identifies the tail
504  *                     element within the ring.
505  *                     (The tail offset variable has type u32.)
506  *                     Valid for HW_TO_SW and SW_TO_SW rings.
507  * dword7  - b'0:31  - ring_tail_off32_remote_addr_hi:
508  *                     Upper 32 bits of memory address of the remote variable
509  *                     storing the 4-byte word offset that identifies the tail
510  *                     element within the ring.
511  *                     (The tail offset variable has type u32.)
512  *                     Valid for HW_TO_SW and SW_TO_SW rings.
513  * dword8  - b'0:31  - ring_msi_addr_lo: Lower 32bits of MSI cfg address
514  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
515  * dword9  - b'0:31  - ring_msi_addr_hi: Upper 32bits of MSI cfg address
516  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
517  * dword10 - b'0:31  - ring_msi_data: MSI data
518  *                     Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
519  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
520  * dword11 - b'0:14  - intr_batch_counter_th:
521  *                     batch counter threshold is in units of 4-byte words.
522  *                     HW internally maintains and increments batch count.
523  *                     (see SRING spec for detail description).
524  *                     When batch count reaches threshold value, an interrupt
525  *                     is generated by HW.
526  *           b'15    - sw_intr_mode:
527  *                     This configuration shall be static.
528  *                     Only programmed at power up.
529  *                     0: generate pulse style sw interrupts
530  *                     1: generate level style sw interrupts
531  *           b'16:31 - intr_timer_th:
532  *                     The timer init value when timer is idle or is
533  *                     initialized to start downcounting.
534  *                     In 8us units (to cover a range of 0 to 524 ms)
535  * dword12 - b'0:15  - intr_low_threshold:
536  *                     Used only by Consumer ring to generate ring_sw_int_p.
537  *                     Ring entries low threshold water mark, that is used
538  *                     in combination with the interrupt timer as well as
539  *                     the clearing of the level interrupt.
540  *           b'16:18 - prefetch_timer_cfg:
541  *                     Used only by Consumer ring to set timer mode to
542  *                     support Application prefetch handling.
543  *                     The external tail offset/pointer will be updated
544  *                     at following intervals:
545  *                     3'b000: (Prefetch feature disabled; used only for debug)
546  *                     3'b001: 1 usec
547  *                     3'b010: 4 usec
548  *                     3'b011: 8 usec (default)
549  *                     3'b100: 16 usec
550  *                     Others: Reserved
551  *           b'19    - response_required:
552  *                     Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
553  *           b'20:31 - reserved:  reserved for future use
554  */
555 
556 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
557 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
558 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID	GENMASK(23, 16)
559 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE	GENMASK(31, 24)
560 
561 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE			GENMASK(15, 0)
562 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE		GENMASK(23, 16)
563 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS		BIT(25)
564 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP		BIT(27)
565 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP	BIT(28)
566 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP		BIT(29)
567 
568 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH	GENMASK(14, 0)
569 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE		BIT(15)
570 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH		GENMASK(31, 16)
571 
572 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH	GENMASK(15, 0)
573 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG	GENMASK(18, 16)
574 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED	BIT(19)
575 
576 struct htt_srng_setup_cmd {
577 	__le32 info0;
578 	__le32 ring_base_addr_lo;
579 	__le32 ring_base_addr_hi;
580 	__le32 info1;
581 	__le32 ring_head_off32_remote_addr_lo;
582 	__le32 ring_head_off32_remote_addr_hi;
583 	__le32 ring_tail_off32_remote_addr_lo;
584 	__le32 ring_tail_off32_remote_addr_hi;
585 	__le32 ring_msi_addr_lo;
586 	__le32 ring_msi_addr_hi;
587 	__le32 msi_data;
588 	__le32 intr_info;
589 	__le32 info2;
590 } __packed;
591 
592 /* host -> target FW  PPDU_STATS config message
593  *
594  * @details
595  * The following field definitions describe the format of the HTT host
596  * to target FW for PPDU_STATS_CFG msg.
597  * The message allows the host to configure the PPDU_STATS_IND messages
598  * produced by the target.
599  *
600  * |31          24|23          16|15           8|7            0|
601  * |-----------------------------------------------------------|
602  * |    REQ bit mask             |   pdev_mask  |   msg type   |
603  * |-----------------------------------------------------------|
604  * Header fields:
605  *  - MSG_TYPE
606  *    Bits 7:0
607  *    Purpose: identifies this is a req to configure ppdu_stats_ind from target
608  *    Value: 0x11
609  *  - PDEV_MASK
610  *    Bits 8:15
611  *    Purpose: identifies which pdevs this PPDU stats configuration applies to
612  *    Value: This is a overloaded field, refer to usage and interpretation of
613  *           PDEV in interface document.
614  *           Bit   8    :  Reserved for SOC stats
615  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
616  *                         Indicates MACID_MASK in DBS
617  *  - REQ_TLV_BIT_MASK
618  *    Bits 16:31
619  *    Purpose: each set bit indicates the corresponding PPDU stats TLV type
620  *        needs to be included in the target's PPDU_STATS_IND messages.
621  *    Value: refer htt_ppdu_stats_tlv_tag_t <<<???
622  *
623  */
624 
625 struct htt_ppdu_stats_cfg_cmd {
626 	__le32 msg;
627 } __packed;
628 
629 #define HTT_PPDU_STATS_CFG_MSG_TYPE		GENMASK(7, 0)
630 #define HTT_PPDU_STATS_CFG_PDEV_ID		GENMASK(15, 8)
631 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK	GENMASK(31, 16)
632 
633 enum htt_ppdu_stats_tag_type {
634 	HTT_PPDU_STATS_TAG_COMMON,
635 	HTT_PPDU_STATS_TAG_USR_COMMON,
636 	HTT_PPDU_STATS_TAG_USR_RATE,
637 	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
638 	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
639 	HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
640 	HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
641 	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
642 	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
643 	HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
644 	HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
645 	HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
646 	HTT_PPDU_STATS_TAG_INFO,
647 	HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
648 
649 	/* New TLV's are added above to this line */
650 	HTT_PPDU_STATS_TAG_MAX,
651 };
652 
653 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
654 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
655 				   | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
656 				   | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
657 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
658 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
659 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
660 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
661 
662 #define HTT_PPDU_STATS_TAG_PKTLOG  (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
663 				    BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
664 				    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
665 				    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
666 				    BIT(HTT_PPDU_STATS_TAG_INFO) | \
667 				    BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
668 				    HTT_PPDU_STATS_TAG_DEFAULT)
669 
670 enum htt_stats_internal_ppdu_frametype {
671 	HTT_STATS_PPDU_FTYPE_CTRL,
672 	HTT_STATS_PPDU_FTYPE_DATA,
673 	HTT_STATS_PPDU_FTYPE_BAR,
674 	HTT_STATS_PPDU_FTYPE_MAX
675 };
676 
677 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
678  *
679  * details:
680  *    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
681  *    configure RXDMA rings.
682  *    The configuration is per ring based and includes both packet subtypes
683  *    and PPDU/MPDU TLVs.
684  *
685  *    The message would appear as follows:
686  *
687  *    |31       26|25|24|23            16|15             8|7             0|
688  *    |-----------------+----------------+----------------+---------------|
689  *    |   rsvd1   |PS|SS|     ring_id    |     pdev_id    |    msg_type   |
690  *    |-------------------------------------------------------------------|
691  *    |              rsvd2               |           ring_buffer_size     |
692  *    |-------------------------------------------------------------------|
693  *    |                        packet_type_enable_flags_0                 |
694  *    |-------------------------------------------------------------------|
695  *    |                        packet_type_enable_flags_1                 |
696  *    |-------------------------------------------------------------------|
697  *    |                        packet_type_enable_flags_2                 |
698  *    |-------------------------------------------------------------------|
699  *    |                        packet_type_enable_flags_3                 |
700  *    |-------------------------------------------------------------------|
701  *    |                         tlv_filter_in_flags                       |
702  *    |-------------------------------------------------------------------|
703  * Where:
704  *     PS = pkt_swap
705  *     SS = status_swap
706  * The message is interpreted as follows:
707  * dword0 - b'0:7   - msg_type: This will be set to
708  *                    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
709  *          b'8:15  - pdev_id:
710  *                    0 (for rings at SOC/UMAC level),
711  *                    1/2/3 mac id (for rings at LMAC level)
712  *          b'16:23 - ring_id : Identify the ring to configure.
713  *                    More details can be got from enum htt_srng_ring_id
714  *          b'24    - status_swap: 1 is to swap status TLV
715  *          b'25    - pkt_swap:  1 is to swap packet TLV
716  *          b'26:31 - rsvd1:  reserved for future use
717  * dword1 - b'0:16  - ring_buffer_size: size of buffers referenced by rx ring,
718  *                    in byte units.
719  *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
720  *        - b'16:31 - rsvd2: Reserved for future use
721  * dword2 - b'0:31  - packet_type_enable_flags_0:
722  *                    Enable MGMT packet from 0b0000 to 0b1001
723  *                    bits from low to high: FP, MD, MO - 3 bits
724  *                        FP: Filter_Pass
725  *                        MD: Monitor_Direct
726  *                        MO: Monitor_Other
727  *                    10 mgmt subtypes * 3 bits -> 30 bits
728  *                    Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
729  * dword3 - b'0:31  - packet_type_enable_flags_1:
730  *                    Enable MGMT packet from 0b1010 to 0b1111
731  *                    bits from low to high: FP, MD, MO - 3 bits
732  *                    Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
733  * dword4 - b'0:31 -  packet_type_enable_flags_2:
734  *                    Enable CTRL packet from 0b0000 to 0b1001
735  *                    bits from low to high: FP, MD, MO - 3 bits
736  *                    Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
737  * dword5 - b'0:31  - packet_type_enable_flags_3:
738  *                    Enable CTRL packet from 0b1010 to 0b1111,
739  *                    MCAST_DATA, UCAST_DATA, NULL_DATA
740  *                    bits from low to high: FP, MD, MO - 3 bits
741  *                    Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
742  * dword6 - b'0:31 -  tlv_filter_in_flags:
743  *                    Filter in Attention/MPDU/PPDU/Header/User tlvs
744  *                    Refer to CFG_TLV_FILTER_IN_FLAG defs
745  */
746 
747 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
748 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
749 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID	GENMASK(23, 16)
750 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS		BIT(24)
751 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS		BIT(25)
752 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE	GENMASK(15, 0)
753 #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID      BIT(26)
754 
755 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET      GENMASK(15, 0)
756 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET      GENMASK(31, 16)
757 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET    GENMASK(15, 0)
758 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET  GENMASK(31, 16)
759 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET    GENMASK(15, 0)
760 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET  GENMASK(31, 16)
761 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET   GENMASK(15, 0)
762 
763 enum htt_rx_filter_tlv_flags {
764 	HTT_RX_FILTER_TLV_FLAGS_MPDU_START		= BIT(0),
765 	HTT_RX_FILTER_TLV_FLAGS_MSDU_START		= BIT(1),
766 	HTT_RX_FILTER_TLV_FLAGS_RX_PACKET		= BIT(2),
767 	HTT_RX_FILTER_TLV_FLAGS_MSDU_END		= BIT(3),
768 	HTT_RX_FILTER_TLV_FLAGS_MPDU_END		= BIT(4),
769 	HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER		= BIT(5),
770 	HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER		= BIT(6),
771 	HTT_RX_FILTER_TLV_FLAGS_ATTENTION		= BIT(7),
772 	HTT_RX_FILTER_TLV_FLAGS_PPDU_START		= BIT(8),
773 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END		= BIT(9),
774 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS	= BIT(10),
775 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT	= BIT(11),
776 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE	= BIT(12),
777 };
778 
779 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
780 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(0),
781 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(1),
782 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(2),
783 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(3),
784 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(4),
785 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(5),
786 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(6),
787 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(7),
788 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(8),
789 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(9),
790 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(10),
791 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(11),
792 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(12),
793 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(13),
794 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(14),
795 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(15),
796 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(16),
797 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(17),
798 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(18),
799 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(19),
800 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(20),
801 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(21),
802 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(22),
803 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(23),
804 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(24),
805 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(25),
806 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(26),
807 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(27),
808 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(28),
809 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(29),
810 };
811 
812 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
813 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(0),
814 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(1),
815 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(2),
816 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(3),
817 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(4),
818 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(5),
819 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(6),
820 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(7),
821 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(8),
822 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(9),
823 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(10),
824 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(11),
825 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(12),
826 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(13),
827 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(14),
828 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(15),
829 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(16),
830 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(17),
831 };
832 
833 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
834 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(0),
835 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(1),
836 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(2),
837 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(3),
838 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(4),
839 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(5),
840 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(6),
841 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(7),
842 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(8),
843 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(9),
844 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(10),
845 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(11),
846 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(12),
847 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(13),
848 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(14),
849 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(15),
850 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(16),
851 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(17),
852 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(18),
853 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(19),
854 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(20),
855 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(21),
856 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(22),
857 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(23),
858 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(24),
859 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(25),
860 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(26),
861 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(27),
862 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(28),
863 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(29),
864 };
865 
866 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
867 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(0),
868 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(1),
869 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(2),
870 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(3),
871 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(4),
872 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(5),
873 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(6),
874 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(7),
875 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(8),
876 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(9),
877 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(10),
878 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(11),
879 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(12),
880 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(13),
881 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(14),
882 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(15),
883 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(16),
884 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(17),
885 };
886 
887 enum htt_rx_data_pkt_filter_tlv_flasg3 {
888 	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(18),
889 	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(19),
890 	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(20),
891 	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(21),
892 	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(22),
893 	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(23),
894 	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(24),
895 	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(25),
896 	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(26),
897 };
898 
899 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
900 	(HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
901 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
902 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
903 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
904 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
905 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
906 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
907 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
908 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
909 
910 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
911 	(HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
912 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
913 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
914 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
915 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
916 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
917 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
918 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
919 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
920 
921 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
922 	(HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
923 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
924 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
925 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
926 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
927 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
928 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
929 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
930 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
931 
932 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
933 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
934 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
935 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
936 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
937 
938 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
939 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
940 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
941 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
942 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
943 
944 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
945 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
946 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
947 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
948 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
949 
950 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
951 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
952 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
953 
954 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
955 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
956 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
957 
958 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
959 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
960 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
961 
962 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
963 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
964 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
965 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
966 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
967 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
968 
969 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
970 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
971 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
972 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
973 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
974 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
975 
976 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
977 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
978 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
979 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
980 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
981 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
982 
983 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
984 				     | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
985 				     | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
986 
987 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
988 				     | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
989 				     | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
990 
991 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
992 				     | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
993 				     | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
994 
995 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
996 		(HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
997 		HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
998 
999 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
1000 		(HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
1001 		HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
1002 
1003 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
1004 		(HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
1005 		HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1006 
1007 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
1008 		(HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
1009 		HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
1010 
1011 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
1012 		(HTT_RX_FP_CTRL_FILTER_FLASG2 | \
1013 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1014 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1015 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1016 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1017 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1018 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1019 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1020 
1021 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
1022 		(HTT_RX_MO_CTRL_FILTER_FLASG2 | \
1023 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
1024 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
1025 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
1026 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
1027 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
1028 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
1029 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
1030 
1031 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
1032 
1033 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
1034 
1035 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
1036 
1037 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
1038 
1039 #define HTT_RX_MON_FILTER_TLV_FLAGS \
1040 		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1041 		HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1042 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1043 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1044 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1045 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1046 
1047 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
1048 		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1049 		HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
1050 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
1051 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
1052 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
1053 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
1054 
1055 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
1056 		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1057 		HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
1058 		HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1059 		HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
1060 		HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
1061 		HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
1062 		HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
1063 		HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
1064 
1065 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */
1066 #define HTT_RX_TLV_FLAGS_RXDMA_RING \
1067 		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
1068 		HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
1069 		HTT_RX_FILTER_TLV_FLAGS_MSDU_END)
1070 
1071 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
1072 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
1073 
1074 struct htt_rx_ring_selection_cfg_cmd {
1075 	__le32 info0;
1076 	__le32 info1;
1077 	__le32 pkt_type_en_flags0;
1078 	__le32 pkt_type_en_flags1;
1079 	__le32 pkt_type_en_flags2;
1080 	__le32 pkt_type_en_flags3;
1081 	__le32 rx_filter_tlv;
1082 	__le32 rx_packet_offset;
1083 	__le32 rx_mpdu_offset;
1084 	__le32 rx_msdu_offset;
1085 	__le32 rx_attn_offset;
1086 } __packed;
1087 
1088 struct htt_rx_ring_tlv_filter {
1089 	u32 rx_filter; /* see htt_rx_filter_tlv_flags */
1090 	u32 pkt_filter_flags0; /* MGMT */
1091 	u32 pkt_filter_flags1; /* MGMT */
1092 	u32 pkt_filter_flags2; /* CTRL */
1093 	u32 pkt_filter_flags3; /* DATA */
1094 	bool offset_valid;
1095 	u16 rx_packet_offset;
1096 	u16 rx_header_offset;
1097 	u16 rx_mpdu_end_offset;
1098 	u16 rx_mpdu_start_offset;
1099 	u16 rx_msdu_end_offset;
1100 	u16 rx_msdu_start_offset;
1101 	u16 rx_attn_offset;
1102 };
1103 
1104 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT  0x0
1105 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL  0x1
1106 #define HTT_STATS_FRAME_CTRL_TYPE_DATA  0x2
1107 #define HTT_STATS_FRAME_CTRL_TYPE_RESV  0x3
1108 
1109 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
1110 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
1111 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID	GENMASK(23, 16)
1112 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS		BIT(24)
1113 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS		BIT(25)
1114 
1115 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE	GENMASK(15, 0)
1116 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE		GENMASK(18, 16)
1117 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT	GENMASK(21, 19)
1118 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL	GENMASK(24, 22)
1119 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA	GENMASK(27, 25)
1120 
1121 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG	GENMASK(2, 0)
1122 
1123 struct htt_tx_ring_selection_cfg_cmd {
1124 	__le32 info0;
1125 	__le32 info1;
1126 	__le32 info2;
1127 	__le32 tlv_filter_mask_in0;
1128 	__le32 tlv_filter_mask_in1;
1129 	__le32 tlv_filter_mask_in2;
1130 	__le32 tlv_filter_mask_in3;
1131 	__le32 reserved[3];
1132 } __packed;
1133 
1134 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN	GENMASK(3, 0)
1135 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN	GENMASK(7, 4)
1136 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN	GENMASK(11, 8)
1137 
1138 #define HTT_TX_MON_FILTER_HYBRID_MODE \
1139 		(HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \
1140 		HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \
1141 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \
1142 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \
1143 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \
1144 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \
1145 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \
1146 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \
1147 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \
1148 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \
1149 		HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \
1150 		HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \
1151 		HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2)
1152 
1153 struct htt_tx_ring_tlv_filter {
1154 	u32 tx_mon_downstream_tlv_flags;
1155 	u32 tx_mon_upstream_tlv_flags0;
1156 	u32 tx_mon_upstream_tlv_flags1;
1157 	u32 tx_mon_upstream_tlv_flags2;
1158 	bool tx_mon_mgmt_filter;
1159 	bool tx_mon_data_filter;
1160 	bool tx_mon_ctrl_filter;
1161 	u16 tx_mon_pkt_dma_len;
1162 } __packed;
1163 
1164 enum htt_tx_mon_upstream_tlv_flags0 {
1165 	HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS		= BIT(1),
1166 	HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS		= BIT(2),
1167 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START		= BIT(3),
1168 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END		= BIT(4),
1169 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU	= BIT(5),
1170 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU	= BIT(6),
1171 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA	= BIT(7),
1172 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA		= BIT(8),
1173 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT	= BIT(9),
1174 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT		= BIT(10),
1175 	HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE	= BIT(11),
1176 	HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK		= BIT(12),
1177 	HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK		= BIT(13),
1178 	HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS			= BIT(14),
1179 	HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO		= BIT(15),
1180 	HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2	= BIT(16),
1181 };
1182 
1183 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32	BIT(11)
1184 
1185 /* HTT message target->host */
1186 
1187 enum htt_t2h_msg_type {
1188 	HTT_T2H_MSG_TYPE_VERSION_CONF,
1189 	HTT_T2H_MSG_TYPE_PEER_MAP	= 0x3,
1190 	HTT_T2H_MSG_TYPE_PEER_UNMAP	= 0x4,
1191 	HTT_T2H_MSG_TYPE_RX_ADDBA	= 0x5,
1192 	HTT_T2H_MSG_TYPE_PKTLOG		= 0x8,
1193 	HTT_T2H_MSG_TYPE_SEC_IND	= 0xb,
1194 	HTT_T2H_MSG_TYPE_PEER_MAP2	= 0x1e,
1195 	HTT_T2H_MSG_TYPE_PEER_UNMAP2	= 0x1f,
1196 	HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1197 	HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1198 	HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1199 	HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28,
1200 	HTT_T2H_MSG_TYPE_PEER_MAP3	= 0x2b,
1201 	HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c,
1202 };
1203 
1204 #define HTT_TARGET_VERSION_MAJOR 3
1205 
1206 #define HTT_T2H_MSG_TYPE		GENMASK(7, 0)
1207 #define HTT_T2H_VERSION_CONF_MINOR	GENMASK(15, 8)
1208 #define HTT_T2H_VERSION_CONF_MAJOR	GENMASK(23, 16)
1209 
1210 struct htt_t2h_version_conf_msg {
1211 	__le32 version;
1212 } __packed;
1213 
1214 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID	GENMASK(15, 8)
1215 #define HTT_T2H_PEER_MAP_INFO_PEER_ID	GENMASK(31, 16)
1216 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16	GENMASK(15, 0)
1217 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID	GENMASK(31, 16)
1218 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL	GENMASK(15, 0)
1219 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M	BIT(16)
1220 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S	16
1221 
1222 struct htt_t2h_peer_map_event {
1223 	__le32 info;
1224 	__le32 mac_addr_l32;
1225 	__le32 info1;
1226 	__le32 info2;
1227 } __packed;
1228 
1229 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID	HTT_T2H_PEER_MAP_INFO_VDEV_ID
1230 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID	HTT_T2H_PEER_MAP_INFO_PEER_ID
1231 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1232 					HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1233 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1234 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1235 
1236 struct htt_t2h_peer_unmap_event {
1237 	__le32 info;
1238 	__le32 mac_addr_l32;
1239 	__le32 info1;
1240 } __packed;
1241 
1242 struct htt_resp_msg {
1243 	union {
1244 		struct htt_t2h_version_conf_msg version_msg;
1245 		struct htt_t2h_peer_map_event peer_map_ev;
1246 		struct htt_t2h_peer_unmap_event peer_unmap_ev;
1247 	};
1248 } __packed;
1249 
1250 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\
1251 	(((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32)))
1252 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE		GENMASK(7, 0)
1253 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID		GENMASK(15, 8)
1254 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV		GENMASK(23, 16)
1255 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES	GENMASK(15, 0)
1256 #define HTT_VDEV_TXRX_STATS_COMMON_TLV		0
1257 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV	1
1258 
1259 struct htt_t2h_vdev_txrx_stats_ind {
1260 	__le32 vdev_id;
1261 	__le32 rx_msdu_byte_cnt_lo;
1262 	__le32 rx_msdu_byte_cnt_hi;
1263 	__le32 rx_msdu_cnt_lo;
1264 	__le32 rx_msdu_cnt_hi;
1265 	__le32 tx_msdu_byte_cnt_lo;
1266 	__le32 tx_msdu_byte_cnt_hi;
1267 	__le32 tx_msdu_cnt_lo;
1268 	__le32 tx_msdu_cnt_hi;
1269 	__le32 tx_retry_cnt_lo;
1270 	__le32 tx_retry_cnt_hi;
1271 	__le32 tx_retry_byte_cnt_lo;
1272 	__le32 tx_retry_byte_cnt_hi;
1273 	__le32 tx_drop_cnt_lo;
1274 	__le32 tx_drop_cnt_hi;
1275 	__le32 tx_drop_byte_cnt_lo;
1276 	__le32 tx_drop_byte_cnt_hi;
1277 	__le32 msdu_ttl_cnt_lo;
1278 	__le32 msdu_ttl_cnt_hi;
1279 	__le32 msdu_ttl_byte_cnt_lo;
1280 	__le32 msdu_ttl_byte_cnt_hi;
1281 } __packed;
1282 
1283 struct htt_t2h_vdev_common_stats_tlv {
1284 	__le32 soc_drop_count_lo;
1285 	__le32 soc_drop_count_hi;
1286 } __packed;
1287 
1288 /* ppdu stats
1289  *
1290  * @details
1291  * The following field definitions describe the format of the HTT target
1292  * to host ppdu stats indication message.
1293  *
1294  *
1295  * |31                         16|15   12|11   10|9      8|7            0 |
1296  * |----------------------------------------------------------------------|
1297  * |    payload_size             | rsvd  |pdev_id|mac_id  |    msg type   |
1298  * |----------------------------------------------------------------------|
1299  * |                          ppdu_id                                     |
1300  * |----------------------------------------------------------------------|
1301  * |                        Timestamp in us                               |
1302  * |----------------------------------------------------------------------|
1303  * |                          reserved                                    |
1304  * |----------------------------------------------------------------------|
1305  * |                    type-specific stats info                          |
1306  * |                     (see htt_ppdu_stats.h)                           |
1307  * |----------------------------------------------------------------------|
1308  * Header fields:
1309  *  - MSG_TYPE
1310  *    Bits 7:0
1311  *    Purpose: Identifies this is a PPDU STATS indication
1312  *             message.
1313  *    Value: 0x1d
1314  *  - mac_id
1315  *    Bits 9:8
1316  *    Purpose: mac_id of this ppdu_id
1317  *    Value: 0-3
1318  *  - pdev_id
1319  *    Bits 11:10
1320  *    Purpose: pdev_id of this ppdu_id
1321  *    Value: 0-3
1322  *     0 (for rings at SOC level),
1323  *     1/2/3 PDEV -> 0/1/2
1324  *  - payload_size
1325  *    Bits 31:16
1326  *    Purpose: total tlv size
1327  *    Value: payload_size in bytes
1328  */
1329 
1330 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1331 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1332 
1333 struct ath12k_htt_ppdu_stats_msg {
1334 	__le32 info;
1335 	__le32 ppdu_id;
1336 	__le32 timestamp;
1337 	__le32 rsvd;
1338 	u8 data[];
1339 } __packed;
1340 
1341 struct htt_tlv {
1342 	__le32 header;
1343 	u8 value[];
1344 } __packed;
1345 
1346 #define HTT_TLV_TAG			GENMASK(11, 0)
1347 #define HTT_TLV_LEN			GENMASK(23, 12)
1348 
1349 enum HTT_PPDU_STATS_BW {
1350 	HTT_PPDU_STATS_BANDWIDTH_5MHZ   = 0,
1351 	HTT_PPDU_STATS_BANDWIDTH_10MHZ  = 1,
1352 	HTT_PPDU_STATS_BANDWIDTH_20MHZ  = 2,
1353 	HTT_PPDU_STATS_BANDWIDTH_40MHZ  = 3,
1354 	HTT_PPDU_STATS_BANDWIDTH_80MHZ  = 4,
1355 	HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1356 	HTT_PPDU_STATS_BANDWIDTH_DYN    = 6,
1357 };
1358 
1359 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M	GENMASK(7, 0)
1360 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M	GENMASK(15, 8)
1361 /* bw - HTT_PPDU_STATS_BW */
1362 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M		GENMASK(19, 16)
1363 
1364 struct htt_ppdu_stats_common {
1365 	__le32 ppdu_id;
1366 	__le16 sched_cmdid;
1367 	u8 ring_id;
1368 	u8 num_users;
1369 	__le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1370 	__le32 chain_mask;
1371 	__le32 fes_duration_us; /* frame exchange sequence */
1372 	__le32 ppdu_sch_eval_start_tstmp_us;
1373 	__le32 ppdu_sch_end_tstmp_us;
1374 	__le32 ppdu_start_tstmp_us;
1375 	/* BIT [15 :  0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1376 	 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1377 	 */
1378 	__le16 phy_mode;
1379 	__le16 bw_mhz;
1380 } __packed;
1381 
1382 enum htt_ppdu_stats_gi {
1383 	HTT_PPDU_STATS_SGI_0_8_US,
1384 	HTT_PPDU_STATS_SGI_0_4_US,
1385 	HTT_PPDU_STATS_SGI_1_6_US,
1386 	HTT_PPDU_STATS_SGI_3_2_US,
1387 };
1388 
1389 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M	GENMASK(3, 0)
1390 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M	GENMASK(11, 4)
1391 
1392 enum HTT_PPDU_STATS_PPDU_TYPE {
1393 	HTT_PPDU_STATS_PPDU_TYPE_SU,
1394 	HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO,
1395 	HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA,
1396 	HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA,
1397 	HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG,
1398 	HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN,
1399 	HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP,
1400 	HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG,
1401 	HTT_PPDU_STATS_PPDU_TYPE_UL_RESP,
1402 	HTT_PPDU_STATS_PPDU_TYPE_MAX
1403 };
1404 
1405 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M	BIT(0)
1406 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M	GENMASK(5, 1)
1407 
1408 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M	GENMASK(1, 0)
1409 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M		BIT(2)
1410 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M		BIT(3)
1411 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M		GENMASK(7, 4)
1412 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M		GENMASK(11, 8)
1413 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M		GENMASK(15, 12)
1414 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M		GENMASK(19, 16)
1415 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M	GENMASK(23, 20)
1416 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M		GENMASK(27, 24)
1417 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M		BIT(28)
1418 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M		BIT(29)
1419 
1420 #define HTT_USR_RATE_PREAMBLE(_val) \
1421 		le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M)
1422 #define HTT_USR_RATE_BW(_val) \
1423 		le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M)
1424 #define HTT_USR_RATE_NSS(_val) \
1425 		le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M)
1426 #define HTT_USR_RATE_MCS(_val) \
1427 		le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M)
1428 #define HTT_USR_RATE_GI(_val) \
1429 		le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M)
1430 #define HTT_USR_RATE_DCM(_val) \
1431 		le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M)
1432 
1433 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M		GENMASK(1, 0)
1434 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M		BIT(2)
1435 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M		BIT(3)
1436 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M		GENMASK(7, 4)
1437 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M		GENMASK(11, 8)
1438 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M		GENMASK(15, 12)
1439 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M		GENMASK(19, 16)
1440 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M		GENMASK(23, 20)
1441 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M		GENMASK(27, 24)
1442 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M		BIT(28)
1443 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M		BIT(29)
1444 
1445 struct htt_ppdu_stats_user_rate {
1446 	u8 tid_num;
1447 	u8 reserved0;
1448 	__le16 sw_peer_id;
1449 	__le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1450 	__le16 ru_end;
1451 	__le16 ru_start;
1452 	__le16 resp_ru_end;
1453 	__le16 resp_ru_start;
1454 	__le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1455 	__le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1456 	/* Note: resp_rate_info is only valid for if resp_type is UL */
1457 	__le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1458 } __packed;
1459 
1460 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M		GENMASK(7, 0)
1461 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M		BIT(8)
1462 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M	GENMASK(10, 9)
1463 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M		GENMASK(13, 11)
1464 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M		BIT(14)
1465 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M		GENMASK(31, 16)
1466 
1467 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1468 			u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M)
1469 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1470 			u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M)
1471 #define HTT_TX_INFO_RATECODE(_flags) \
1472 			u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M)
1473 #define HTT_TX_INFO_PEERID(_flags) \
1474 			u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M)
1475 
1476 struct htt_tx_ppdu_stats_info {
1477 	struct htt_tlv tlv_hdr;
1478 	__le32 tx_success_bytes;
1479 	__le32 tx_retry_bytes;
1480 	__le32 tx_failed_bytes;
1481 	__le32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
1482 	__le16 tx_success_msdus;
1483 	__le16 tx_retry_msdus;
1484 	__le16 tx_failed_msdus;
1485 	__le16 tx_duration; /* united in us */
1486 } __packed;
1487 
1488 enum  htt_ppdu_stats_usr_compln_status {
1489 	HTT_PPDU_STATS_USER_STATUS_OK,
1490 	HTT_PPDU_STATS_USER_STATUS_FILTERED,
1491 	HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1492 	HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1493 	HTT_PPDU_STATS_USER_STATUS_ABORT,
1494 };
1495 
1496 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M	GENMASK(3, 0)
1497 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M	GENMASK(7, 4)
1498 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M		BIT(8)
1499 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M		GENMASK(12, 9)
1500 
1501 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1502 	    le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M)
1503 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1504 	    le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M)
1505 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1506 	    le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M)
1507 
1508 struct htt_ppdu_stats_usr_cmpltn_cmn {
1509 	u8 status;
1510 	u8 tid_num;
1511 	__le16 sw_peer_id;
1512 	/* RSSI value of last ack packet (units = dB above noise floor) */
1513 	__le32 ack_rssi;
1514 	__le16 mpdu_tried;
1515 	__le16 mpdu_success;
1516 	__le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1517 } __packed;
1518 
1519 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M	GENMASK(8, 0)
1520 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M	GENMASK(24, 9)
1521 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM	GENMASK(31, 25)
1522 
1523 #define HTT_PPDU_STATS_NON_QOS_TID	16
1524 
1525 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1526 	__le32 ppdu_id;
1527 	__le16 sw_peer_id;
1528 	__le16 reserved0;
1529 	__le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1530 	__le16 current_seq;
1531 	__le16 start_seq;
1532 	__le32 success_bytes;
1533 } __packed;
1534 
1535 struct htt_ppdu_user_stats {
1536 	u16 peer_id;
1537 	u16 delay_ba;
1538 	u32 tlv_flags;
1539 	bool is_valid_peer_id;
1540 	struct htt_ppdu_stats_user_rate rate;
1541 	struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1542 	struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1543 };
1544 
1545 #define HTT_PPDU_STATS_MAX_USERS	8
1546 #define HTT_PPDU_DESC_MAX_DEPTH	16
1547 
1548 struct htt_ppdu_stats {
1549 	struct htt_ppdu_stats_common common;
1550 	struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1551 };
1552 
1553 struct htt_ppdu_stats_info {
1554 	u32 tlv_bitmap;
1555 	u32 ppdu_id;
1556 	u32 frame_type;
1557 	u32 frame_ctrl;
1558 	u32 delay_ba;
1559 	u32 bar_num_users;
1560 	struct htt_ppdu_stats ppdu_stats;
1561 	struct list_head list;
1562 };
1563 
1564 /* @brief target -> host MLO offset indiciation message
1565  *
1566  * @details
1567  * The following field definitions describe the format of the HTT target
1568  * to host mlo offset indication message.
1569  *
1570  *
1571  * |31        29|28    |26|25  22|21 16|15  13|12     10 |9     8|7     0|
1572  * |---------------------------------------------------------------------|
1573  * |   rsvd1    | mac_freq                    |chip_id   |pdev_id|msgtype|
1574  * |---------------------------------------------------------------------|
1575  * |                           sync_timestamp_lo_us                      |
1576  * |---------------------------------------------------------------------|
1577  * |                           sync_timestamp_hi_us                      |
1578  * |---------------------------------------------------------------------|
1579  * |                           mlo_offset_lo                             |
1580  * |---------------------------------------------------------------------|
1581  * |                           mlo_offset_hi                             |
1582  * |---------------------------------------------------------------------|
1583  * |                           mlo_offset_clcks                          |
1584  * |---------------------------------------------------------------------|
1585  * |   rsvd2           | mlo_comp_clks |mlo_comp_us                      |
1586  * |---------------------------------------------------------------------|
1587  * |   rsvd3                   |mlo_comp_timer                           |
1588  * |---------------------------------------------------------------------|
1589  * Header fields
1590  *  - MSG_TYPE
1591  *    Bits 7:0
1592  *    Purpose: Identifies this is a MLO offset indication msg
1593  *  - PDEV_ID
1594  *    Bits 9:8
1595  *    Purpose: Pdev of this MLO offset
1596  *  - CHIP_ID
1597  *    Bits 12:10
1598  *    Purpose: chip_id of this MLO offset
1599  *  - MAC_FREQ
1600  *    Bits 28:13
1601  *  - SYNC_TIMESTAMP_LO_US
1602  *    Purpose: clock frequency of the mac HW block in MHz
1603  *    Bits: 31:0
1604  *    Purpose: lower 32 bits of the WLAN global time stamp at which
1605  *             last sync interrupt was received
1606  *  - SYNC_TIMESTAMP_HI_US
1607  *    Bits: 31:0
1608  *    Purpose: upper 32 bits of WLAN global time stamp at which
1609  *             last sync interrupt was received
1610  *  - MLO_OFFSET_LO
1611  *    Bits: 31:0
1612  *    Purpose: lower 32 bits of the MLO offset in us
1613  *  - MLO_OFFSET_HI
1614  *    Bits: 31:0
1615  *    Purpose: upper 32 bits of the MLO offset in us
1616  *  - MLO_COMP_US
1617  *    Bits: 15:0
1618  *    Purpose: MLO time stamp compensation applied in us
1619  *  - MLO_COMP_CLCKS
1620  *    Bits: 25:16
1621  *    Purpose: MLO time stamp compensation applied in clock ticks
1622  *  - MLO_COMP_TIMER
1623  *    Bits: 21:0
1624  *    Purpose: Periodic timer at which compensation is applied
1625  */
1626 
1627 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE        GENMASK(7, 0)
1628 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID         GENMASK(9, 8)
1629 
1630 struct ath12k_htt_mlo_offset_msg {
1631 	__le32 info;
1632 	__le32 sync_timestamp_lo_us;
1633 	__le32 sync_timestamp_hi_us;
1634 	__le32 mlo_offset_hi;
1635 	__le32 mlo_offset_lo;
1636 	__le32 mlo_offset_clks;
1637 	__le32 mlo_comp_clks;
1638 	__le32 mlo_comp_timer;
1639 } __packed;
1640 
1641 /* @brief host -> target FW extended statistics retrieve
1642  *
1643  * @details
1644  * The following field definitions describe the format of the HTT host
1645  * to target FW extended stats retrieve message.
1646  * The message specifies the type of stats the host wants to retrieve.
1647  *
1648  * |31          24|23          16|15           8|7            0|
1649  * |-----------------------------------------------------------|
1650  * |   reserved   | stats type   |   pdev_mask  |   msg type   |
1651  * |-----------------------------------------------------------|
1652  * |                   config param [0]                        |
1653  * |-----------------------------------------------------------|
1654  * |                   config param [1]                        |
1655  * |-----------------------------------------------------------|
1656  * |                   config param [2]                        |
1657  * |-----------------------------------------------------------|
1658  * |                   config param [3]                        |
1659  * |-----------------------------------------------------------|
1660  * |                         reserved                          |
1661  * |-----------------------------------------------------------|
1662  * |                        cookie LSBs                        |
1663  * |-----------------------------------------------------------|
1664  * |                        cookie MSBs                        |
1665  * |-----------------------------------------------------------|
1666  * Header fields:
1667  *  - MSG_TYPE
1668  *    Bits 7:0
1669  *    Purpose: identifies this is a extended stats upload request message
1670  *    Value: 0x10
1671  *  - PDEV_MASK
1672  *    Bits 8:15
1673  *    Purpose: identifies the mask of PDEVs to retrieve stats from
1674  *    Value: This is a overloaded field, refer to usage and interpretation of
1675  *           PDEV in interface document.
1676  *           Bit   8    :  Reserved for SOC stats
1677  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
1678  *                         Indicates MACID_MASK in DBS
1679  *  - STATS_TYPE
1680  *    Bits 23:16
1681  *    Purpose: identifies which FW statistics to upload
1682  *    Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1683  *  - Reserved
1684  *    Bits 31:24
1685  *  - CONFIG_PARAM [0]
1686  *    Bits 31:0
1687  *    Purpose: give an opaque configuration value to the specified stats type
1688  *    Value: stats-type specific configuration value
1689  *           Refer to htt_stats.h for interpretation for each stats sub_type
1690  *  - CONFIG_PARAM [1]
1691  *    Bits 31:0
1692  *    Purpose: give an opaque configuration value to the specified stats type
1693  *    Value: stats-type specific configuration value
1694  *           Refer to htt_stats.h for interpretation for each stats sub_type
1695  *  - CONFIG_PARAM [2]
1696  *    Bits 31:0
1697  *    Purpose: give an opaque configuration value to the specified stats type
1698  *    Value: stats-type specific configuration value
1699  *           Refer to htt_stats.h for interpretation for each stats sub_type
1700  *  - CONFIG_PARAM [3]
1701  *    Bits 31:0
1702  *    Purpose: give an opaque configuration value to the specified stats type
1703  *    Value: stats-type specific configuration value
1704  *           Refer to htt_stats.h for interpretation for each stats sub_type
1705  *  - Reserved [31:0] for future use.
1706  *  - COOKIE_LSBS
1707  *    Bits 31:0
1708  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1709  *        message with its preceding host->target stats request message.
1710  *    Value: LSBs of the opaque cookie specified by the host-side requestor
1711  *  - COOKIE_MSBS
1712  *    Bits 31:0
1713  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1714  *        message with its preceding host->target stats request message.
1715  *    Value: MSBs of the opaque cookie specified by the host-side requestor
1716  */
1717 
1718 struct htt_ext_stats_cfg_hdr {
1719 	u8 msg_type;
1720 	u8 pdev_mask;
1721 	u8 stats_type;
1722 	u8 reserved;
1723 } __packed;
1724 
1725 struct htt_ext_stats_cfg_cmd {
1726 	struct htt_ext_stats_cfg_hdr hdr;
1727 	__le32 cfg_param0;
1728 	__le32 cfg_param1;
1729 	__le32 cfg_param2;
1730 	__le32 cfg_param3;
1731 	__le32 reserved;
1732 	__le32 cookie_lsb;
1733 	__le32 cookie_msb;
1734 } __packed;
1735 
1736 /* htt stats config default params */
1737 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1738 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1739 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1740 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1741 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1742 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1743 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1744 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1745 
1746 /* HTT_DBG_EXT_STATS_PEER_INFO
1747  * PARAMS:
1748  * @config_param0:
1749  *  [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1750  *  [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1751  *  [Bit31 : Bit16] sw_peer_id
1752  * @config_param1:
1753  *  peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1754  *   0 bit htt_peer_stats_cmn_tlv
1755  *   1 bit htt_peer_details_tlv
1756  *   2 bit htt_tx_peer_rate_stats_tlv
1757  *   3 bit htt_rx_peer_rate_stats_tlv
1758  *   4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1759  *   5 bit htt_rx_tid_stats_tlv
1760  *   6 bit htt_msdu_flow_stats_tlv
1761  * @config_param2: [Bit31 : Bit0] mac_addr31to0
1762  * @config_param3: [Bit15 : Bit0] mac_addr47to32
1763  *                [Bit31 : Bit16] reserved
1764  */
1765 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1766 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1767 
1768 /* Used to set different configs to the specified stats type.*/
1769 struct htt_ext_stats_cfg_params {
1770 	u32 cfg0;
1771 	u32 cfg1;
1772 	u32 cfg2;
1773 	u32 cfg3;
1774 };
1775 
1776 enum vdev_stats_offload_timer_duration {
1777 	ATH12K_STATS_TIMER_DUR_500MS = 1,
1778 	ATH12K_STATS_TIMER_DUR_1SEC = 2,
1779 	ATH12K_STATS_TIMER_DUR_2SEC = 3,
1780 };
1781 
ath12k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1782 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1783 {
1784 	memcpy(addr, &addr_l32, 4);
1785 	memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1786 }
1787 
1788 int ath12k_dp_service_srng(struct ath12k_base *ab,
1789 			   struct ath12k_ext_irq_grp *irq_grp,
1790 			   int budget);
1791 int ath12k_dp_htt_connect(struct ath12k_dp *dp);
1792 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif);
1793 void ath12k_dp_free(struct ath12k_base *ab);
1794 int ath12k_dp_alloc(struct ath12k_base *ab);
1795 void ath12k_dp_cc_config(struct ath12k_base *ab);
1796 int ath12k_dp_pdev_alloc(struct ath12k_base *ab);
1797 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab);
1798 void ath12k_dp_pdev_free(struct ath12k_base *ab);
1799 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
1800 				int mac_id, enum hal_ring_type ring_type);
1801 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr);
1802 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr);
1803 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring);
1804 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
1805 			 enum hal_ring_type type, int ring_num,
1806 			 int mac_id, int num_entries);
1807 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
1808 				 struct dp_link_desc_bank *desc_bank,
1809 				 u32 ring_type, struct dp_srng *ring);
1810 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
1811 			      struct dp_link_desc_bank *link_desc_banks,
1812 			      u32 ring_type, struct hal_srng *srng,
1813 			      u32 n_link_desc);
1814 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1815 						  u32 cookie);
1816 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1817 						  u32 desc_id);
1818 #endif
1819