1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <asm/amd_nb.h>
14 #include <linux/acpi.h>
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/limits.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/rtc.h>
26 #include <linux/serio.h>
27 #include <linux/suspend.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30
31 #include "pmc.h"
32
33 /* SMU communication registers */
34 #define AMD_PMC_REGISTER_MESSAGE 0x538
35 #define AMD_PMC_REGISTER_RESPONSE 0x980
36 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC
37
38 /* PMC Scratch Registers */
39 #define AMD_PMC_SCRATCH_REG_CZN 0x94
40 #define AMD_PMC_SCRATCH_REG_YC 0xD14
41
42 /* STB Registers */
43 #define AMD_PMC_STB_PMI_0 0x03E30600
44 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
45 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
46 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
47 #define AMD_PMC_STB_DUMMY_PC 0xC6000007
48
49 /* STB S2D(Spill to DRAM) has different message port offset */
50 #define AMD_S2D_REGISTER_MESSAGE 0xA20
51 #define AMD_S2D_REGISTER_RESPONSE 0xA80
52 #define AMD_S2D_REGISTER_ARGUMENT 0xA88
53
54 /* STB Spill to DRAM Parameters */
55 #define S2D_TELEMETRY_BYTES_MAX 0x100000
56 #define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
57
58 /* Base address of SMU for mapping physical address to virtual address */
59 #define AMD_PMC_MAPPING_SIZE 0x01000
60 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000
61 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8
62 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC
63 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
64 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
65
66 /* SMU Response Codes */
67 #define AMD_PMC_RESULT_OK 0x01
68 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
69 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
70 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
71 #define AMD_PMC_RESULT_FAILED 0xFF
72
73 /* FCH SSC Registers */
74 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
75 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
76 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
77 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
78 #define FCH_SSC_MAPPING_SIZE 0x800
79 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100
80 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000
81
82 /* SMU Message Definations */
83 #define SMU_MSG_GETSMUVERSION 0x02
84 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
85 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
86 #define SMU_MSG_LOG_START 0x06
87 #define SMU_MSG_LOG_RESET 0x07
88 #define SMU_MSG_LOG_DUMP_DATA 0x08
89 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
90
91 #define PMC_MSG_DELAY_MIN_US 50
92 #define RESPONSE_REGISTER_LOOP_MAX 20000
93
94 #define DELAY_MIN_US 2000
95 #define DELAY_MAX_US 3000
96 #define FIFO_SIZE 4096
97
98 enum amd_pmc_def {
99 MSG_TEST = 0x01,
100 MSG_OS_HINT_PCO,
101 MSG_OS_HINT_RN,
102 };
103
104 enum s2d_arg {
105 S2D_TELEMETRY_SIZE = 0x01,
106 S2D_PHYS_ADDR_LOW,
107 S2D_PHYS_ADDR_HIGH,
108 S2D_NUM_SAMPLES,
109 S2D_DRAM_SIZE,
110 };
111
112 struct amd_pmc_bit_map {
113 const char *name;
114 u32 bit_mask;
115 };
116
117 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
118 {"DISPLAY", BIT(0)},
119 {"CPU", BIT(1)},
120 {"GFX", BIT(2)},
121 {"VDD", BIT(3)},
122 {"ACP", BIT(4)},
123 {"VCN", BIT(5)},
124 {"ISP", BIT(6)},
125 {"NBIO", BIT(7)},
126 {"DF", BIT(8)},
127 {"USB3_0", BIT(9)},
128 {"USB3_1", BIT(10)},
129 {"LAPIC", BIT(11)},
130 {"USB3_2", BIT(12)},
131 {"USB3_3", BIT(13)},
132 {"USB3_4", BIT(14)},
133 {"USB4_0", BIT(15)},
134 {"USB4_1", BIT(16)},
135 {"MPM", BIT(17)},
136 {"JPEG", BIT(18)},
137 {"IPU", BIT(19)},
138 {"UMSCH", BIT(20)},
139 {}
140 };
141
142 static bool enable_stb;
143 module_param(enable_stb, bool, 0644);
144 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
145
146 static bool disable_workarounds;
147 module_param(disable_workarounds, bool, 0644);
148 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
149
150 static struct amd_pmc_dev pmc;
151 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
152 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
153 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
154
amd_pmc_reg_read(struct amd_pmc_dev * dev,int reg_offset)155 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
156 {
157 return ioread32(dev->regbase + reg_offset);
158 }
159
amd_pmc_reg_write(struct amd_pmc_dev * dev,int reg_offset,u32 val)160 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
161 {
162 iowrite32(val, dev->regbase + reg_offset);
163 }
164
165 struct smu_metrics {
166 u32 table_version;
167 u32 hint_count;
168 u32 s0i3_last_entry_status;
169 u32 timein_s0i2;
170 u64 timeentering_s0i3_lastcapture;
171 u64 timeentering_s0i3_totaltime;
172 u64 timeto_resume_to_os_lastcapture;
173 u64 timeto_resume_to_os_totaltime;
174 u64 timein_s0i3_lastcapture;
175 u64 timein_s0i3_totaltime;
176 u64 timein_swdrips_lastcapture;
177 u64 timein_swdrips_totaltime;
178 u64 timecondition_notmet_lastcapture[32];
179 u64 timecondition_notmet_totaltime[32];
180 } __packed;
181
amd_pmc_stb_debugfs_open(struct inode * inode,struct file * filp)182 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
183 {
184 struct amd_pmc_dev *dev = filp->f_inode->i_private;
185 u32 size = FIFO_SIZE * sizeof(u32);
186 u32 *buf;
187 int rc;
188
189 buf = kzalloc(size, GFP_KERNEL);
190 if (!buf)
191 return -ENOMEM;
192
193 rc = amd_pmc_read_stb(dev, buf);
194 if (rc) {
195 kfree(buf);
196 return rc;
197 }
198
199 filp->private_data = buf;
200 return rc;
201 }
202
amd_pmc_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)203 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
204 loff_t *pos)
205 {
206 if (!filp->private_data)
207 return -EINVAL;
208
209 return simple_read_from_buffer(buf, size, pos, filp->private_data,
210 FIFO_SIZE * sizeof(u32));
211 }
212
amd_pmc_stb_debugfs_release(struct inode * inode,struct file * filp)213 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
214 {
215 kfree(filp->private_data);
216 return 0;
217 }
218
219 static const struct file_operations amd_pmc_stb_debugfs_fops = {
220 .owner = THIS_MODULE,
221 .open = amd_pmc_stb_debugfs_open,
222 .read = amd_pmc_stb_debugfs_read,
223 .release = amd_pmc_stb_debugfs_release,
224 };
225
amd_pmc_stb_debugfs_open_v2(struct inode * inode,struct file * filp)226 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
227 {
228 struct amd_pmc_dev *dev = filp->f_inode->i_private;
229 u32 *buf, fsize, num_samples, stb_rdptr_offset = 0;
230 int ret;
231
232 /* Write dummy postcode while reading the STB buffer */
233 ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC);
234 if (ret)
235 dev_err(dev->dev, "error writing to STB: %d\n", ret);
236
237 buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
238 if (!buf)
239 return -ENOMEM;
240
241 /* Spill to DRAM num_samples uses separate SMU message port */
242 dev->msg_port = 1;
243
244 /* Get the num_samples to calculate the last push location */
245 ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true);
246 /* Clear msg_port for other SMU operation */
247 dev->msg_port = 0;
248 if (ret) {
249 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret);
250 kfree(buf);
251 return ret;
252 }
253
254 /* Start capturing data from the last push location */
255 if (num_samples > S2D_TELEMETRY_BYTES_MAX) {
256 fsize = S2D_TELEMETRY_BYTES_MAX;
257 stb_rdptr_offset = num_samples - fsize;
258 } else {
259 fsize = num_samples;
260 stb_rdptr_offset = 0;
261 }
262
263 memcpy_fromio(buf, dev->stb_virt_addr + stb_rdptr_offset, fsize);
264 filp->private_data = buf;
265
266 return 0;
267 }
268
amd_pmc_stb_debugfs_read_v2(struct file * filp,char __user * buf,size_t size,loff_t * pos)269 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
270 loff_t *pos)
271 {
272 if (!filp->private_data)
273 return -EINVAL;
274
275 return simple_read_from_buffer(buf, size, pos, filp->private_data,
276 S2D_TELEMETRY_BYTES_MAX);
277 }
278
amd_pmc_stb_debugfs_release_v2(struct inode * inode,struct file * filp)279 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
280 {
281 kfree(filp->private_data);
282 return 0;
283 }
284
285 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
286 .owner = THIS_MODULE,
287 .open = amd_pmc_stb_debugfs_open_v2,
288 .read = amd_pmc_stb_debugfs_read_v2,
289 .release = amd_pmc_stb_debugfs_release_v2,
290 };
291
amd_pmc_get_ip_info(struct amd_pmc_dev * dev)292 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
293 {
294 switch (dev->cpu_id) {
295 case AMD_CPU_ID_PCO:
296 case AMD_CPU_ID_RN:
297 case AMD_CPU_ID_YC:
298 case AMD_CPU_ID_CB:
299 dev->num_ips = 12;
300 dev->s2d_msg_id = 0xBE;
301 break;
302 case AMD_CPU_ID_PS:
303 dev->num_ips = 21;
304 dev->s2d_msg_id = 0x85;
305 break;
306 }
307 }
308
amd_pmc_setup_smu_logging(struct amd_pmc_dev * dev)309 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
310 {
311 if (dev->cpu_id == AMD_CPU_ID_PCO) {
312 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
313 return -EINVAL;
314 }
315
316 /* Get Active devices list from SMU */
317 if (!dev->active_ips)
318 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
319
320 /* Get dram address */
321 if (!dev->smu_virt_addr) {
322 u32 phys_addr_low, phys_addr_hi;
323 u64 smu_phys_addr;
324
325 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
326 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
327 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
328
329 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
330 sizeof(struct smu_metrics));
331 if (!dev->smu_virt_addr)
332 return -ENOMEM;
333 }
334
335 /* Start the logging */
336 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
337 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
338
339 return 0;
340 }
341
get_metrics_table(struct amd_pmc_dev * pdev,struct smu_metrics * table)342 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
343 {
344 if (!pdev->smu_virt_addr) {
345 int ret = amd_pmc_setup_smu_logging(pdev);
346
347 if (ret)
348 return ret;
349 }
350
351 if (pdev->cpu_id == AMD_CPU_ID_PCO)
352 return -ENODEV;
353 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
354 return 0;
355 }
356
amd_pmc_validate_deepest(struct amd_pmc_dev * pdev)357 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
358 {
359 struct smu_metrics table;
360
361 if (get_metrics_table(pdev, &table))
362 return;
363
364 if (!table.s0i3_last_entry_status)
365 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
366 pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
367 table.timein_s0i3_lastcapture : 0);
368 }
369
amd_pmc_get_smu_version(struct amd_pmc_dev * dev)370 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
371 {
372 int rc;
373 u32 val;
374
375 if (dev->cpu_id == AMD_CPU_ID_PCO)
376 return -ENODEV;
377
378 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
379 if (rc)
380 return rc;
381
382 dev->smu_program = (val >> 24) & GENMASK(7, 0);
383 dev->major = (val >> 16) & GENMASK(7, 0);
384 dev->minor = (val >> 8) & GENMASK(7, 0);
385 dev->rev = (val >> 0) & GENMASK(7, 0);
386
387 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
388 dev->smu_program, dev->major, dev->minor, dev->rev);
389
390 return 0;
391 }
392
smu_fw_version_show(struct device * d,struct device_attribute * attr,char * buf)393 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
394 char *buf)
395 {
396 struct amd_pmc_dev *dev = dev_get_drvdata(d);
397
398 if (!dev->major) {
399 int rc = amd_pmc_get_smu_version(dev);
400
401 if (rc)
402 return rc;
403 }
404 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
405 }
406
smu_program_show(struct device * d,struct device_attribute * attr,char * buf)407 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
408 char *buf)
409 {
410 struct amd_pmc_dev *dev = dev_get_drvdata(d);
411
412 if (!dev->major) {
413 int rc = amd_pmc_get_smu_version(dev);
414
415 if (rc)
416 return rc;
417 }
418 return sysfs_emit(buf, "%u\n", dev->smu_program);
419 }
420
421 static DEVICE_ATTR_RO(smu_fw_version);
422 static DEVICE_ATTR_RO(smu_program);
423
pmc_attr_is_visible(struct kobject * kobj,struct attribute * attr,int idx)424 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
425 {
426 struct device *dev = kobj_to_dev(kobj);
427 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
428
429 if (pdev->cpu_id == AMD_CPU_ID_PCO)
430 return 0;
431 return 0444;
432 }
433
434 static struct attribute *pmc_attrs[] = {
435 &dev_attr_smu_fw_version.attr,
436 &dev_attr_smu_program.attr,
437 NULL,
438 };
439
440 static struct attribute_group pmc_attr_group = {
441 .attrs = pmc_attrs,
442 .is_visible = pmc_attr_is_visible,
443 };
444
445 static const struct attribute_group *pmc_groups[] = {
446 &pmc_attr_group,
447 NULL,
448 };
449
smu_fw_info_show(struct seq_file * s,void * unused)450 static int smu_fw_info_show(struct seq_file *s, void *unused)
451 {
452 struct amd_pmc_dev *dev = s->private;
453 struct smu_metrics table;
454 int idx;
455
456 if (get_metrics_table(dev, &table))
457 return -EINVAL;
458
459 seq_puts(s, "\n=== SMU Statistics ===\n");
460 seq_printf(s, "Table Version: %d\n", table.table_version);
461 seq_printf(s, "Hint Count: %d\n", table.hint_count);
462 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
463 "Unknown/Fail");
464 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
465 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
466 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
467 table.timeto_resume_to_os_lastcapture);
468
469 seq_puts(s, "\n=== Active time (in us) ===\n");
470 for (idx = 0 ; idx < dev->num_ips ; idx++) {
471 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
472 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
473 table.timecondition_notmet_lastcapture[idx]);
474 }
475
476 return 0;
477 }
478 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
479
s0ix_stats_show(struct seq_file * s,void * unused)480 static int s0ix_stats_show(struct seq_file *s, void *unused)
481 {
482 struct amd_pmc_dev *dev = s->private;
483 u64 entry_time, exit_time, residency;
484
485 /* Use FCH registers to get the S0ix stats */
486 if (!dev->fch_virt_addr) {
487 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
488 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
489 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
490
491 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
492 if (!dev->fch_virt_addr)
493 return -ENOMEM;
494 }
495
496 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
497 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
498
499 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
500 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
501
502 /* It's in 48MHz. We need to convert it */
503 residency = exit_time - entry_time;
504 do_div(residency, 48);
505
506 seq_puts(s, "=== S0ix statistics ===\n");
507 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
508 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
509 seq_printf(s, "Residency Time: %lld\n", residency);
510
511 return 0;
512 }
513 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
514
amd_pmc_idlemask_read(struct amd_pmc_dev * pdev,struct device * dev,struct seq_file * s)515 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
516 struct seq_file *s)
517 {
518 u32 val;
519 int rc;
520
521 switch (pdev->cpu_id) {
522 case AMD_CPU_ID_CZN:
523 /* we haven't yet read SMU version */
524 if (!pdev->major) {
525 rc = amd_pmc_get_smu_version(pdev);
526 if (rc)
527 return rc;
528 }
529 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
530 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
531 else
532 return -EINVAL;
533 break;
534 case AMD_CPU_ID_YC:
535 case AMD_CPU_ID_CB:
536 case AMD_CPU_ID_PS:
537 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 if (dev)
544 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
545
546 if (s)
547 seq_printf(s, "SMU idlemask : 0x%x\n", val);
548
549 return 0;
550 }
551
amd_pmc_idlemask_show(struct seq_file * s,void * unused)552 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
553 {
554 return amd_pmc_idlemask_read(s->private, NULL, s);
555 }
556 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
557
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)558 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
559 {
560 debugfs_remove_recursive(dev->dbgfs_dir);
561 }
562
amd_pmc_is_stb_supported(struct amd_pmc_dev * dev)563 static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev)
564 {
565 switch (dev->cpu_id) {
566 case AMD_CPU_ID_YC:
567 case AMD_CPU_ID_CB:
568 case AMD_CPU_ID_PS:
569 return true;
570 default:
571 return false;
572 }
573 }
574
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)575 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
576 {
577 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
578 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
579 &smu_fw_info_fops);
580 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
581 &s0ix_stats_fops);
582 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
583 &amd_pmc_idlemask_fops);
584 /* Enable STB only when the module_param is set */
585 if (enable_stb) {
586 if (amd_pmc_is_stb_supported(dev))
587 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
588 &amd_pmc_stb_debugfs_fops_v2);
589 else
590 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
591 &amd_pmc_stb_debugfs_fops);
592 }
593 }
594
amd_pmc_dump_registers(struct amd_pmc_dev * dev)595 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
596 {
597 u32 value, message, argument, response;
598
599 if (dev->msg_port) {
600 message = AMD_S2D_REGISTER_MESSAGE;
601 argument = AMD_S2D_REGISTER_ARGUMENT;
602 response = AMD_S2D_REGISTER_RESPONSE;
603 } else {
604 message = AMD_PMC_REGISTER_MESSAGE;
605 argument = AMD_PMC_REGISTER_ARGUMENT;
606 response = AMD_PMC_REGISTER_RESPONSE;
607 }
608
609 value = amd_pmc_reg_read(dev, response);
610 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
611
612 value = amd_pmc_reg_read(dev, argument);
613 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value);
614
615 value = amd_pmc_reg_read(dev, message);
616 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value);
617 }
618
amd_pmc_send_cmd(struct amd_pmc_dev * dev,u32 arg,u32 * data,u8 msg,bool ret)619 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
620 {
621 int rc;
622 u32 val, message, argument, response;
623
624 mutex_lock(&dev->lock);
625
626 if (dev->msg_port) {
627 message = AMD_S2D_REGISTER_MESSAGE;
628 argument = AMD_S2D_REGISTER_ARGUMENT;
629 response = AMD_S2D_REGISTER_RESPONSE;
630 } else {
631 message = AMD_PMC_REGISTER_MESSAGE;
632 argument = AMD_PMC_REGISTER_ARGUMENT;
633 response = AMD_PMC_REGISTER_RESPONSE;
634 }
635
636 /* Wait until we get a valid response */
637 rc = readx_poll_timeout(ioread32, dev->regbase + response,
638 val, val != 0, PMC_MSG_DELAY_MIN_US,
639 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
640 if (rc) {
641 dev_err(dev->dev, "failed to talk to SMU\n");
642 goto out_unlock;
643 }
644
645 /* Write zero to response register */
646 amd_pmc_reg_write(dev, response, 0);
647
648 /* Write argument into response register */
649 amd_pmc_reg_write(dev, argument, arg);
650
651 /* Write message ID to message ID register */
652 amd_pmc_reg_write(dev, message, msg);
653
654 /* Wait until we get a valid response */
655 rc = readx_poll_timeout(ioread32, dev->regbase + response,
656 val, val != 0, PMC_MSG_DELAY_MIN_US,
657 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
658 if (rc) {
659 dev_err(dev->dev, "SMU response timed out\n");
660 goto out_unlock;
661 }
662
663 switch (val) {
664 case AMD_PMC_RESULT_OK:
665 if (ret) {
666 /* PMFW may take longer time to return back the data */
667 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
668 *data = amd_pmc_reg_read(dev, argument);
669 }
670 break;
671 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
672 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
673 rc = -EBUSY;
674 goto out_unlock;
675 case AMD_PMC_RESULT_CMD_UNKNOWN:
676 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
677 rc = -EINVAL;
678 goto out_unlock;
679 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
680 case AMD_PMC_RESULT_FAILED:
681 default:
682 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
683 rc = -EIO;
684 goto out_unlock;
685 }
686
687 out_unlock:
688 mutex_unlock(&dev->lock);
689 amd_pmc_dump_registers(dev);
690 return rc;
691 }
692
amd_pmc_get_os_hint(struct amd_pmc_dev * dev)693 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
694 {
695 switch (dev->cpu_id) {
696 case AMD_CPU_ID_PCO:
697 return MSG_OS_HINT_PCO;
698 case AMD_CPU_ID_RN:
699 case AMD_CPU_ID_YC:
700 case AMD_CPU_ID_CB:
701 case AMD_CPU_ID_PS:
702 return MSG_OS_HINT_RN;
703 }
704 return -EINVAL;
705 }
706
amd_pmc_wa_irq1(struct amd_pmc_dev * pdev)707 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
708 {
709 struct device *d;
710 int rc;
711
712 /* cezanne platform firmware has a fix in 64.66.0 */
713 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
714 if (!pdev->major) {
715 rc = amd_pmc_get_smu_version(pdev);
716 if (rc)
717 return rc;
718 }
719
720 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
721 return 0;
722 }
723
724 d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
725 if (!d)
726 return 0;
727 if (device_may_wakeup(d)) {
728 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
729 disable_irq_wake(1);
730 device_set_wakeup_enable(d, false);
731 }
732 put_device(d);
733
734 return 0;
735 }
736
amd_pmc_verify_czn_rtc(struct amd_pmc_dev * pdev,u32 * arg)737 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
738 {
739 struct rtc_device *rtc_device;
740 time64_t then, now, duration;
741 struct rtc_wkalrm alarm;
742 struct rtc_time tm;
743 int rc;
744
745 /* we haven't yet read SMU version */
746 if (!pdev->major) {
747 rc = amd_pmc_get_smu_version(pdev);
748 if (rc)
749 return rc;
750 }
751
752 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
753 return 0;
754
755 rtc_device = rtc_class_open("rtc0");
756 if (!rtc_device)
757 return 0;
758 rc = rtc_read_alarm(rtc_device, &alarm);
759 if (rc)
760 return rc;
761 if (!alarm.enabled) {
762 dev_dbg(pdev->dev, "alarm not enabled\n");
763 return 0;
764 }
765 rc = rtc_read_time(rtc_device, &tm);
766 if (rc)
767 return rc;
768 then = rtc_tm_to_time64(&alarm.time);
769 now = rtc_tm_to_time64(&tm);
770 duration = then-now;
771
772 /* in the past */
773 if (then < now)
774 return 0;
775
776 /* will be stored in upper 16 bits of s0i3 hint argument,
777 * so timer wakeup from s0i3 is limited to ~18 hours or less
778 */
779 if (duration <= 4 || duration > U16_MAX)
780 return -EINVAL;
781
782 *arg |= (duration << 16);
783 rc = rtc_alarm_irq_enable(rtc_device, 0);
784 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
785
786 return rc;
787 }
788
amd_pmc_s2idle_prepare(void)789 static void amd_pmc_s2idle_prepare(void)
790 {
791 struct amd_pmc_dev *pdev = &pmc;
792 int rc;
793 u8 msg;
794 u32 arg = 1;
795
796 /* Reset and Start SMU logging - to monitor the s0i3 stats */
797 amd_pmc_setup_smu_logging(pdev);
798
799 /* Activate CZN specific platform bug workarounds */
800 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
801 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
802 if (rc) {
803 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
804 return;
805 }
806 }
807
808 msg = amd_pmc_get_os_hint(pdev);
809 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
810 if (rc) {
811 dev_err(pdev->dev, "suspend failed: %d\n", rc);
812 return;
813 }
814
815 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
816 if (rc)
817 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
818 }
819
amd_pmc_s2idle_check(void)820 static void amd_pmc_s2idle_check(void)
821 {
822 struct amd_pmc_dev *pdev = &pmc;
823 struct smu_metrics table;
824 int rc;
825
826 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
827 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
828 table.s0i3_last_entry_status)
829 usleep_range(10000, 20000);
830
831 /* Dump the IdleMask before we add to the STB */
832 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
833
834 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
835 if (rc)
836 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
837 }
838
amd_pmc_dump_data(struct amd_pmc_dev * pdev)839 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
840 {
841 if (pdev->cpu_id == AMD_CPU_ID_PCO)
842 return -ENODEV;
843
844 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
845 }
846
amd_pmc_s2idle_restore(void)847 static void amd_pmc_s2idle_restore(void)
848 {
849 struct amd_pmc_dev *pdev = &pmc;
850 int rc;
851 u8 msg;
852
853 msg = amd_pmc_get_os_hint(pdev);
854 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
855 if (rc)
856 dev_err(pdev->dev, "resume failed: %d\n", rc);
857
858 /* Let SMU know that we are looking for stats */
859 amd_pmc_dump_data(pdev);
860
861 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
862 if (rc)
863 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
864
865 /* Notify on failed entry */
866 amd_pmc_validate_deepest(pdev);
867
868 amd_pmc_process_restore_quirks(pdev);
869 }
870
871 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
872 .prepare = amd_pmc_s2idle_prepare,
873 .check = amd_pmc_s2idle_check,
874 .restore = amd_pmc_s2idle_restore,
875 };
876
amd_pmc_suspend_handler(struct device * dev)877 static int amd_pmc_suspend_handler(struct device *dev)
878 {
879 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
880
881 if (pdev->disable_8042_wakeup && !disable_workarounds) {
882 int rc = amd_pmc_wa_irq1(pdev);
883
884 if (rc) {
885 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
886 return rc;
887 }
888 }
889
890 return 0;
891 }
892
893 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
894
895 static const struct pci_device_id pmc_pci_ids[] = {
896 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
897 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
898 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
899 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
900 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
901 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
902 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
903 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
904 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
905 { }
906 };
907
amd_pmc_s2d_init(struct amd_pmc_dev * dev)908 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
909 {
910 u32 phys_addr_low, phys_addr_hi;
911 u64 stb_phys_addr;
912 u32 size = 0;
913 int ret;
914
915 /* Spill to DRAM feature uses separate SMU message port */
916 dev->msg_port = 1;
917
918 /* Get num of IP blocks within the SoC */
919 amd_pmc_get_ip_info(dev);
920
921 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true);
922 if (size != S2D_TELEMETRY_BYTES_MAX)
923 return -EIO;
924
925 /* Get DRAM size */
926 ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true);
927 if (ret || !dev->dram_size)
928 dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
929
930 /* Get STB DRAM address */
931 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true);
932 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true);
933
934 if (!phys_addr_hi && !phys_addr_low) {
935 dev_err(dev->dev, "STB is not enabled on the system; disable enable_stb or contact system vendor\n");
936 return -EINVAL;
937 }
938
939 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
940
941 /* Clear msg_port for other SMU operation */
942 dev->msg_port = 0;
943
944 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
945 if (!dev->stb_virt_addr)
946 return -ENOMEM;
947
948 return 0;
949 }
950
amd_pmc_write_stb(struct amd_pmc_dev * dev,u32 data)951 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
952 {
953 int err;
954
955 err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);
956 if (err) {
957 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);
958 return pcibios_err_to_errno(err);
959 }
960
961 return 0;
962 }
963
amd_pmc_read_stb(struct amd_pmc_dev * dev,u32 * buf)964 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
965 {
966 int i, err;
967
968 for (i = 0; i < FIFO_SIZE; i++) {
969 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);
970 if (err) {
971 dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);
972 return pcibios_err_to_errno(err);
973 }
974 }
975
976 return 0;
977 }
978
amd_pmc_probe(struct platform_device * pdev)979 static int amd_pmc_probe(struct platform_device *pdev)
980 {
981 struct amd_pmc_dev *dev = &pmc;
982 struct pci_dev *rdev;
983 u32 base_addr_lo, base_addr_hi;
984 u64 base_addr;
985 int err;
986 u32 val;
987
988 dev->dev = &pdev->dev;
989
990 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
991 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
992 err = -ENODEV;
993 goto err_pci_dev_put;
994 }
995
996 dev->cpu_id = rdev->device;
997
998 if (dev->cpu_id == AMD_CPU_ID_SP) {
999 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
1000 err = -ENODEV;
1001 goto err_pci_dev_put;
1002 }
1003
1004 dev->rdev = rdev;
1005 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
1006 if (err) {
1007 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
1008 err = pcibios_err_to_errno(err);
1009 goto err_pci_dev_put;
1010 }
1011
1012 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
1013
1014 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
1015 if (err) {
1016 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
1017 err = pcibios_err_to_errno(err);
1018 goto err_pci_dev_put;
1019 }
1020
1021 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
1022 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
1023
1024 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
1025 AMD_PMC_MAPPING_SIZE);
1026 if (!dev->regbase) {
1027 err = -ENOMEM;
1028 goto err_pci_dev_put;
1029 }
1030
1031 mutex_init(&dev->lock);
1032
1033 if (enable_stb && amd_pmc_is_stb_supported(dev)) {
1034 err = amd_pmc_s2d_init(dev);
1035 if (err)
1036 goto err_pci_dev_put;
1037 }
1038
1039 platform_set_drvdata(pdev, dev);
1040 if (IS_ENABLED(CONFIG_SUSPEND)) {
1041 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
1042 if (err)
1043 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
1044 if (!disable_workarounds)
1045 amd_pmc_quirks_init(dev);
1046 }
1047
1048 amd_pmc_dbgfs_register(dev);
1049 pm_report_max_hw_sleep(U64_MAX);
1050 return 0;
1051
1052 err_pci_dev_put:
1053 pci_dev_put(rdev);
1054 return err;
1055 }
1056
amd_pmc_remove(struct platform_device * pdev)1057 static void amd_pmc_remove(struct platform_device *pdev)
1058 {
1059 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1060
1061 if (IS_ENABLED(CONFIG_SUSPEND))
1062 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1063 amd_pmc_dbgfs_unregister(dev);
1064 pci_dev_put(dev->rdev);
1065 mutex_destroy(&dev->lock);
1066 }
1067
1068 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1069 {"AMDI0005", 0},
1070 {"AMDI0006", 0},
1071 {"AMDI0007", 0},
1072 {"AMDI0008", 0},
1073 {"AMDI0009", 0},
1074 {"AMDI000A", 0},
1075 {"AMD0004", 0},
1076 {"AMD0005", 0},
1077 { }
1078 };
1079 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1080
1081 static struct platform_driver amd_pmc_driver = {
1082 .driver = {
1083 .name = "amd_pmc",
1084 .acpi_match_table = amd_pmc_acpi_ids,
1085 .dev_groups = pmc_groups,
1086 .pm = pm_sleep_ptr(&amd_pmc_pm),
1087 },
1088 .probe = amd_pmc_probe,
1089 .remove_new = amd_pmc_remove,
1090 };
1091 module_platform_driver(amd_pmc_driver);
1092
1093 MODULE_LICENSE("GPL v2");
1094 MODULE_DESCRIPTION("AMD PMC Driver");
1095