1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 #include "../mt76_connac_mcu.h" 8 9 enum { 10 MCU_ATE_SET_TRX = 0x1, 11 MCU_ATE_SET_FREQ_OFFSET = 0xa, 12 MCU_ATE_SET_SLOT_TIME = 0x13, 13 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 14 }; 15 16 struct mt7915_mcu_thermal_ctrl { 17 u8 ctrl_id; 18 u8 band_idx; 19 union { 20 struct { 21 u8 protect_type; /* 1: duty admit, 2: radio off */ 22 u8 trigger_type; /* 0: low, 1: high */ 23 } __packed type; 24 struct { 25 u8 duty_level; /* level 0~3 */ 26 u8 duty_cycle; 27 } __packed duty; 28 }; 29 } __packed; 30 31 struct mt7915_mcu_thermal_notify { 32 struct mt76_connac2_mcu_rxd rxd; 33 34 struct mt7915_mcu_thermal_ctrl ctrl; 35 __le32 temperature; 36 u8 rsv[8]; 37 } __packed; 38 39 struct mt7915_mcu_csa_notify { 40 struct mt76_connac2_mcu_rxd rxd; 41 42 u8 omac_idx; 43 u8 csa_count; 44 u8 band_idx; 45 u8 rsv; 46 } __packed; 47 48 struct mt7915_mcu_bcc_notify { 49 struct mt76_connac2_mcu_rxd rxd; 50 51 u8 band_idx; 52 u8 omac_idx; 53 u8 cca_count; 54 u8 rsv; 55 } __packed; 56 57 struct mt7915_mcu_rdd_report { 58 struct mt76_connac2_mcu_rxd rxd; 59 60 u8 band_idx; 61 u8 long_detected; 62 u8 constant_prf_detected; 63 u8 staggered_prf_detected; 64 u8 radar_type_idx; 65 u8 periodic_pulse_num; 66 u8 long_pulse_num; 67 u8 hw_pulse_num; 68 69 u8 out_lpn; 70 u8 out_spn; 71 u8 out_crpn; 72 u8 out_crpw; 73 u8 out_crbn; 74 u8 out_stgpn; 75 u8 out_stgpw; 76 77 u8 rsv; 78 79 __le32 out_pri_const; 80 __le32 out_pri_stg[3]; 81 82 struct { 83 __le32 start; 84 __le16 pulse_width; 85 __le16 pulse_power; 86 u8 mdrdy_flag; 87 u8 rsv[3]; 88 } long_pulse[32]; 89 90 struct { 91 __le32 start; 92 __le16 pulse_width; 93 __le16 pulse_power; 94 u8 mdrdy_flag; 95 u8 rsv[3]; 96 } periodic_pulse[32]; 97 98 struct { 99 __le32 start; 100 __le16 pulse_width; 101 __le16 pulse_power; 102 u8 sc_pass; 103 u8 sw_reset; 104 u8 mdrdy_flag; 105 u8 tx_active; 106 } hw_pulse[32]; 107 } __packed; 108 109 struct mt7915_mcu_background_chain_ctrl { 110 u8 chan; /* primary channel */ 111 u8 central_chan; /* central channel */ 112 u8 bw; 113 u8 tx_stream; 114 u8 rx_stream; 115 116 u8 monitor_chan; /* monitor channel */ 117 u8 monitor_central_chan;/* monitor central channel */ 118 u8 monitor_bw; 119 u8 monitor_tx_stream; 120 u8 monitor_rx_stream; 121 122 u8 scan_mode; /* 0: ScanStop 123 * 1: ScanStart 124 * 2: ScanRunning 125 */ 126 u8 band_idx; /* DBDC */ 127 u8 monitor_scan_type; 128 u8 band; /* 0: 2.4GHz, 1: 5GHz */ 129 u8 rsv[2]; 130 } __packed; 131 132 struct mt7915_mcu_sr_ctrl { 133 u8 action; 134 u8 argnum; 135 u8 band_idx; 136 u8 status; 137 u8 drop_ta_idx; 138 u8 sta_idx; /* 256 sta */ 139 u8 rsv[2]; 140 __le32 val; 141 } __packed; 142 143 struct mt7915_mcu_eeprom { 144 u8 buffer_mode; 145 u8 format; 146 __le16 len; 147 } __packed; 148 149 struct mt7915_mcu_eeprom_info { 150 __le32 addr; 151 __le32 valid; 152 u8 data[16]; 153 } __packed; 154 155 struct mt7915_mcu_phy_rx_info { 156 u8 category; 157 u8 rate; 158 u8 mode; 159 u8 nsts; 160 u8 gi; 161 u8 coding; 162 u8 stbc; 163 u8 bw; 164 }; 165 166 struct mt7915_mcu_mib { 167 __le32 band; 168 __le32 offs; 169 __le64 data; 170 } __packed; 171 172 enum mt7915_chan_mib_offs { 173 /* mt7915 */ 174 MIB_TX_TIME = 81, 175 MIB_RX_TIME, 176 MIB_OBSS_AIRTIME = 86, 177 MIB_NON_WIFI_TIME, 178 MIB_TXOP_INIT_COUNT, 179 180 /* mt7916 */ 181 MIB_TX_TIME_V2 = 6, 182 MIB_RX_TIME_V2 = 8, 183 MIB_OBSS_AIRTIME_V2 = 490, 184 MIB_NON_WIFI_TIME_V2 185 }; 186 187 struct mt7915_mcu_txpower_sku { 188 u8 format_id; 189 u8 limit_type; 190 u8 band_idx; 191 s8 txpower_sku[MT7915_SKU_RATE_NUM]; 192 } __packed; 193 194 struct edca { 195 u8 queue; 196 u8 set; 197 u8 aifs; 198 u8 cw_min; 199 __le16 cw_max; 200 __le16 txop; 201 }; 202 203 struct mt7915_mcu_tx { 204 u8 total; 205 u8 action; 206 u8 valid; 207 u8 mode; 208 209 struct edca edca[IEEE80211_NUM_ACS]; 210 } __packed; 211 212 struct mt7915_mcu_muru_stats { 213 __le32 event_id; 214 struct { 215 __le32 cck_cnt; 216 __le32 ofdm_cnt; 217 __le32 htmix_cnt; 218 __le32 htgf_cnt; 219 __le32 vht_su_cnt; 220 __le32 vht_2mu_cnt; 221 __le32 vht_3mu_cnt; 222 __le32 vht_4mu_cnt; 223 __le32 he_su_cnt; 224 __le32 he_ext_su_cnt; 225 __le32 he_2ru_cnt; 226 __le32 he_2mu_cnt; 227 __le32 he_3ru_cnt; 228 __le32 he_3mu_cnt; 229 __le32 he_4ru_cnt; 230 __le32 he_4mu_cnt; 231 __le32 he_5to8ru_cnt; 232 __le32 he_9to16ru_cnt; 233 __le32 he_gtr16ru_cnt; 234 } dl; 235 236 struct { 237 __le32 hetrig_su_cnt; 238 __le32 hetrig_2ru_cnt; 239 __le32 hetrig_3ru_cnt; 240 __le32 hetrig_4ru_cnt; 241 __le32 hetrig_5to8ru_cnt; 242 __le32 hetrig_9to16ru_cnt; 243 __le32 hetrig_gtr16ru_cnt; 244 __le32 hetrig_2mu_cnt; 245 __le32 hetrig_3mu_cnt; 246 __le32 hetrig_4mu_cnt; 247 } ul; 248 }; 249 250 #define WMM_AIFS_SET BIT(0) 251 #define WMM_CW_MIN_SET BIT(1) 252 #define WMM_CW_MAX_SET BIT(2) 253 #define WMM_TXOP_SET BIT(3) 254 #define WMM_PARAM_SET GENMASK(3, 0) 255 256 enum { 257 MCU_FW_LOG_WM, 258 MCU_FW_LOG_WA, 259 MCU_FW_LOG_TO_HOST, 260 }; 261 262 enum { 263 MCU_TWT_AGRT_ADD, 264 MCU_TWT_AGRT_MODIFY, 265 MCU_TWT_AGRT_DELETE, 266 MCU_TWT_AGRT_TEARDOWN, 267 MCU_TWT_AGRT_GET_TSF, 268 }; 269 270 enum { 271 MCU_WA_PARAM_CMD_QUERY, 272 MCU_WA_PARAM_CMD_SET, 273 MCU_WA_PARAM_CMD_CAPABILITY, 274 MCU_WA_PARAM_CMD_DEBUG, 275 }; 276 277 enum { 278 MCU_WA_PARAM_PDMA_RX = 0x04, 279 MCU_WA_PARAM_CPU_UTIL = 0x0b, 280 MCU_WA_PARAM_RED = 0x0e, 281 MCU_WA_PARAM_RED_SETTING = 0x40, 282 }; 283 284 enum mcu_mmps_mode { 285 MCU_MMPS_STATIC, 286 MCU_MMPS_DYNAMIC, 287 MCU_MMPS_RSV, 288 MCU_MMPS_DISABLE, 289 }; 290 291 struct bss_info_bmc_rate { 292 __le16 tag; 293 __le16 len; 294 __le16 bc_trans; 295 __le16 mc_trans; 296 u8 short_preamble; 297 u8 rsv[7]; 298 } __packed; 299 300 struct bss_info_ra { 301 __le16 tag; 302 __le16 len; 303 u8 op_mode; 304 u8 adhoc_en; 305 u8 short_preamble; 306 u8 tx_streams; 307 u8 rx_streams; 308 u8 algo; 309 u8 force_sgi; 310 u8 force_gf; 311 u8 ht_mode; 312 u8 has_20_sta; /* Check if any sta support GF. */ 313 u8 bss_width_trigger_events; 314 u8 vht_nss_cap; 315 u8 vht_bw_signal; /* not use */ 316 u8 vht_force_sgi; /* not use */ 317 u8 se_off; 318 u8 antenna_idx; 319 u8 train_up_rule; 320 u8 rsv[3]; 321 unsigned short train_up_high_thres; 322 short train_up_rule_rssi; 323 unsigned short low_traffic_thres; 324 __le16 max_phyrate; 325 __le32 phy_cap; 326 __le32 interval; 327 __le32 fast_interval; 328 } __packed; 329 330 struct bss_info_hw_amsdu { 331 __le16 tag; 332 __le16 len; 333 __le32 cmp_bitmap_0; 334 __le32 cmp_bitmap_1; 335 __le16 trig_thres; 336 u8 enable; 337 u8 rsv; 338 } __packed; 339 340 struct bss_info_color { 341 __le16 tag; 342 __le16 len; 343 u8 disable; 344 u8 color; 345 u8 rsv[2]; 346 } __packed; 347 348 struct bss_info_he { 349 __le16 tag; 350 __le16 len; 351 u8 he_pe_duration; 352 u8 vht_op_info_present; 353 __le16 he_rts_thres; 354 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 355 u8 rsv[6]; 356 } __packed; 357 358 struct bss_info_bcn { 359 __le16 tag; 360 __le16 len; 361 u8 ver; 362 u8 enable; 363 __le16 sub_ntlv; 364 } __packed __aligned(4); 365 366 struct bss_info_bcn_cntdwn { 367 __le16 tag; 368 __le16 len; 369 u8 cnt; 370 u8 rsv[3]; 371 } __packed __aligned(4); 372 373 struct bss_info_bcn_mbss { 374 #define MAX_BEACON_NUM 32 375 __le16 tag; 376 __le16 len; 377 __le32 bitmap; 378 __le16 offset[MAX_BEACON_NUM]; 379 u8 rsv[8]; 380 } __packed __aligned(4); 381 382 struct bss_info_bcn_cont { 383 __le16 tag; 384 __le16 len; 385 __le16 tim_ofs; 386 __le16 csa_ofs; 387 __le16 bcc_ofs; 388 __le16 pkt_len; 389 } __packed __aligned(4); 390 391 struct bss_info_inband_discovery { 392 __le16 tag; 393 __le16 len; 394 u8 tx_type; 395 u8 tx_mode; 396 u8 tx_interval; 397 u8 enable; 398 __le16 rsv; 399 __le16 prob_rsp_len; 400 } __packed __aligned(4); 401 402 enum { 403 BSS_INFO_BCN_CSA, 404 BSS_INFO_BCN_BCC, 405 BSS_INFO_BCN_MBSSID, 406 BSS_INFO_BCN_CONTENT, 407 BSS_INFO_BCN_DISCOV, 408 BSS_INFO_BCN_MAX 409 }; 410 411 enum { 412 RATE_PARAM_FIXED = 3, 413 RATE_PARAM_MMPS_UPDATE = 5, 414 RATE_PARAM_FIXED_HE_LTF = 7, 415 RATE_PARAM_FIXED_MCS, 416 RATE_PARAM_FIXED_GI = 11, 417 RATE_PARAM_AUTO = 20, 418 RATE_PARAM_SPE_UPDATE = 22, 419 }; 420 421 #define RATE_CFG_MCS GENMASK(3, 0) 422 #define RATE_CFG_NSS GENMASK(7, 4) 423 #define RATE_CFG_GI GENMASK(11, 8) 424 #define RATE_CFG_BW GENMASK(15, 12) 425 #define RATE_CFG_STBC GENMASK(19, 16) 426 #define RATE_CFG_LDPC GENMASK(23, 20) 427 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 428 #define RATE_CFG_HE_LTF GENMASK(31, 28) 429 430 enum { 431 TX_POWER_LIMIT_ENABLE, 432 TX_POWER_LIMIT_TABLE = 0x4, 433 TX_POWER_LIMIT_INFO = 0x7, 434 TX_POWER_LIMIT_FRAME = 0x11, 435 TX_POWER_LIMIT_FRAME_MIN = 0x12, 436 }; 437 438 enum { 439 SPR_ENABLE = 0x1, 440 SPR_ENABLE_SD = 0x3, 441 SPR_ENABLE_MODE = 0x5, 442 SPR_ENABLE_DPD = 0x23, 443 SPR_ENABLE_TX = 0x25, 444 SPR_SET_SRG_BITMAP = 0x80, 445 SPR_SET_PARAM = 0xc2, 446 SPR_SET_SIGA = 0xdc, 447 }; 448 449 enum { 450 THERMAL_PROTECT_PARAMETER_CTRL, 451 THERMAL_PROTECT_BASIC_INFO, 452 THERMAL_PROTECT_ENABLE, 453 THERMAL_PROTECT_DISABLE, 454 THERMAL_PROTECT_DUTY_CONFIG, 455 THERMAL_PROTECT_MECH_INFO, 456 THERMAL_PROTECT_DUTY_INFO, 457 THERMAL_PROTECT_STATE_ACT, 458 }; 459 460 enum { 461 MT_BF_SOUNDING_ON = 1, 462 MT_BF_TYPE_UPDATE = 20, 463 MT_BF_MODULE_UPDATE = 25 464 }; 465 466 enum { 467 MURU_SET_ARB_OP_MODE = 14, 468 MURU_SET_PLATFORM_TYPE = 25, 469 }; 470 471 enum { 472 MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, 473 MURU_PLATFORM_TYPE_PERF_LEVEL_2, 474 }; 475 476 /* tx cmd tx statistics */ 477 enum { 478 MURU_SET_TXC_TX_STATS_EN = 150, 479 MURU_GET_TXC_TX_STATS = 151, 480 }; 481 482 enum { 483 SER_QUERY, 484 /* recovery */ 485 SER_SET_RECOVER_L1, 486 SER_SET_RECOVER_L2, 487 SER_SET_RECOVER_L3_RX_ABORT, 488 SER_SET_RECOVER_L3_TX_ABORT, 489 SER_SET_RECOVER_L3_TX_DISABLE, 490 SER_SET_RECOVER_L3_BF, 491 SER_SET_RECOVER_FULL, 492 SER_SET_SYSTEM_ASSERT, 493 /* action */ 494 SER_ENABLE = 2, 495 SER_RECOVER 496 }; 497 498 #define MT7915_MAX_BEACON_SIZE 1308 499 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 500 sizeof(struct bss_info_bcn) + \ 501 sizeof(struct bss_info_bcn_cntdwn) + \ 502 sizeof(struct bss_info_bcn_mbss) + \ 503 MT_TXD_SIZE + \ 504 sizeof(struct bss_info_bcn_cont)) 505 #define MT7915_MAX_BSS_OFFLOAD_SIZE (MT7915_MAX_BEACON_SIZE + \ 506 MT7915_BEACON_UPDATE_SIZE) 507 508 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 509 sizeof(struct bss_info_omac) + \ 510 sizeof(struct bss_info_basic) +\ 511 sizeof(struct bss_info_rf_ch) +\ 512 sizeof(struct bss_info_ra) + \ 513 sizeof(struct bss_info_hw_amsdu) +\ 514 sizeof(struct bss_info_he) + \ 515 sizeof(struct bss_info_bmc_rate) +\ 516 sizeof(struct bss_info_ext_bss)) 517 518 static inline s8 mt7915_get_power_bound(struct mt7915_phy * phy,s8 txpower)519 mt7915_get_power_bound(struct mt7915_phy *phy, s8 txpower) 520 { 521 struct mt76_phy *mphy = phy->mt76; 522 int n_chains = hweight8(mphy->antenna_mask); 523 524 txpower = mt76_get_sar_power(mphy, mphy->chandef.chan, txpower * 2); 525 txpower -= mt76_tx_power_nss_delta(n_chains); 526 527 return txpower; 528 } 529 530 #endif 531