1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7 #include <linux/atomic.h>
8 #include <linux/auxiliary_bus.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/i2c.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/of_graph.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <asm/unaligned.h>
25
26 #include <drm/display/drm_dp_aux_bus.h>
27 #include <drm/display/drm_dp_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_bridge_connector.h>
32 #include <drm/drm_edid.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_of.h>
35 #include <drm/drm_panel.h>
36 #include <drm/drm_print.h>
37 #include <drm/drm_probe_helper.h>
38
39 #define SN_DEVICE_REV_REG 0x08
40 #define SN_DPPLL_SRC_REG 0x0A
41 #define DPPLL_CLK_SRC_DSICLK BIT(0)
42 #define REFCLK_FREQ_MASK GENMASK(3, 1)
43 #define REFCLK_FREQ(x) ((x) << 1)
44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
45 #define SN_PLL_ENABLE_REG 0x0D
46 #define SN_DSI_LANES_REG 0x10
47 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
48 #define CHA_DSI_LANES(x) ((x) << 3)
49 #define SN_DSIA_CLK_FREQ_REG 0x12
50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
54 #define CHA_HSYNC_POLARITY BIT(7)
55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
57 #define CHA_VSYNC_POLARITY BIT(7)
58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
62 #define SN_LN_ASSIGN_REG 0x59
63 #define LN_ASSIGN_WIDTH 2
64 #define SN_ENH_FRAME_REG 0x5A
65 #define VSTREAM_ENABLE BIT(3)
66 #define LN_POLRS_OFFSET 4
67 #define LN_POLRS_MASK 0xf0
68 #define SN_DATA_FORMAT_REG 0x5B
69 #define BPP_18_RGB BIT(0)
70 #define SN_HPD_DISABLE_REG 0x5C
71 #define HPD_DISABLE BIT(0)
72 #define HPD_DEBOUNCED_STATE BIT(4)
73 #define SN_GPIO_IO_REG 0x5E
74 #define SN_GPIO_INPUT_SHIFT 4
75 #define SN_GPIO_OUTPUT_SHIFT 0
76 #define SN_GPIO_CTRL_REG 0x5F
77 #define SN_GPIO_MUX_INPUT 0
78 #define SN_GPIO_MUX_OUTPUT 1
79 #define SN_GPIO_MUX_SPECIAL 2
80 #define SN_GPIO_MUX_MASK 0x3
81 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
82 #define SN_AUX_ADDR_19_16_REG 0x74
83 #define SN_AUX_ADDR_15_8_REG 0x75
84 #define SN_AUX_ADDR_7_0_REG 0x76
85 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
86 #define SN_AUX_LENGTH_REG 0x77
87 #define SN_AUX_CMD_REG 0x78
88 #define AUX_CMD_SEND BIT(0)
89 #define AUX_CMD_REQ(x) ((x) << 4)
90 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
91 #define SN_SSC_CONFIG_REG 0x93
92 #define DP_NUM_LANES_MASK GENMASK(5, 4)
93 #define DP_NUM_LANES(x) ((x) << 4)
94 #define SN_DATARATE_CONFIG_REG 0x94
95 #define DP_DATARATE_MASK GENMASK(7, 5)
96 #define DP_DATARATE(x) ((x) << 5)
97 #define SN_TRAINING_SETTING_REG 0x95
98 #define SCRAMBLE_DISABLE BIT(4)
99 #define SN_ML_TX_MODE_REG 0x96
100 #define ML_TX_MAIN_LINK_OFF 0
101 #define ML_TX_NORMAL_MODE BIT(0)
102 #define SN_PWM_PRE_DIV_REG 0xA0
103 #define SN_BACKLIGHT_SCALE_REG 0xA1
104 #define BACKLIGHT_SCALE_MAX 0xFFFF
105 #define SN_BACKLIGHT_REG 0xA3
106 #define SN_PWM_EN_INV_REG 0xA5
107 #define SN_PWM_INV_MASK BIT(0)
108 #define SN_PWM_EN_MASK BIT(1)
109 #define SN_AUX_CMD_STATUS_REG 0xF4
110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
113
114 #define MIN_DSI_CLK_FREQ_MHZ 40
115
116 /* fudge factor required to account for 8b/10b encoding */
117 #define DP_CLK_FUDGE_NUM 10
118 #define DP_CLK_FUDGE_DEN 8
119
120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
121 #define SN_AUX_MAX_PAYLOAD_BYTES 16
122
123 #define SN_REGULATOR_SUPPLY_NUM 4
124
125 #define SN_MAX_DP_LANES 4
126 #define SN_NUM_GPIOS 4
127 #define SN_GPIO_PHYSICAL_OFFSET 1
128
129 #define SN_LINK_TRAINING_TRIES 10
130
131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */
132
133 /**
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
139 *
140 * @dev: Pointer to the top level (i2c) device.
141 * @regmap: Regmap for accessing i2c.
142 * @aux: Our aux channel.
143 * @bridge: Our bridge.
144 * @connector: Our connector.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
147 * @refclk: Our reference clock.
148 * @next_bridge: The bridge on the eDP side.
149 * @enable_gpio: The GPIO we toggle to enable the bridge.
150 * @supplies: Data for bulk enabling/disabling our regulators.
151 * @dp_lanes: Count of dp_lanes we're using.
152 * @ln_assign: Value to program to the LN_ASSIGN register.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
155 * @comms_mutex: Protects modification of comms_enabled.
156 *
157 * @gchip: If we expose our GPIOs, this is used.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
159 * serves double-duty of keeping track of the direction and
160 * also keeping track of whether we've incremented the
161 * pm_runtime reference count for this pin, which we do
162 * whenever a pin is configured as an output. This is a
163 * bitmap so we can do atomic ops on it without an extra
164 * lock so concurrent users of our 4 GPIOs don't stomp on
165 * each other's read-modify-write.
166 *
167 * @pchip: pwm_chip if the PWM is exposed.
168 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
171 */
172 struct ti_sn65dsi86 {
173 struct auxiliary_device *bridge_aux;
174 struct auxiliary_device *gpio_aux;
175 struct auxiliary_device *aux_aux;
176 struct auxiliary_device *pwm_aux;
177
178 struct device *dev;
179 struct regmap *regmap;
180 struct drm_dp_aux aux;
181 struct drm_bridge bridge;
182 struct drm_connector *connector;
183 struct device_node *host_node;
184 struct mipi_dsi_device *dsi;
185 struct clk *refclk;
186 struct drm_bridge *next_bridge;
187 struct gpio_desc *enable_gpio;
188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
189 int dp_lanes;
190 u8 ln_assign;
191 u8 ln_polrs;
192 bool comms_enabled;
193 struct mutex comms_mutex;
194
195 #if defined(CONFIG_OF_GPIO)
196 struct gpio_chip gchip;
197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
198 #endif
199 #if defined(CONFIG_PWM)
200 struct pwm_chip pchip;
201 bool pwm_enabled;
202 atomic_t pwm_pin_busy;
203 #endif
204 unsigned int pwm_refclk_freq;
205 };
206
207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
208 { .range_min = 0, .range_max = 0xFF },
209 };
210
211 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
212 .yes_ranges = ti_sn65dsi86_volatile_ranges,
213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
214 };
215
216 static const struct regmap_config ti_sn65dsi86_regmap_config = {
217 .reg_bits = 8,
218 .val_bits = 8,
219 .volatile_table = &ti_sn_bridge_volatile_table,
220 .cache_type = REGCACHE_NONE,
221 .max_register = 0xFF,
222 };
223
ti_sn65dsi86_read_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 * val)224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
225 unsigned int reg, u16 *val)
226 {
227 u8 buf[2];
228 int ret;
229
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
231 if (ret)
232 return ret;
233
234 *val = buf[0] | (buf[1] << 8);
235
236 return 0;
237 }
238
ti_sn65dsi86_write_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 val)239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
240 unsigned int reg, u16 val)
241 {
242 u8 buf[2] = { val & 0xff, val >> 8 };
243
244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
245 }
246
ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 * pdata)247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
248 {
249 u32 bit_rate_khz, clk_freq_khz;
250 struct drm_display_mode *mode =
251 &pdata->bridge.encoder->crtc->state->adjusted_mode;
252
253 bit_rate_khz = mode->clock *
254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
256
257 return clk_freq_khz;
258 }
259
260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
261 static const u32 ti_sn_bridge_refclk_lut[] = {
262 12000000,
263 19200000,
264 26000000,
265 27000000,
266 38400000,
267 };
268
269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
270 static const u32 ti_sn_bridge_dsiclk_lut[] = {
271 468000000,
272 384000000,
273 416000000,
274 486000000,
275 460800000,
276 };
277
ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 * pdata)278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
279 {
280 int i;
281 u32 refclk_rate;
282 const u32 *refclk_lut;
283 size_t refclk_lut_size;
284
285 if (pdata->refclk) {
286 refclk_rate = clk_get_rate(pdata->refclk);
287 refclk_lut = ti_sn_bridge_refclk_lut;
288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
289 clk_prepare_enable(pdata->refclk);
290 } else {
291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
292 refclk_lut = ti_sn_bridge_dsiclk_lut;
293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
294 }
295
296 /* for i equals to refclk_lut_size means default frequency */
297 for (i = 0; i < refclk_lut_size; i++)
298 if (refclk_lut[i] == refclk_rate)
299 break;
300
301 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
302 if (i >= refclk_lut_size)
303 i = 1;
304
305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
306 REFCLK_FREQ(i));
307
308 /*
309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
310 * regardless of its actual sourcing.
311 */
312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
313 }
314
ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 * pdata)315 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
316 {
317 mutex_lock(&pdata->comms_mutex);
318
319 /* configure bridge ref_clk */
320 ti_sn_bridge_set_refclk_freq(pdata);
321
322 /*
323 * HPD on this bridge chip is a bit useless. This is an eDP bridge
324 * so the HPD is an internal signal that's only there to signal that
325 * the panel is done powering up. ...but the bridge chip debounces
326 * this signal by between 100 ms and 400 ms (depending on process,
327 * voltage, and temperate--I measured it at about 200 ms). One
328 * particular panel asserted HPD 84 ms after it was powered on meaning
329 * that we saw HPD 284 ms after power on. ...but the same panel said
330 * that instead of looking at HPD you could just hardcode a delay of
331 * 200 ms. We'll assume that the panel driver will have the hardcoded
332 * delay in its prepare and always disable HPD.
333 *
334 * If HPD somehow makes sense on some future panel we'll have to
335 * change this to be conditional on someone specifying that HPD should
336 * be used.
337 */
338 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
339 HPD_DISABLE);
340
341 pdata->comms_enabled = true;
342
343 mutex_unlock(&pdata->comms_mutex);
344 }
345
ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 * pdata)346 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
347 {
348 mutex_lock(&pdata->comms_mutex);
349
350 pdata->comms_enabled = false;
351 clk_disable_unprepare(pdata->refclk);
352
353 mutex_unlock(&pdata->comms_mutex);
354 }
355
ti_sn65dsi86_resume(struct device * dev)356 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
357 {
358 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
359 int ret;
360
361 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
362 if (ret) {
363 DRM_ERROR("failed to enable supplies %d\n", ret);
364 return ret;
365 }
366
367 /* td2: min 100 us after regulators before enabling the GPIO */
368 usleep_range(100, 110);
369
370 gpiod_set_value_cansleep(pdata->enable_gpio, 1);
371
372 /*
373 * If we have a reference clock we can enable communication w/ the
374 * panel (including the aux channel) w/out any need for an input clock
375 * so we can do it in resume which lets us read the EDID before
376 * pre_enable(). Without a reference clock we need the MIPI reference
377 * clock so reading early doesn't work.
378 */
379 if (pdata->refclk)
380 ti_sn65dsi86_enable_comms(pdata);
381
382 return ret;
383 }
384
ti_sn65dsi86_suspend(struct device * dev)385 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
386 {
387 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
388 int ret;
389
390 if (pdata->refclk)
391 ti_sn65dsi86_disable_comms(pdata);
392
393 gpiod_set_value_cansleep(pdata->enable_gpio, 0);
394
395 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
396 if (ret)
397 DRM_ERROR("failed to disable supplies %d\n", ret);
398
399 return ret;
400 }
401
402 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
403 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
404 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
405 pm_runtime_force_resume)
406 };
407
status_show(struct seq_file * s,void * data)408 static int status_show(struct seq_file *s, void *data)
409 {
410 struct ti_sn65dsi86 *pdata = s->private;
411 unsigned int reg, val;
412
413 seq_puts(s, "STATUS REGISTERS:\n");
414
415 pm_runtime_get_sync(pdata->dev);
416
417 /* IRQ Status Registers, see Table 31 in datasheet */
418 for (reg = 0xf0; reg <= 0xf8; reg++) {
419 regmap_read(pdata->regmap, reg, &val);
420 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
421 }
422
423 pm_runtime_put_autosuspend(pdata->dev);
424
425 return 0;
426 }
427
428 DEFINE_SHOW_ATTRIBUTE(status);
429
ti_sn65dsi86_debugfs_remove(void * data)430 static void ti_sn65dsi86_debugfs_remove(void *data)
431 {
432 debugfs_remove_recursive(data);
433 }
434
ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 * pdata)435 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
436 {
437 struct device *dev = pdata->dev;
438 struct dentry *debugfs;
439 int ret;
440
441 debugfs = debugfs_create_dir(dev_name(dev), NULL);
442
443 /*
444 * We might get an error back if debugfs wasn't enabled in the kernel
445 * so let's just silently return upon failure.
446 */
447 if (IS_ERR_OR_NULL(debugfs))
448 return;
449
450 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
451 if (ret)
452 return;
453
454 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
455 }
456
457 /* -----------------------------------------------------------------------------
458 * Auxiliary Devices (*not* AUX)
459 */
460
ti_sn65dsi86_uninit_aux(void * data)461 static void ti_sn65dsi86_uninit_aux(void *data)
462 {
463 auxiliary_device_uninit(data);
464 }
465
ti_sn65dsi86_delete_aux(void * data)466 static void ti_sn65dsi86_delete_aux(void *data)
467 {
468 auxiliary_device_delete(data);
469 }
470
ti_sn65dsi86_aux_device_release(struct device * dev)471 static void ti_sn65dsi86_aux_device_release(struct device *dev)
472 {
473 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
474
475 kfree(aux);
476 }
477
ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 * pdata,struct auxiliary_device ** aux_out,const char * name)478 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
479 struct auxiliary_device **aux_out,
480 const char *name)
481 {
482 struct device *dev = pdata->dev;
483 const struct i2c_client *client = to_i2c_client(dev);
484 struct auxiliary_device *aux;
485 int ret;
486
487 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
488 if (!aux)
489 return -ENOMEM;
490
491 aux->name = name;
492 aux->id = (client->adapter->nr << 10) | client->addr;
493 aux->dev.parent = dev;
494 aux->dev.release = ti_sn65dsi86_aux_device_release;
495 device_set_of_node_from_dev(&aux->dev, dev);
496 ret = auxiliary_device_init(aux);
497 if (ret) {
498 kfree(aux);
499 return ret;
500 }
501 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
502 if (ret)
503 return ret;
504
505 ret = auxiliary_device_add(aux);
506 if (ret)
507 return ret;
508 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
509 if (!ret)
510 *aux_out = aux;
511
512 return ret;
513 }
514
515 /* -----------------------------------------------------------------------------
516 * AUX Adapter
517 */
518
aux_to_ti_sn65dsi86(struct drm_dp_aux * aux)519 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
520 {
521 return container_of(aux, struct ti_sn65dsi86, aux);
522 }
523
ti_sn_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)524 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
525 struct drm_dp_aux_msg *msg)
526 {
527 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
528 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
529 u32 request_val = AUX_CMD_REQ(msg->request);
530 u8 *buf = msg->buffer;
531 unsigned int len = msg->size;
532 unsigned int short_len;
533 unsigned int val;
534 int ret;
535 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
536
537 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
538 return -EINVAL;
539
540 pm_runtime_get_sync(pdata->dev);
541 mutex_lock(&pdata->comms_mutex);
542
543 /*
544 * If someone tries to do a DDC over AUX transaction before pre_enable()
545 * on a device without a dedicated reference clock then we just can't
546 * do it. Fail right away. This prevents non-refclk users from reading
547 * the EDID before enabling the panel but such is life.
548 */
549 if (!pdata->comms_enabled) {
550 ret = -EIO;
551 goto exit;
552 }
553
554 switch (request) {
555 case DP_AUX_NATIVE_WRITE:
556 case DP_AUX_I2C_WRITE:
557 case DP_AUX_NATIVE_READ:
558 case DP_AUX_I2C_READ:
559 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
560 /* Assume it's good */
561 msg->reply = 0;
562 break;
563 default:
564 ret = -EINVAL;
565 goto exit;
566 }
567
568 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
569 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
570 addr_len);
571 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
572 ARRAY_SIZE(addr_len));
573
574 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
575 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
576
577 /* Clear old status bits before start so we don't get confused */
578 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
579 AUX_IRQ_STATUS_NAT_I2C_FAIL |
580 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
581 AUX_IRQ_STATUS_AUX_SHORT);
582
583 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
584
585 /* Zero delay loop because i2c transactions are slow already */
586 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
587 !(val & AUX_CMD_SEND), 0, 50 * 1000);
588 if (ret)
589 goto exit;
590
591 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
592 if (ret)
593 goto exit;
594
595 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
596 /*
597 * The hardware tried the message seven times per the DP spec
598 * but it hit a timeout. We ignore defers here because they're
599 * handled in hardware.
600 */
601 ret = -ETIMEDOUT;
602 goto exit;
603 }
604
605 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
606 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
607 len = min(len, short_len);
608 if (ret)
609 goto exit;
610 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
611 switch (request) {
612 case DP_AUX_I2C_WRITE:
613 case DP_AUX_I2C_READ:
614 msg->reply |= DP_AUX_I2C_REPLY_NACK;
615 break;
616 case DP_AUX_NATIVE_READ:
617 case DP_AUX_NATIVE_WRITE:
618 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
619 break;
620 }
621 len = 0;
622 goto exit;
623 }
624
625 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
626 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
627
628 exit:
629 mutex_unlock(&pdata->comms_mutex);
630 pm_runtime_mark_last_busy(pdata->dev);
631 pm_runtime_put_autosuspend(pdata->dev);
632
633 if (ret)
634 return ret;
635 return len;
636 }
637
ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux * aux,unsigned long wait_us)638 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
639 {
640 /*
641 * The HPD in this chip is a bit useless (See comment in
642 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
643 * for HPD, we just assume it's asserted after the wait_us delay.
644 *
645 * In case we are asked to wait forever (wait_us=0) take conservative
646 * 500ms delay.
647 */
648 if (wait_us == 0)
649 wait_us = 500000;
650
651 usleep_range(wait_us, wait_us + 1000);
652
653 return 0;
654 }
655
ti_sn_aux_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)656 static int ti_sn_aux_probe(struct auxiliary_device *adev,
657 const struct auxiliary_device_id *id)
658 {
659 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
660 int ret;
661
662 pdata->aux.name = "ti-sn65dsi86-aux";
663 pdata->aux.dev = &adev->dev;
664 pdata->aux.transfer = ti_sn_aux_transfer;
665 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
666 drm_dp_aux_init(&pdata->aux);
667
668 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
669 if (ret)
670 return ret;
671
672 /*
673 * The eDP to MIPI bridge parts don't work until the AUX channel is
674 * setup so we don't add it in the main driver probe, we add it now.
675 */
676 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
677 }
678
679 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
680 { .name = "ti_sn65dsi86.aux", },
681 {},
682 };
683
684 static struct auxiliary_driver ti_sn_aux_driver = {
685 .name = "aux",
686 .probe = ti_sn_aux_probe,
687 .id_table = ti_sn_aux_id_table,
688 };
689
690 /*------------------------------------------------------------------------------
691 * DRM Bridge
692 */
693
bridge_to_ti_sn65dsi86(struct drm_bridge * bridge)694 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
695 {
696 return container_of(bridge, struct ti_sn65dsi86, bridge);
697 }
698
ti_sn_attach_host(struct auxiliary_device * adev,struct ti_sn65dsi86 * pdata)699 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata)
700 {
701 int val;
702 struct mipi_dsi_host *host;
703 struct mipi_dsi_device *dsi;
704 struct device *dev = pdata->dev;
705 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
706 .channel = 0,
707 .node = NULL,
708 };
709
710 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
711 if (!host)
712 return -EPROBE_DEFER;
713
714 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info);
715 if (IS_ERR(dsi))
716 return PTR_ERR(dsi);
717
718 /* TODO: setting to 4 MIPI lanes always for now */
719 dsi->lanes = 4;
720 dsi->format = MIPI_DSI_FMT_RGB888;
721 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
722
723 /* check if continuous dsi clock is required or not */
724 pm_runtime_get_sync(dev);
725 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
726 pm_runtime_put_autosuspend(dev);
727 if (!(val & DPPLL_CLK_SRC_DSICLK))
728 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
729
730 pdata->dsi = dsi;
731
732 return devm_mipi_dsi_attach(&adev->dev, dsi);
733 }
734
ti_sn_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)735 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
736 enum drm_bridge_attach_flags flags)
737 {
738 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
739 int ret;
740
741 pdata->aux.drm_dev = bridge->dev;
742 ret = drm_dp_aux_register(&pdata->aux);
743 if (ret < 0) {
744 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
745 return ret;
746 }
747
748 /*
749 * Attach the next bridge.
750 * We never want the next bridge to *also* create a connector.
751 */
752 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
753 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
754 if (ret < 0)
755 goto err_initted_aux;
756
757 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
758 return 0;
759
760 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
761 pdata->bridge.encoder);
762 if (IS_ERR(pdata->connector)) {
763 ret = PTR_ERR(pdata->connector);
764 goto err_initted_aux;
765 }
766
767 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
768
769 return 0;
770
771 err_initted_aux:
772 drm_dp_aux_unregister(&pdata->aux);
773 return ret;
774 }
775
ti_sn_bridge_detach(struct drm_bridge * bridge)776 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
777 {
778 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
779 }
780
781 static enum drm_mode_status
ti_sn_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)782 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
783 const struct drm_display_info *info,
784 const struct drm_display_mode *mode)
785 {
786 /* maximum supported resolution is 4K at 60 fps */
787 if (mode->clock > 594000)
788 return MODE_CLOCK_HIGH;
789
790 /*
791 * The front and back porch registers are 8 bits, and pulse width
792 * registers are 15 bits, so reject any modes with larger periods.
793 */
794
795 if ((mode->hsync_start - mode->hdisplay) > 0xff)
796 return MODE_HBLANK_WIDE;
797
798 if ((mode->vsync_start - mode->vdisplay) > 0xff)
799 return MODE_VBLANK_WIDE;
800
801 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
802 return MODE_HSYNC_WIDE;
803
804 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
805 return MODE_VSYNC_WIDE;
806
807 if ((mode->htotal - mode->hsync_end) > 0xff)
808 return MODE_HBLANK_WIDE;
809
810 if ((mode->vtotal - mode->vsync_end) > 0xff)
811 return MODE_VBLANK_WIDE;
812
813 return MODE_OK;
814 }
815
ti_sn_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)816 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
817 struct drm_bridge_state *old_bridge_state)
818 {
819 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
820
821 /* disable video stream */
822 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
823 }
824
ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 * pdata)825 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
826 {
827 unsigned int bit_rate_mhz, clk_freq_mhz;
828 unsigned int val;
829 struct drm_display_mode *mode =
830 &pdata->bridge.encoder->crtc->state->adjusted_mode;
831
832 /* set DSIA clk frequency */
833 bit_rate_mhz = (mode->clock / 1000) *
834 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
835 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
836
837 /* for each increment in val, frequency increases by 5MHz */
838 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
839 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
840 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
841 }
842
ti_sn_bridge_get_bpp(struct drm_connector * connector)843 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
844 {
845 if (connector->display_info.bpc <= 6)
846 return 18;
847 else
848 return 24;
849 }
850
851 /*
852 * LUT index corresponds to register value and
853 * LUT values corresponds to dp data rate supported
854 * by the bridge in Mbps unit.
855 */
856 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
857 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
858 };
859
ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 * pdata,unsigned int bpp)860 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp)
861 {
862 unsigned int bit_rate_khz, dp_rate_mhz;
863 unsigned int i;
864 struct drm_display_mode *mode =
865 &pdata->bridge.encoder->crtc->state->adjusted_mode;
866
867 /* Calculate minimum bit rate based on our pixel clock. */
868 bit_rate_khz = mode->clock * bpp;
869
870 /* Calculate minimum DP data rate, taking 80% as per DP spec */
871 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
872 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
873
874 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
875 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
876 break;
877
878 return i;
879 }
880
ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 * pdata)881 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
882 {
883 unsigned int valid_rates = 0;
884 unsigned int rate_per_200khz;
885 unsigned int rate_mhz;
886 u8 dpcd_val;
887 int ret;
888 int i, j;
889
890 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
891 if (ret != 1) {
892 DRM_DEV_ERROR(pdata->dev,
893 "Can't read eDP rev (%d), assuming 1.1\n", ret);
894 dpcd_val = DP_EDP_11;
895 }
896
897 if (dpcd_val >= DP_EDP_14) {
898 /* eDP 1.4 devices must provide a custom table */
899 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
900
901 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
902 sink_rates, sizeof(sink_rates));
903
904 if (ret != sizeof(sink_rates)) {
905 DRM_DEV_ERROR(pdata->dev,
906 "Can't read supported rate table (%d)\n", ret);
907
908 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
909 memset(sink_rates, 0, sizeof(sink_rates));
910 }
911
912 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
913 rate_per_200khz = le16_to_cpu(sink_rates[i]);
914
915 if (!rate_per_200khz)
916 break;
917
918 rate_mhz = rate_per_200khz * 200 / 1000;
919 for (j = 0;
920 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
921 j++) {
922 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
923 valid_rates |= BIT(j);
924 }
925 }
926
927 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
928 if (valid_rates & BIT(i))
929 return valid_rates;
930 }
931 DRM_DEV_ERROR(pdata->dev,
932 "No matching eDP rates in table; falling back\n");
933 }
934
935 /* On older versions best we can do is use DP_MAX_LINK_RATE */
936 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
937 if (ret != 1) {
938 DRM_DEV_ERROR(pdata->dev,
939 "Can't read max rate (%d); assuming 5.4 GHz\n",
940 ret);
941 dpcd_val = DP_LINK_BW_5_4;
942 }
943
944 switch (dpcd_val) {
945 default:
946 DRM_DEV_ERROR(pdata->dev,
947 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
948 (int)dpcd_val);
949 fallthrough;
950 case DP_LINK_BW_5_4:
951 valid_rates |= BIT(7);
952 fallthrough;
953 case DP_LINK_BW_2_7:
954 valid_rates |= BIT(4);
955 fallthrough;
956 case DP_LINK_BW_1_62:
957 valid_rates |= BIT(1);
958 break;
959 }
960
961 return valid_rates;
962 }
963
ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 * pdata)964 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
965 {
966 struct drm_display_mode *mode =
967 &pdata->bridge.encoder->crtc->state->adjusted_mode;
968 u8 hsync_polarity = 0, vsync_polarity = 0;
969
970 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
971 hsync_polarity = CHA_HSYNC_POLARITY;
972 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
973 vsync_polarity = CHA_VSYNC_POLARITY;
974
975 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
976 mode->hdisplay);
977 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
978 mode->vdisplay);
979 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
980 (mode->hsync_end - mode->hsync_start) & 0xFF);
981 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
982 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
983 hsync_polarity);
984 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
985 (mode->vsync_end - mode->vsync_start) & 0xFF);
986 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
987 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
988 vsync_polarity);
989
990 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
991 (mode->htotal - mode->hsync_end) & 0xFF);
992 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
993 (mode->vtotal - mode->vsync_end) & 0xFF);
994
995 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
996 (mode->hsync_start - mode->hdisplay) & 0xFF);
997 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
998 (mode->vsync_start - mode->vdisplay) & 0xFF);
999
1000 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
1001 }
1002
ti_sn_get_max_lanes(struct ti_sn65dsi86 * pdata)1003 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
1004 {
1005 u8 data;
1006 int ret;
1007
1008 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
1009 if (ret != 1) {
1010 DRM_DEV_ERROR(pdata->dev,
1011 "Can't read lane count (%d); assuming 4\n", ret);
1012 return 4;
1013 }
1014
1015 return data & DP_LANE_COUNT_MASK;
1016 }
1017
ti_sn_link_training(struct ti_sn65dsi86 * pdata,int dp_rate_idx,const char ** last_err_str)1018 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1019 const char **last_err_str)
1020 {
1021 unsigned int val;
1022 int ret;
1023 int i;
1024
1025 /* set dp clk frequency value */
1026 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1027 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1028
1029 /* enable DP PLL */
1030 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1031
1032 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1033 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1034 50 * 1000);
1035 if (ret) {
1036 *last_err_str = "DP_PLL_LOCK polling failed";
1037 goto exit;
1038 }
1039
1040 /*
1041 * We'll try to link train several times. As part of link training
1042 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1043 * the panel isn't ready quite it might respond NAK here which means
1044 * we need to try again.
1045 */
1046 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1047 /* Semi auto link training mode */
1048 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1049 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1050 val == ML_TX_MAIN_LINK_OFF ||
1051 val == ML_TX_NORMAL_MODE, 1000,
1052 500 * 1000);
1053 if (ret) {
1054 *last_err_str = "Training complete polling failed";
1055 } else if (val == ML_TX_MAIN_LINK_OFF) {
1056 *last_err_str = "Link training failed, link is off";
1057 ret = -EIO;
1058 continue;
1059 }
1060
1061 break;
1062 }
1063
1064 /* If we saw quite a few retries, add a note about it */
1065 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1066 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1067
1068 exit:
1069 /* Disable the PLL if we failed */
1070 if (ret)
1071 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1072
1073 return ret;
1074 }
1075
ti_sn_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1076 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1077 struct drm_bridge_state *old_bridge_state)
1078 {
1079 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1080 struct drm_connector *connector;
1081 const char *last_err_str = "No supported DP rate";
1082 unsigned int valid_rates;
1083 int dp_rate_idx;
1084 unsigned int val;
1085 int ret = -EINVAL;
1086 int max_dp_lanes;
1087 unsigned int bpp;
1088
1089 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
1090 bridge->encoder);
1091 if (!connector) {
1092 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1093 return;
1094 }
1095
1096 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1097 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1098
1099 /* DSI_A lane config */
1100 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1101 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1102 CHA_DSI_LANES_MASK, val);
1103
1104 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1105 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1106 pdata->ln_polrs << LN_POLRS_OFFSET);
1107
1108 /* set dsi clk frequency value */
1109 ti_sn_bridge_set_dsi_rate(pdata);
1110
1111 /*
1112 * The SN65DSI86 only supports ASSR Display Authentication method and
1113 * this method is enabled for eDP panels. An eDP panel must support this
1114 * authentication method. We need to enable this method in the eDP panel
1115 * at DisplayPort address 0x0010A prior to link training.
1116 *
1117 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1118 * we need to disable the scrambler.
1119 */
1120 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1121 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1122 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1123
1124 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1125 SCRAMBLE_DISABLE, 0);
1126 } else {
1127 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1128 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1129 }
1130
1131 bpp = ti_sn_bridge_get_bpp(connector);
1132 /* Set the DP output format (18 bpp or 24 bpp) */
1133 val = bpp == 18 ? BPP_18_RGB : 0;
1134 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1135
1136 /* DP lane config */
1137 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1138 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1139 val);
1140
1141 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1142
1143 /* Train until we run out of rates */
1144 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
1145 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1146 dp_rate_idx++) {
1147 if (!(valid_rates & BIT(dp_rate_idx)))
1148 continue;
1149
1150 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1151 if (!ret)
1152 break;
1153 }
1154 if (ret) {
1155 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1156 return;
1157 }
1158
1159 /* config video parameters */
1160 ti_sn_bridge_set_video_timings(pdata);
1161
1162 /* enable video stream */
1163 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1164 VSTREAM_ENABLE);
1165 }
1166
ti_sn_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1167 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1168 struct drm_bridge_state *old_bridge_state)
1169 {
1170 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1171
1172 pm_runtime_get_sync(pdata->dev);
1173
1174 if (!pdata->refclk)
1175 ti_sn65dsi86_enable_comms(pdata);
1176
1177 /* td7: min 100 us after enable before DSI data */
1178 usleep_range(100, 110);
1179 }
1180
ti_sn_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)1181 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1182 struct drm_bridge_state *old_bridge_state)
1183 {
1184 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1185
1186 /* semi auto link training mode OFF */
1187 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1188 /* Num lanes to 0 as per power sequencing in data sheet */
1189 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1190 /* disable DP PLL */
1191 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1192
1193 if (!pdata->refclk)
1194 ti_sn65dsi86_disable_comms(pdata);
1195
1196 pm_runtime_put_sync(pdata->dev);
1197 }
1198
ti_sn_bridge_detect(struct drm_bridge * bridge)1199 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
1200 {
1201 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1202 int val = 0;
1203
1204 pm_runtime_get_sync(pdata->dev);
1205 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1206 pm_runtime_put_autosuspend(pdata->dev);
1207
1208 return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1209 : connector_status_disconnected;
1210 }
1211
ti_sn_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)1212 static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge,
1213 struct drm_connector *connector)
1214 {
1215 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1216
1217 return drm_get_edid(connector, &pdata->aux.ddc);
1218 }
1219
1220 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1221 .attach = ti_sn_bridge_attach,
1222 .detach = ti_sn_bridge_detach,
1223 .mode_valid = ti_sn_bridge_mode_valid,
1224 .get_edid = ti_sn_bridge_get_edid,
1225 .detect = ti_sn_bridge_detect,
1226 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1227 .atomic_enable = ti_sn_bridge_atomic_enable,
1228 .atomic_disable = ti_sn_bridge_atomic_disable,
1229 .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1230 .atomic_reset = drm_atomic_helper_bridge_reset,
1231 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1232 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1233 };
1234
ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 * pdata,struct device_node * np)1235 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1236 struct device_node *np)
1237 {
1238 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1239 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1240 struct device_node *endpoint;
1241 u8 ln_assign = 0;
1242 u8 ln_polrs = 0;
1243 int dp_lanes;
1244 int i;
1245
1246 /*
1247 * Read config from the device tree about lane remapping and lane
1248 * polarities. These are optional and we assume identity map and
1249 * normal polarity if nothing is specified. It's OK to specify just
1250 * data-lanes but not lane-polarities but not vice versa.
1251 *
1252 * Error checking is light (we just make sure we don't crash or
1253 * buffer overrun) and we assume dts is well formed and specifying
1254 * mappings that the hardware supports.
1255 */
1256 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1257 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES);
1258 if (dp_lanes > 0) {
1259 of_property_read_u32_array(endpoint, "data-lanes",
1260 lane_assignments, dp_lanes);
1261 of_property_read_u32_array(endpoint, "lane-polarities",
1262 lane_polarities, dp_lanes);
1263 } else {
1264 dp_lanes = SN_MAX_DP_LANES;
1265 }
1266 of_node_put(endpoint);
1267
1268 /*
1269 * Convert into register format. Loop over all lanes even if
1270 * data-lanes had fewer elements so that we nicely initialize
1271 * the LN_ASSIGN register.
1272 */
1273 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1274 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1275 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1276 }
1277
1278 /* Stash in our struct for when we power on */
1279 pdata->dp_lanes = dp_lanes;
1280 pdata->ln_assign = ln_assign;
1281 pdata->ln_polrs = ln_polrs;
1282 }
1283
ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 * pdata)1284 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1285 {
1286 struct device_node *np = pdata->dev->of_node;
1287
1288 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1289
1290 if (!pdata->host_node) {
1291 DRM_ERROR("remote dsi host node not found\n");
1292 return -ENODEV;
1293 }
1294
1295 return 0;
1296 }
1297
ti_sn_bridge_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1298 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1299 const struct auxiliary_device_id *id)
1300 {
1301 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1302 struct device_node *np = pdata->dev->of_node;
1303 int ret;
1304
1305 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0);
1306 if (IS_ERR(pdata->next_bridge))
1307 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge),
1308 "failed to create panel bridge\n");
1309
1310 ti_sn_bridge_parse_lanes(pdata, np);
1311
1312 ret = ti_sn_bridge_parse_dsi_host(pdata);
1313 if (ret)
1314 return ret;
1315
1316 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1317 pdata->bridge.of_node = np;
1318 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1319 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1320
1321 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort)
1322 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
1323
1324 drm_bridge_add(&pdata->bridge);
1325
1326 ret = ti_sn_attach_host(adev, pdata);
1327 if (ret) {
1328 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n");
1329 goto err_remove_bridge;
1330 }
1331
1332 return 0;
1333
1334 err_remove_bridge:
1335 drm_bridge_remove(&pdata->bridge);
1336 return ret;
1337 }
1338
ti_sn_bridge_remove(struct auxiliary_device * adev)1339 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1340 {
1341 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1342
1343 if (!pdata)
1344 return;
1345
1346 drm_bridge_remove(&pdata->bridge);
1347
1348 of_node_put(pdata->host_node);
1349 }
1350
1351 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1352 { .name = "ti_sn65dsi86.bridge", },
1353 {},
1354 };
1355
1356 static struct auxiliary_driver ti_sn_bridge_driver = {
1357 .name = "bridge",
1358 .probe = ti_sn_bridge_probe,
1359 .remove = ti_sn_bridge_remove,
1360 .id_table = ti_sn_bridge_id_table,
1361 };
1362
1363 /* -----------------------------------------------------------------------------
1364 * PWM Controller
1365 */
1366 #if defined(CONFIG_PWM)
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1367 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1368 {
1369 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1370 }
1371
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1372 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1373 {
1374 atomic_set(&pdata->pwm_pin_busy, 0);
1375 }
1376
pwm_chip_to_ti_sn_bridge(struct pwm_chip * chip)1377 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1378 {
1379 return container_of(chip, struct ti_sn65dsi86, pchip);
1380 }
1381
ti_sn_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)1382 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1383 {
1384 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1385
1386 return ti_sn_pwm_pin_request(pdata);
1387 }
1388
ti_sn_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)1389 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1390 {
1391 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1392
1393 ti_sn_pwm_pin_release(pdata);
1394 }
1395
1396 /*
1397 * Limitations:
1398 * - The PWM signal is not driven when the chip is powered down, or in its
1399 * reset state and the driver does not implement the "suspend state"
1400 * described in the documentation. In order to save power, state->enabled is
1401 * interpreted as denoting if the signal is expected to be valid, and is used
1402 * to determine if the chip needs to be kept powered.
1403 * - Changing both period and duty_cycle is not done atomically, neither is the
1404 * multi-byte register updates, so the output might briefly be undefined
1405 * during update.
1406 */
ti_sn_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)1407 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1408 const struct pwm_state *state)
1409 {
1410 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1411 unsigned int pwm_en_inv;
1412 unsigned int backlight;
1413 unsigned int pre_div;
1414 unsigned int scale;
1415 u64 period_max;
1416 u64 period;
1417 int ret;
1418
1419 if (!pdata->pwm_enabled) {
1420 ret = pm_runtime_get_sync(pdata->dev);
1421 if (ret < 0) {
1422 pm_runtime_put_sync(pdata->dev);
1423 return ret;
1424 }
1425 }
1426
1427 if (state->enabled) {
1428 if (!pdata->pwm_enabled) {
1429 /*
1430 * The chip might have been powered down while we
1431 * didn't hold a PM runtime reference, so mux in the
1432 * PWM function on the GPIO pin again.
1433 */
1434 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1435 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1436 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1437 if (ret) {
1438 dev_err(pdata->dev, "failed to mux in PWM function\n");
1439 goto out;
1440 }
1441 }
1442
1443 /*
1444 * Per the datasheet the PWM frequency is given by:
1445 *
1446 * REFCLK_FREQ
1447 * PWM_FREQ = -----------------------------------
1448 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1449 *
1450 * However, after careful review the author is convinced that
1451 * the documentation has lost some parenthesis around
1452 * "BACKLIGHT_SCALE + 1".
1453 *
1454 * With the period T_pwm = 1/PWM_FREQ this can be written:
1455 *
1456 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1457 *
1458 * In order to keep BACKLIGHT_SCALE within its 16 bits,
1459 * PWM_PRE_DIV must be:
1460 *
1461 * T_pwm * REFCLK_FREQ
1462 * PWM_PRE_DIV >= -------------------------
1463 * BACKLIGHT_SCALE_MAX + 1
1464 *
1465 * To simplify the search and to favour higher resolution of
1466 * the duty cycle over accuracy of the period, the lowest
1467 * possible PWM_PRE_DIV is used. Finally the scale is
1468 * calculated as:
1469 *
1470 * T_pwm * REFCLK_FREQ
1471 * BACKLIGHT_SCALE = ---------------------- - 1
1472 * PWM_PRE_DIV
1473 *
1474 * Here T_pwm is represented in seconds, so appropriate scaling
1475 * to nanoseconds is necessary.
1476 */
1477
1478 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1479 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1480 ret = -EINVAL;
1481 goto out;
1482 }
1483
1484 /*
1485 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1486 * Limit period to this to avoid overflows
1487 */
1488 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1489 pdata->pwm_refclk_freq);
1490 period = min(state->period, period_max);
1491
1492 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1493 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1494 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1495
1496 /*
1497 * The documentation has the duty ratio given as:
1498 *
1499 * duty BACKLIGHT
1500 * ------- = ---------------------
1501 * period BACKLIGHT_SCALE + 1
1502 *
1503 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1504 * to definition above and adjusting for nanosecond
1505 * representation of duty cycle gives us:
1506 */
1507 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1508 (u64)NSEC_PER_SEC * pre_div);
1509 if (backlight > scale)
1510 backlight = scale;
1511
1512 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1513 if (ret) {
1514 dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n");
1515 goto out;
1516 }
1517
1518 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1519 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1520 }
1521
1522 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1523 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1524 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1525 if (ret) {
1526 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n");
1527 goto out;
1528 }
1529
1530 pdata->pwm_enabled = state->enabled;
1531 out:
1532
1533 if (!pdata->pwm_enabled)
1534 pm_runtime_put_sync(pdata->dev);
1535
1536 return ret;
1537 }
1538
ti_sn_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)1539 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1540 struct pwm_state *state)
1541 {
1542 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1543 unsigned int pwm_en_inv;
1544 unsigned int pre_div;
1545 u16 backlight;
1546 u16 scale;
1547 int ret;
1548
1549 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1550 if (ret)
1551 return ret;
1552
1553 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1554 if (ret)
1555 return ret;
1556
1557 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1558 if (ret)
1559 return ret;
1560
1561 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1562 if (ret)
1563 return ret;
1564
1565 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1566 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1567 state->polarity = PWM_POLARITY_INVERSED;
1568 else
1569 state->polarity = PWM_POLARITY_NORMAL;
1570
1571 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1572 pdata->pwm_refclk_freq);
1573 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1574 pdata->pwm_refclk_freq);
1575
1576 if (state->duty_cycle > state->period)
1577 state->duty_cycle = state->period;
1578
1579 return 0;
1580 }
1581
1582 static const struct pwm_ops ti_sn_pwm_ops = {
1583 .request = ti_sn_pwm_request,
1584 .free = ti_sn_pwm_free,
1585 .apply = ti_sn_pwm_apply,
1586 .get_state = ti_sn_pwm_get_state,
1587 .owner = THIS_MODULE,
1588 };
1589
ti_sn_pwm_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1590 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1591 const struct auxiliary_device_id *id)
1592 {
1593 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1594
1595 pdata->pchip.dev = pdata->dev;
1596 pdata->pchip.ops = &ti_sn_pwm_ops;
1597 pdata->pchip.npwm = 1;
1598 pdata->pchip.of_xlate = of_pwm_single_xlate;
1599 pdata->pchip.of_pwm_n_cells = 1;
1600
1601 return pwmchip_add(&pdata->pchip);
1602 }
1603
ti_sn_pwm_remove(struct auxiliary_device * adev)1604 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1605 {
1606 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1607
1608 pwmchip_remove(&pdata->pchip);
1609
1610 if (pdata->pwm_enabled)
1611 pm_runtime_put_sync(pdata->dev);
1612 }
1613
1614 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1615 { .name = "ti_sn65dsi86.pwm", },
1616 {},
1617 };
1618
1619 static struct auxiliary_driver ti_sn_pwm_driver = {
1620 .name = "pwm",
1621 .probe = ti_sn_pwm_probe,
1622 .remove = ti_sn_pwm_remove,
1623 .id_table = ti_sn_pwm_id_table,
1624 };
1625
ti_sn_pwm_register(void)1626 static int __init ti_sn_pwm_register(void)
1627 {
1628 return auxiliary_driver_register(&ti_sn_pwm_driver);
1629 }
1630
ti_sn_pwm_unregister(void)1631 static void ti_sn_pwm_unregister(void)
1632 {
1633 auxiliary_driver_unregister(&ti_sn_pwm_driver);
1634 }
1635
1636 #else
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1637 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1638 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1639
ti_sn_pwm_register(void)1640 static inline int ti_sn_pwm_register(void) { return 0; }
ti_sn_pwm_unregister(void)1641 static inline void ti_sn_pwm_unregister(void) {}
1642 #endif
1643
1644 /* -----------------------------------------------------------------------------
1645 * GPIO Controller
1646 */
1647 #if defined(CONFIG_OF_GPIO)
1648
tn_sn_bridge_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpiospec,u32 * flags)1649 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1650 const struct of_phandle_args *gpiospec,
1651 u32 *flags)
1652 {
1653 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1654 return -EINVAL;
1655
1656 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1657 return -EINVAL;
1658
1659 if (flags)
1660 *flags = gpiospec->args[1];
1661
1662 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1663 }
1664
ti_sn_bridge_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1665 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1666 unsigned int offset)
1667 {
1668 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1669
1670 /*
1671 * We already have to keep track of the direction because we use
1672 * that to figure out whether we've powered the device. We can
1673 * just return that rather than (maybe) powering up the device
1674 * to ask its direction.
1675 */
1676 return test_bit(offset, pdata->gchip_output) ?
1677 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1678 }
1679
ti_sn_bridge_gpio_get(struct gpio_chip * chip,unsigned int offset)1680 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1681 {
1682 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1683 unsigned int val;
1684 int ret;
1685
1686 /*
1687 * When the pin is an input we don't forcibly keep the bridge
1688 * powered--we just power it on to read the pin. NOTE: part of
1689 * the reason this works is that the bridge defaults (when
1690 * powered back on) to all 4 GPIOs being configured as GPIO input.
1691 * Also note that if something else is keeping the chip powered the
1692 * pm_runtime functions are lightweight increments of a refcount.
1693 */
1694 pm_runtime_get_sync(pdata->dev);
1695 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1696 pm_runtime_put_autosuspend(pdata->dev);
1697
1698 if (ret)
1699 return ret;
1700
1701 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1702 }
1703
ti_sn_bridge_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1704 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1705 int val)
1706 {
1707 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1708 int ret;
1709
1710 if (!test_bit(offset, pdata->gchip_output)) {
1711 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1712 return;
1713 }
1714
1715 val &= 1;
1716 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1717 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1718 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1719 if (ret)
1720 dev_warn(pdata->dev,
1721 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1722 }
1723
ti_sn_bridge_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1724 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1725 unsigned int offset)
1726 {
1727 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1728 int shift = offset * 2;
1729 int ret;
1730
1731 if (!test_and_clear_bit(offset, pdata->gchip_output))
1732 return 0;
1733
1734 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1735 SN_GPIO_MUX_MASK << shift,
1736 SN_GPIO_MUX_INPUT << shift);
1737 if (ret) {
1738 set_bit(offset, pdata->gchip_output);
1739 return ret;
1740 }
1741
1742 /*
1743 * NOTE: if nobody else is powering the device this may fully power
1744 * it off and when it comes back it will have lost all state, but
1745 * that's OK because the default is input and we're now an input.
1746 */
1747 pm_runtime_put_autosuspend(pdata->dev);
1748
1749 return 0;
1750 }
1751
ti_sn_bridge_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1752 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1753 unsigned int offset, int val)
1754 {
1755 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1756 int shift = offset * 2;
1757 int ret;
1758
1759 if (test_and_set_bit(offset, pdata->gchip_output))
1760 return 0;
1761
1762 pm_runtime_get_sync(pdata->dev);
1763
1764 /* Set value first to avoid glitching */
1765 ti_sn_bridge_gpio_set(chip, offset, val);
1766
1767 /* Set direction */
1768 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1769 SN_GPIO_MUX_MASK << shift,
1770 SN_GPIO_MUX_OUTPUT << shift);
1771 if (ret) {
1772 clear_bit(offset, pdata->gchip_output);
1773 pm_runtime_put_autosuspend(pdata->dev);
1774 }
1775
1776 return ret;
1777 }
1778
ti_sn_bridge_gpio_request(struct gpio_chip * chip,unsigned int offset)1779 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1780 {
1781 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1782
1783 if (offset == SN_PWM_GPIO_IDX)
1784 return ti_sn_pwm_pin_request(pdata);
1785
1786 return 0;
1787 }
1788
ti_sn_bridge_gpio_free(struct gpio_chip * chip,unsigned int offset)1789 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1790 {
1791 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1792
1793 /* We won't keep pm_runtime if we're input, so switch there on free */
1794 ti_sn_bridge_gpio_direction_input(chip, offset);
1795
1796 if (offset == SN_PWM_GPIO_IDX)
1797 ti_sn_pwm_pin_release(pdata);
1798 }
1799
1800 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1801 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1802 };
1803
ti_sn_gpio_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1804 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1805 const struct auxiliary_device_id *id)
1806 {
1807 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1808 int ret;
1809
1810 /* Only init if someone is going to use us as a GPIO controller */
1811 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1812 return 0;
1813
1814 pdata->gchip.label = dev_name(pdata->dev);
1815 pdata->gchip.parent = pdata->dev;
1816 pdata->gchip.owner = THIS_MODULE;
1817 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1818 pdata->gchip.of_gpio_n_cells = 2;
1819 pdata->gchip.request = ti_sn_bridge_gpio_request;
1820 pdata->gchip.free = ti_sn_bridge_gpio_free;
1821 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1822 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1823 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1824 pdata->gchip.get = ti_sn_bridge_gpio_get;
1825 pdata->gchip.set = ti_sn_bridge_gpio_set;
1826 pdata->gchip.can_sleep = true;
1827 pdata->gchip.names = ti_sn_bridge_gpio_names;
1828 pdata->gchip.ngpio = SN_NUM_GPIOS;
1829 pdata->gchip.base = -1;
1830 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1831 if (ret)
1832 dev_err(pdata->dev, "can't add gpio chip\n");
1833
1834 return ret;
1835 }
1836
1837 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1838 { .name = "ti_sn65dsi86.gpio", },
1839 {},
1840 };
1841
1842 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1843
1844 static struct auxiliary_driver ti_sn_gpio_driver = {
1845 .name = "gpio",
1846 .probe = ti_sn_gpio_probe,
1847 .id_table = ti_sn_gpio_id_table,
1848 };
1849
ti_sn_gpio_register(void)1850 static int __init ti_sn_gpio_register(void)
1851 {
1852 return auxiliary_driver_register(&ti_sn_gpio_driver);
1853 }
1854
ti_sn_gpio_unregister(void)1855 static void ti_sn_gpio_unregister(void)
1856 {
1857 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1858 }
1859
1860 #else
1861
ti_sn_gpio_register(void)1862 static inline int ti_sn_gpio_register(void) { return 0; }
ti_sn_gpio_unregister(void)1863 static inline void ti_sn_gpio_unregister(void) {}
1864
1865 #endif
1866
1867 /* -----------------------------------------------------------------------------
1868 * Probe & Remove
1869 */
1870
ti_sn65dsi86_runtime_disable(void * data)1871 static void ti_sn65dsi86_runtime_disable(void *data)
1872 {
1873 pm_runtime_dont_use_autosuspend(data);
1874 pm_runtime_disable(data);
1875 }
1876
ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 * pdata)1877 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1878 {
1879 unsigned int i;
1880 const char * const ti_sn_bridge_supply_names[] = {
1881 "vcca", "vcc", "vccio", "vpll",
1882 };
1883
1884 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1885 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1886
1887 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1888 pdata->supplies);
1889 }
1890
ti_sn65dsi86_probe(struct i2c_client * client)1891 static int ti_sn65dsi86_probe(struct i2c_client *client)
1892 {
1893 struct device *dev = &client->dev;
1894 struct ti_sn65dsi86 *pdata;
1895 int ret;
1896
1897 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1898 DRM_ERROR("device doesn't support I2C\n");
1899 return -ENODEV;
1900 }
1901
1902 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1903 if (!pdata)
1904 return -ENOMEM;
1905 dev_set_drvdata(dev, pdata);
1906 pdata->dev = dev;
1907
1908 mutex_init(&pdata->comms_mutex);
1909
1910 pdata->regmap = devm_regmap_init_i2c(client,
1911 &ti_sn65dsi86_regmap_config);
1912 if (IS_ERR(pdata->regmap))
1913 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1914 "regmap i2c init failed\n");
1915
1916 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1917 GPIOD_OUT_LOW);
1918 if (IS_ERR(pdata->enable_gpio))
1919 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1920 "failed to get enable gpio from DT\n");
1921
1922 ret = ti_sn65dsi86_parse_regulators(pdata);
1923 if (ret)
1924 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1925
1926 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1927 if (IS_ERR(pdata->refclk))
1928 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1929 "failed to get reference clock\n");
1930
1931 pm_runtime_enable(dev);
1932 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1933 pm_runtime_use_autosuspend(pdata->dev);
1934 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1935 if (ret)
1936 return ret;
1937
1938 ti_sn65dsi86_debugfs_init(pdata);
1939
1940 /*
1941 * Break ourselves up into a collection of aux devices. The only real
1942 * motiviation here is to solve the chicken-and-egg problem of probe
1943 * ordering. The bridge wants the panel to be there when it probes.
1944 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1945 * when it probes. The panel and maybe backlight might want the DDC
1946 * bus or the pwm_chip. Having sub-devices allows the some sub devices
1947 * to finish probing even if others return -EPROBE_DEFER and gets us
1948 * around the problems.
1949 */
1950
1951 if (IS_ENABLED(CONFIG_OF_GPIO)) {
1952 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1953 if (ret)
1954 return ret;
1955 }
1956
1957 if (IS_ENABLED(CONFIG_PWM)) {
1958 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1959 if (ret)
1960 return ret;
1961 }
1962
1963 /*
1964 * NOTE: At the end of the AUX channel probe we'll add the aux device
1965 * for the bridge. This is because the bridge can't be used until the
1966 * AUX channel is there and this is a very simple solution to the
1967 * dependency problem.
1968 */
1969 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1970 }
1971
1972 static struct i2c_device_id ti_sn65dsi86_id[] = {
1973 { "ti,sn65dsi86", 0},
1974 {},
1975 };
1976 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1977
1978 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1979 {.compatible = "ti,sn65dsi86"},
1980 {},
1981 };
1982 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1983
1984 static struct i2c_driver ti_sn65dsi86_driver = {
1985 .driver = {
1986 .name = "ti_sn65dsi86",
1987 .of_match_table = ti_sn65dsi86_match_table,
1988 .pm = &ti_sn65dsi86_pm_ops,
1989 },
1990 .probe = ti_sn65dsi86_probe,
1991 .id_table = ti_sn65dsi86_id,
1992 };
1993
ti_sn65dsi86_init(void)1994 static int __init ti_sn65dsi86_init(void)
1995 {
1996 int ret;
1997
1998 ret = i2c_add_driver(&ti_sn65dsi86_driver);
1999 if (ret)
2000 return ret;
2001
2002 ret = ti_sn_gpio_register();
2003 if (ret)
2004 goto err_main_was_registered;
2005
2006 ret = ti_sn_pwm_register();
2007 if (ret)
2008 goto err_gpio_was_registered;
2009
2010 ret = auxiliary_driver_register(&ti_sn_aux_driver);
2011 if (ret)
2012 goto err_pwm_was_registered;
2013
2014 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
2015 if (ret)
2016 goto err_aux_was_registered;
2017
2018 return 0;
2019
2020 err_aux_was_registered:
2021 auxiliary_driver_unregister(&ti_sn_aux_driver);
2022 err_pwm_was_registered:
2023 ti_sn_pwm_unregister();
2024 err_gpio_was_registered:
2025 ti_sn_gpio_unregister();
2026 err_main_was_registered:
2027 i2c_del_driver(&ti_sn65dsi86_driver);
2028
2029 return ret;
2030 }
2031 module_init(ti_sn65dsi86_init);
2032
ti_sn65dsi86_exit(void)2033 static void __exit ti_sn65dsi86_exit(void)
2034 {
2035 auxiliary_driver_unregister(&ti_sn_bridge_driver);
2036 auxiliary_driver_unregister(&ti_sn_aux_driver);
2037 ti_sn_pwm_unregister();
2038 ti_sn_gpio_unregister();
2039 i2c_del_driver(&ti_sn65dsi86_driver);
2040 }
2041 module_exit(ti_sn65dsi86_exit);
2042
2043 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
2044 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2045 MODULE_LICENSE("GPL v2");
2046