1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
33
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
37
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
43
44 /**
45 * struct panel_desc - Describes a simple panel.
46 */
47 struct panel_desc {
48 /**
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
50 *
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
54 */
55 const struct drm_display_mode *modes;
56
57 /** @num_modes: Number of elements in modes array. */
58 unsigned int num_modes;
59
60 /**
61 * @timings: Pointer to array of display timings
62 *
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
65 */
66 const struct display_timing *timings;
67
68 /** @num_timings: Number of elements in timings array. */
69 unsigned int num_timings;
70
71 /** @bpc: Bits per color. */
72 unsigned int bpc;
73
74 /** @size: Structure containing the physical size of this panel. */
75 struct {
76 /**
77 * @size.width: Width (in mm) of the active display area.
78 */
79 unsigned int width;
80
81 /**
82 * @size.height: Height (in mm) of the active display area.
83 */
84 unsigned int height;
85 } size;
86
87 /** @delay: Structure containing various delay values for this panel. */
88 struct {
89 /**
90 * @delay.prepare: Time for the panel to become ready.
91 *
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
94 */
95 unsigned int prepare;
96
97 /**
98 * @delay.enable: Time for the panel to display a valid frame.
99 *
100 * The time (in milliseconds) that it takes for the panel to
101 * display the first valid frame after starting to receive
102 * video data.
103 */
104 unsigned int enable;
105
106 /**
107 * @delay.disable: Time for the panel to turn the display off.
108 *
109 * The time (in milliseconds) that it takes for the panel to
110 * turn the display off (no content is visible).
111 */
112 unsigned int disable;
113
114 /**
115 * @delay.unprepare: Time to power down completely.
116 *
117 * The time (in milliseconds) that it takes for the panel
118 * to power itself down completely.
119 *
120 * This time is used to prevent a future "prepare" from
121 * starting until at least this many milliseconds has passed.
122 * If at prepare time less time has passed since unprepare
123 * finished, the driver waits for the remaining time.
124 */
125 unsigned int unprepare;
126 } delay;
127
128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
129 u32 bus_format;
130
131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
132 u32 bus_flags;
133
134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
135 int connector_type;
136 };
137
138 struct panel_simple {
139 struct drm_panel base;
140 bool enabled;
141
142 bool prepared;
143
144 ktime_t unprepared_time;
145
146 const struct panel_desc *desc;
147
148 struct regulator *supply;
149 struct i2c_adapter *ddc;
150
151 struct gpio_desc *enable_gpio;
152
153 struct edid *edid;
154
155 struct drm_display_mode override_mode;
156
157 enum drm_panel_orientation orientation;
158 };
159
to_panel_simple(struct drm_panel * panel)160 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
161 {
162 return container_of(panel, struct panel_simple, base);
163 }
164
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)165 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
166 struct drm_connector *connector)
167 {
168 struct drm_display_mode *mode;
169 unsigned int i, num = 0;
170
171 for (i = 0; i < panel->desc->num_timings; i++) {
172 const struct display_timing *dt = &panel->desc->timings[i];
173 struct videomode vm;
174
175 videomode_from_timing(dt, &vm);
176 mode = drm_mode_create(connector->dev);
177 if (!mode) {
178 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
179 dt->hactive.typ, dt->vactive.typ);
180 continue;
181 }
182
183 drm_display_mode_from_videomode(&vm, mode);
184
185 mode->type |= DRM_MODE_TYPE_DRIVER;
186
187 if (panel->desc->num_timings == 1)
188 mode->type |= DRM_MODE_TYPE_PREFERRED;
189
190 drm_mode_probed_add(connector, mode);
191 num++;
192 }
193
194 return num;
195 }
196
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)197 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
198 struct drm_connector *connector)
199 {
200 struct drm_display_mode *mode;
201 unsigned int i, num = 0;
202
203 for (i = 0; i < panel->desc->num_modes; i++) {
204 const struct drm_display_mode *m = &panel->desc->modes[i];
205
206 mode = drm_mode_duplicate(connector->dev, m);
207 if (!mode) {
208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
209 m->hdisplay, m->vdisplay,
210 drm_mode_vrefresh(m));
211 continue;
212 }
213
214 mode->type |= DRM_MODE_TYPE_DRIVER;
215
216 if (panel->desc->num_modes == 1)
217 mode->type |= DRM_MODE_TYPE_PREFERRED;
218
219 drm_mode_set_name(mode);
220
221 drm_mode_probed_add(connector, mode);
222 num++;
223 }
224
225 return num;
226 }
227
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)228 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
229 struct drm_connector *connector)
230 {
231 struct drm_display_mode *mode;
232 bool has_override = panel->override_mode.type;
233 unsigned int num = 0;
234
235 if (!panel->desc)
236 return 0;
237
238 if (has_override) {
239 mode = drm_mode_duplicate(connector->dev,
240 &panel->override_mode);
241 if (mode) {
242 drm_mode_probed_add(connector, mode);
243 num = 1;
244 } else {
245 dev_err(panel->base.dev, "failed to add override mode\n");
246 }
247 }
248
249 /* Only add timings if override was not there or failed to validate */
250 if (num == 0 && panel->desc->num_timings)
251 num = panel_simple_get_timings_modes(panel, connector);
252
253 /*
254 * Only add fixed modes if timings/override added no mode.
255 *
256 * We should only ever have either the display timings specified
257 * or a fixed mode. Anything else is rather bogus.
258 */
259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
260 if (num == 0)
261 num = panel_simple_get_display_modes(panel, connector);
262
263 connector->display_info.bpc = panel->desc->bpc;
264 connector->display_info.width_mm = panel->desc->size.width;
265 connector->display_info.height_mm = panel->desc->size.height;
266 if (panel->desc->bus_format)
267 drm_display_info_set_bus_formats(&connector->display_info,
268 &panel->desc->bus_format, 1);
269 connector->display_info.bus_flags = panel->desc->bus_flags;
270
271 return num;
272 }
273
panel_simple_wait(ktime_t start_ktime,unsigned int min_ms)274 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
275 {
276 ktime_t now_ktime, min_ktime;
277
278 if (!min_ms)
279 return;
280
281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
282 now_ktime = ktime_get_boottime();
283
284 if (ktime_before(now_ktime, min_ktime))
285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
286 }
287
panel_simple_disable(struct drm_panel * panel)288 static int panel_simple_disable(struct drm_panel *panel)
289 {
290 struct panel_simple *p = to_panel_simple(panel);
291
292 if (!p->enabled)
293 return 0;
294
295 if (p->desc->delay.disable)
296 msleep(p->desc->delay.disable);
297
298 p->enabled = false;
299
300 return 0;
301 }
302
panel_simple_suspend(struct device * dev)303 static int panel_simple_suspend(struct device *dev)
304 {
305 struct panel_simple *p = dev_get_drvdata(dev);
306
307 gpiod_set_value_cansleep(p->enable_gpio, 0);
308 regulator_disable(p->supply);
309 p->unprepared_time = ktime_get_boottime();
310
311 kfree(p->edid);
312 p->edid = NULL;
313
314 return 0;
315 }
316
panel_simple_unprepare(struct drm_panel * panel)317 static int panel_simple_unprepare(struct drm_panel *panel)
318 {
319 struct panel_simple *p = to_panel_simple(panel);
320 int ret;
321
322 /* Unpreparing when already unprepared is a no-op */
323 if (!p->prepared)
324 return 0;
325
326 pm_runtime_mark_last_busy(panel->dev);
327 ret = pm_runtime_put_autosuspend(panel->dev);
328 if (ret < 0)
329 return ret;
330 p->prepared = false;
331
332 return 0;
333 }
334
panel_simple_resume(struct device * dev)335 static int panel_simple_resume(struct device *dev)
336 {
337 struct panel_simple *p = dev_get_drvdata(dev);
338 int err;
339
340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
341
342 err = regulator_enable(p->supply);
343 if (err < 0) {
344 dev_err(dev, "failed to enable supply: %d\n", err);
345 return err;
346 }
347
348 gpiod_set_value_cansleep(p->enable_gpio, 1);
349
350 if (p->desc->delay.prepare)
351 msleep(p->desc->delay.prepare);
352
353 return 0;
354 }
355
panel_simple_prepare(struct drm_panel * panel)356 static int panel_simple_prepare(struct drm_panel *panel)
357 {
358 struct panel_simple *p = to_panel_simple(panel);
359 int ret;
360
361 /* Preparing when already prepared is a no-op */
362 if (p->prepared)
363 return 0;
364
365 ret = pm_runtime_get_sync(panel->dev);
366 if (ret < 0) {
367 pm_runtime_put_autosuspend(panel->dev);
368 return ret;
369 }
370
371 p->prepared = true;
372
373 return 0;
374 }
375
panel_simple_enable(struct drm_panel * panel)376 static int panel_simple_enable(struct drm_panel *panel)
377 {
378 struct panel_simple *p = to_panel_simple(panel);
379
380 if (p->enabled)
381 return 0;
382
383 if (p->desc->delay.enable)
384 msleep(p->desc->delay.enable);
385
386 p->enabled = true;
387
388 return 0;
389 }
390
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)391 static int panel_simple_get_modes(struct drm_panel *panel,
392 struct drm_connector *connector)
393 {
394 struct panel_simple *p = to_panel_simple(panel);
395 int num = 0;
396
397 /* probe EDID if a DDC bus is available */
398 if (p->ddc) {
399 pm_runtime_get_sync(panel->dev);
400
401 if (!p->edid)
402 p->edid = drm_get_edid(connector, p->ddc);
403
404 if (p->edid)
405 num += drm_add_edid_modes(connector, p->edid);
406
407 pm_runtime_mark_last_busy(panel->dev);
408 pm_runtime_put_autosuspend(panel->dev);
409 }
410
411 /* add hard-coded panel modes */
412 num += panel_simple_get_non_edid_modes(p, connector);
413
414 /*
415 * TODO: Remove once all drm drivers call
416 * drm_connector_set_orientation_from_panel()
417 */
418 drm_connector_set_panel_orientation(connector, p->orientation);
419
420 return num;
421 }
422
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)423 static int panel_simple_get_timings(struct drm_panel *panel,
424 unsigned int num_timings,
425 struct display_timing *timings)
426 {
427 struct panel_simple *p = to_panel_simple(panel);
428 unsigned int i;
429
430 if (p->desc->num_timings < num_timings)
431 num_timings = p->desc->num_timings;
432
433 if (timings)
434 for (i = 0; i < num_timings; i++)
435 timings[i] = p->desc->timings[i];
436
437 return p->desc->num_timings;
438 }
439
panel_simple_get_orientation(struct drm_panel * panel)440 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
441 {
442 struct panel_simple *p = to_panel_simple(panel);
443
444 return p->orientation;
445 }
446
447 static const struct drm_panel_funcs panel_simple_funcs = {
448 .disable = panel_simple_disable,
449 .unprepare = panel_simple_unprepare,
450 .prepare = panel_simple_prepare,
451 .enable = panel_simple_enable,
452 .get_modes = panel_simple_get_modes,
453 .get_orientation = panel_simple_get_orientation,
454 .get_timings = panel_simple_get_timings,
455 };
456
457 static struct panel_desc panel_dpi;
458
panel_dpi_probe(struct device * dev,struct panel_simple * panel)459 static int panel_dpi_probe(struct device *dev,
460 struct panel_simple *panel)
461 {
462 struct display_timing *timing;
463 const struct device_node *np;
464 struct panel_desc *desc;
465 unsigned int bus_flags;
466 struct videomode vm;
467 int ret;
468
469 np = dev->of_node;
470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
471 if (!desc)
472 return -ENOMEM;
473
474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
475 if (!timing)
476 return -ENOMEM;
477
478 ret = of_get_display_timing(np, "panel-timing", timing);
479 if (ret < 0) {
480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
481 np);
482 return ret;
483 }
484
485 desc->timings = timing;
486 desc->num_timings = 1;
487
488 of_property_read_u32(np, "width-mm", &desc->size.width);
489 of_property_read_u32(np, "height-mm", &desc->size.height);
490
491 /* Extract bus_flags from display_timing */
492 bus_flags = 0;
493 vm.flags = timing->flags;
494 drm_bus_flags_from_videomode(&vm, &bus_flags);
495 desc->bus_flags = bus_flags;
496
497 /* We do not know the connector for the DT node, so guess it */
498 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
499
500 panel->desc = desc;
501
502 return 0;
503 }
504
505 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
506 (to_check->field.typ >= bounds->field.min && \
507 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)508 static void panel_simple_parse_panel_timing_node(struct device *dev,
509 struct panel_simple *panel,
510 const struct display_timing *ot)
511 {
512 const struct panel_desc *desc = panel->desc;
513 struct videomode vm;
514 unsigned int i;
515
516 if (WARN_ON(desc->num_modes)) {
517 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
518 return;
519 }
520 if (WARN_ON(!desc->num_timings)) {
521 dev_err(dev, "Reject override mode: no timings specified\n");
522 return;
523 }
524
525 for (i = 0; i < panel->desc->num_timings; i++) {
526 const struct display_timing *dt = &panel->desc->timings[i];
527
528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
536 continue;
537
538 if (ot->flags != dt->flags)
539 continue;
540
541 videomode_from_timing(ot, &vm);
542 drm_display_mode_from_videomode(&vm, &panel->override_mode);
543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
544 DRM_MODE_TYPE_PREFERRED;
545 break;
546 }
547
548 if (WARN_ON(!panel->override_mode.type))
549 dev_err(dev, "Reject override mode: No display_timing found\n");
550 }
551
panel_simple_probe(struct device * dev,const struct panel_desc * desc)552 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
553 {
554 struct panel_simple *panel;
555 struct display_timing dt;
556 struct device_node *ddc;
557 int connector_type;
558 u32 bus_flags;
559 int err;
560
561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
562 if (!panel)
563 return -ENOMEM;
564
565 panel->enabled = false;
566 panel->desc = desc;
567
568 panel->supply = devm_regulator_get(dev, "power");
569 if (IS_ERR(panel->supply))
570 return PTR_ERR(panel->supply);
571
572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
573 GPIOD_OUT_LOW);
574 if (IS_ERR(panel->enable_gpio))
575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
576 "failed to request GPIO\n");
577
578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
579 if (err) {
580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
581 return err;
582 }
583
584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
585 if (ddc) {
586 panel->ddc = of_find_i2c_adapter_by_node(ddc);
587 of_node_put(ddc);
588
589 if (!panel->ddc)
590 return -EPROBE_DEFER;
591 }
592
593 if (desc == &panel_dpi) {
594 /* Handle the generic panel-dpi binding */
595 err = panel_dpi_probe(dev, panel);
596 if (err)
597 goto free_ddc;
598 desc = panel->desc;
599 } else {
600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
601 panel_simple_parse_panel_timing_node(dev, panel, &dt);
602 }
603
604 connector_type = desc->connector_type;
605 /* Catch common mistakes for panels. */
606 switch (connector_type) {
607 case 0:
608 dev_warn(dev, "Specify missing connector_type\n");
609 connector_type = DRM_MODE_CONNECTOR_DPI;
610 break;
611 case DRM_MODE_CONNECTOR_LVDS:
612 WARN_ON(desc->bus_flags &
613 ~(DRM_BUS_FLAG_DE_LOW |
614 DRM_BUS_FLAG_DE_HIGH |
615 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
616 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
621 desc->bpc != 6);
622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
624 desc->bpc != 8);
625 break;
626 case DRM_MODE_CONNECTOR_eDP:
627 dev_warn(dev, "eDP panels moved to panel-edp\n");
628 err = -EINVAL;
629 goto free_ddc;
630 case DRM_MODE_CONNECTOR_DSI:
631 if (desc->bpc != 6 && desc->bpc != 8)
632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
633 break;
634 case DRM_MODE_CONNECTOR_DPI:
635 bus_flags = DRM_BUS_FLAG_DE_LOW |
636 DRM_BUS_FLAG_DE_HIGH |
637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
639 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
640 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
643 if (desc->bus_flags & ~bus_flags)
644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
645 if (!(desc->bus_flags & bus_flags))
646 dev_warn(dev, "Specify missing bus_flags\n");
647 if (desc->bus_format == 0)
648 dev_warn(dev, "Specify missing bus_format\n");
649 if (desc->bpc != 6 && desc->bpc != 8)
650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
651 break;
652 default:
653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
654 connector_type = DRM_MODE_CONNECTOR_DPI;
655 break;
656 }
657
658 dev_set_drvdata(dev, panel);
659
660 /*
661 * We use runtime PM for prepare / unprepare since those power the panel
662 * on and off and those can be very slow operations. This is important
663 * to optimize powering the panel on briefly to read the EDID before
664 * fully enabling the panel.
665 */
666 pm_runtime_enable(dev);
667 pm_runtime_set_autosuspend_delay(dev, 1000);
668 pm_runtime_use_autosuspend(dev);
669
670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
671
672 err = drm_panel_of_backlight(&panel->base);
673 if (err) {
674 dev_err_probe(dev, err, "Could not find backlight\n");
675 goto disable_pm_runtime;
676 }
677
678 drm_panel_add(&panel->base);
679
680 return 0;
681
682 disable_pm_runtime:
683 pm_runtime_dont_use_autosuspend(dev);
684 pm_runtime_disable(dev);
685 free_ddc:
686 if (panel->ddc)
687 put_device(&panel->ddc->dev);
688
689 return err;
690 }
691
panel_simple_remove(struct device * dev)692 static void panel_simple_remove(struct device *dev)
693 {
694 struct panel_simple *panel = dev_get_drvdata(dev);
695
696 drm_panel_remove(&panel->base);
697 drm_panel_disable(&panel->base);
698 drm_panel_unprepare(&panel->base);
699
700 pm_runtime_dont_use_autosuspend(dev);
701 pm_runtime_disable(dev);
702 if (panel->ddc)
703 put_device(&panel->ddc->dev);
704 }
705
panel_simple_shutdown(struct device * dev)706 static void panel_simple_shutdown(struct device *dev)
707 {
708 struct panel_simple *panel = dev_get_drvdata(dev);
709
710 drm_panel_disable(&panel->base);
711 drm_panel_unprepare(&panel->base);
712 }
713
714 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
715 .clock = 71100,
716 .hdisplay = 1280,
717 .hsync_start = 1280 + 40,
718 .hsync_end = 1280 + 40 + 80,
719 .htotal = 1280 + 40 + 80 + 40,
720 .vdisplay = 800,
721 .vsync_start = 800 + 3,
722 .vsync_end = 800 + 3 + 10,
723 .vtotal = 800 + 3 + 10 + 10,
724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
725 };
726
727 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
728 .modes = &ire_am_1280800n3tzqw_t00h_mode,
729 .num_modes = 1,
730 .bpc = 8,
731 .size = {
732 .width = 217,
733 .height = 136,
734 },
735 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
737 .connector_type = DRM_MODE_CONNECTOR_LVDS,
738 };
739
740 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
741 .clock = 9000,
742 .hdisplay = 480,
743 .hsync_start = 480 + 2,
744 .hsync_end = 480 + 2 + 41,
745 .htotal = 480 + 2 + 41 + 2,
746 .vdisplay = 272,
747 .vsync_start = 272 + 2,
748 .vsync_end = 272 + 2 + 10,
749 .vtotal = 272 + 2 + 10 + 2,
750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
751 };
752
753 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
754 .modes = &ire_am_480272h3tmqw_t01h_mode,
755 .num_modes = 1,
756 .bpc = 8,
757 .size = {
758 .width = 99,
759 .height = 58,
760 },
761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
762 };
763
764 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
765 .clock = 33333,
766 .hdisplay = 800,
767 .hsync_start = 800 + 0,
768 .hsync_end = 800 + 0 + 255,
769 .htotal = 800 + 0 + 255 + 0,
770 .vdisplay = 480,
771 .vsync_start = 480 + 2,
772 .vsync_end = 480 + 2 + 45,
773 .vtotal = 480 + 2 + 45 + 0,
774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
775 };
776
777 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
778 .pixelclock = { 29930000, 33260000, 36590000 },
779 .hactive = { 800, 800, 800 },
780 .hfront_porch = { 1, 40, 168 },
781 .hback_porch = { 88, 88, 88 },
782 .hsync_len = { 1, 128, 128 },
783 .vactive = { 480, 480, 480 },
784 .vfront_porch = { 1, 35, 37 },
785 .vback_porch = { 8, 8, 8 },
786 .vsync_len = { 1, 2, 2 },
787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
789 DISPLAY_FLAGS_SYNC_POSEDGE,
790 };
791
792 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
793 .timings = &ire_am_800480l1tmqw_t00h_timing,
794 .num_timings = 1,
795 .bpc = 8,
796 .size = {
797 .width = 111,
798 .height = 67,
799 },
800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
801 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
804 .connector_type = DRM_MODE_CONNECTOR_DPI,
805 };
806
807 static const struct panel_desc ampire_am800480r3tmqwa1h = {
808 .modes = &ire_am800480r3tmqwa1h_mode,
809 .num_modes = 1,
810 .bpc = 6,
811 .size = {
812 .width = 152,
813 .height = 91,
814 },
815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
816 };
817
818 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
819 .pixelclock = { 34500000, 39600000, 50400000 },
820 .hactive = { 800, 800, 800 },
821 .hfront_porch = { 12, 112, 312 },
822 .hback_porch = { 87, 87, 48 },
823 .hsync_len = { 1, 1, 40 },
824 .vactive = { 600, 600, 600 },
825 .vfront_porch = { 1, 21, 61 },
826 .vback_porch = { 38, 38, 19 },
827 .vsync_len = { 1, 1, 20 },
828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
830 DISPLAY_FLAGS_SYNC_POSEDGE,
831 };
832
833 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
834 .timings = &ire_am800600p5tmqw_tb8h_timing,
835 .num_timings = 1,
836 .bpc = 6,
837 .size = {
838 .width = 162,
839 .height = 122,
840 },
841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
842 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
845 .connector_type = DRM_MODE_CONNECTOR_DPI,
846 };
847
848 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
849 .pixelclock = { 26400000, 33300000, 46800000 },
850 .hactive = { 800, 800, 800 },
851 .hfront_porch = { 16, 210, 354 },
852 .hback_porch = { 45, 36, 6 },
853 .hsync_len = { 1, 10, 40 },
854 .vactive = { 480, 480, 480 },
855 .vfront_porch = { 7, 22, 147 },
856 .vback_porch = { 22, 13, 3 },
857 .vsync_len = { 1, 10, 20 },
858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
860 };
861
862 static const struct panel_desc armadeus_st0700_adapt = {
863 .timings = &santek_st0700i5y_rbslw_f_timing,
864 .num_timings = 1,
865 .bpc = 6,
866 .size = {
867 .width = 154,
868 .height = 86,
869 },
870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
872 };
873
874 static const struct drm_display_mode auo_b101aw03_mode = {
875 .clock = 51450,
876 .hdisplay = 1024,
877 .hsync_start = 1024 + 156,
878 .hsync_end = 1024 + 156 + 8,
879 .htotal = 1024 + 156 + 8 + 156,
880 .vdisplay = 600,
881 .vsync_start = 600 + 16,
882 .vsync_end = 600 + 16 + 6,
883 .vtotal = 600 + 16 + 6 + 16,
884 };
885
886 static const struct panel_desc auo_b101aw03 = {
887 .modes = &auo_b101aw03_mode,
888 .num_modes = 1,
889 .bpc = 6,
890 .size = {
891 .width = 223,
892 .height = 125,
893 },
894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
895 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
896 .connector_type = DRM_MODE_CONNECTOR_LVDS,
897 };
898
899 static const struct drm_display_mode auo_b101xtn01_mode = {
900 .clock = 72000,
901 .hdisplay = 1366,
902 .hsync_start = 1366 + 20,
903 .hsync_end = 1366 + 20 + 70,
904 .htotal = 1366 + 20 + 70,
905 .vdisplay = 768,
906 .vsync_start = 768 + 14,
907 .vsync_end = 768 + 14 + 42,
908 .vtotal = 768 + 14 + 42,
909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
910 };
911
912 static const struct panel_desc auo_b101xtn01 = {
913 .modes = &auo_b101xtn01_mode,
914 .num_modes = 1,
915 .bpc = 6,
916 .size = {
917 .width = 223,
918 .height = 125,
919 },
920 };
921
922 static const struct drm_display_mode auo_b116xw03_mode = {
923 .clock = 70589,
924 .hdisplay = 1366,
925 .hsync_start = 1366 + 40,
926 .hsync_end = 1366 + 40 + 40,
927 .htotal = 1366 + 40 + 40 + 32,
928 .vdisplay = 768,
929 .vsync_start = 768 + 10,
930 .vsync_end = 768 + 10 + 12,
931 .vtotal = 768 + 10 + 12 + 6,
932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
933 };
934
935 static const struct panel_desc auo_b116xw03 = {
936 .modes = &auo_b116xw03_mode,
937 .num_modes = 1,
938 .bpc = 6,
939 .size = {
940 .width = 256,
941 .height = 144,
942 },
943 .delay = {
944 .prepare = 1,
945 .enable = 200,
946 .disable = 200,
947 .unprepare = 500,
948 },
949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
950 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
951 .connector_type = DRM_MODE_CONNECTOR_LVDS,
952 };
953
954 static const struct display_timing auo_g070vvn01_timings = {
955 .pixelclock = { 33300000, 34209000, 45000000 },
956 .hactive = { 800, 800, 800 },
957 .hfront_porch = { 20, 40, 200 },
958 .hback_porch = { 87, 40, 1 },
959 .hsync_len = { 1, 48, 87 },
960 .vactive = { 480, 480, 480 },
961 .vfront_porch = { 5, 13, 200 },
962 .vback_porch = { 31, 31, 29 },
963 .vsync_len = { 1, 1, 3 },
964 };
965
966 static const struct panel_desc auo_g070vvn01 = {
967 .timings = &auo_g070vvn01_timings,
968 .num_timings = 1,
969 .bpc = 8,
970 .size = {
971 .width = 152,
972 .height = 91,
973 },
974 .delay = {
975 .prepare = 200,
976 .enable = 50,
977 .disable = 50,
978 .unprepare = 1000,
979 },
980 };
981
982 static const struct drm_display_mode auo_g101evn010_mode = {
983 .clock = 68930,
984 .hdisplay = 1280,
985 .hsync_start = 1280 + 82,
986 .hsync_end = 1280 + 82 + 2,
987 .htotal = 1280 + 82 + 2 + 84,
988 .vdisplay = 800,
989 .vsync_start = 800 + 8,
990 .vsync_end = 800 + 8 + 2,
991 .vtotal = 800 + 8 + 2 + 6,
992 };
993
994 static const struct panel_desc auo_g101evn010 = {
995 .modes = &auo_g101evn010_mode,
996 .num_modes = 1,
997 .bpc = 6,
998 .size = {
999 .width = 216,
1000 .height = 135,
1001 },
1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1003 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1004 };
1005
1006 static const struct drm_display_mode auo_g104sn02_mode = {
1007 .clock = 40000,
1008 .hdisplay = 800,
1009 .hsync_start = 800 + 40,
1010 .hsync_end = 800 + 40 + 216,
1011 .htotal = 800 + 40 + 216 + 128,
1012 .vdisplay = 600,
1013 .vsync_start = 600 + 10,
1014 .vsync_end = 600 + 10 + 35,
1015 .vtotal = 600 + 10 + 35 + 2,
1016 };
1017
1018 static const struct panel_desc auo_g104sn02 = {
1019 .modes = &auo_g104sn02_mode,
1020 .num_modes = 1,
1021 .bpc = 8,
1022 .size = {
1023 .width = 211,
1024 .height = 158,
1025 },
1026 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1027 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1028 };
1029
1030 static const struct display_timing auo_g121ean01_timing = {
1031 .pixelclock = { 60000000, 74400000, 90000000 },
1032 .hactive = { 1280, 1280, 1280 },
1033 .hfront_porch = { 20, 50, 100 },
1034 .hback_porch = { 20, 50, 100 },
1035 .hsync_len = { 30, 100, 200 },
1036 .vactive = { 800, 800, 800 },
1037 .vfront_porch = { 2, 10, 25 },
1038 .vback_porch = { 2, 10, 25 },
1039 .vsync_len = { 4, 18, 50 },
1040 };
1041
1042 static const struct panel_desc auo_g121ean01 = {
1043 .timings = &auo_g121ean01_timing,
1044 .num_timings = 1,
1045 .bpc = 8,
1046 .size = {
1047 .width = 261,
1048 .height = 163,
1049 },
1050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1051 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1052 };
1053
1054 static const struct display_timing auo_g133han01_timings = {
1055 .pixelclock = { 134000000, 141200000, 149000000 },
1056 .hactive = { 1920, 1920, 1920 },
1057 .hfront_porch = { 39, 58, 77 },
1058 .hback_porch = { 59, 88, 117 },
1059 .hsync_len = { 28, 42, 56 },
1060 .vactive = { 1080, 1080, 1080 },
1061 .vfront_porch = { 3, 8, 11 },
1062 .vback_porch = { 5, 14, 19 },
1063 .vsync_len = { 4, 14, 19 },
1064 };
1065
1066 static const struct panel_desc auo_g133han01 = {
1067 .timings = &auo_g133han01_timings,
1068 .num_timings = 1,
1069 .bpc = 8,
1070 .size = {
1071 .width = 293,
1072 .height = 165,
1073 },
1074 .delay = {
1075 .prepare = 200,
1076 .enable = 50,
1077 .disable = 50,
1078 .unprepare = 1000,
1079 },
1080 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1081 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1082 };
1083
1084 static const struct drm_display_mode auo_g156xtn01_mode = {
1085 .clock = 76000,
1086 .hdisplay = 1366,
1087 .hsync_start = 1366 + 33,
1088 .hsync_end = 1366 + 33 + 67,
1089 .htotal = 1560,
1090 .vdisplay = 768,
1091 .vsync_start = 768 + 4,
1092 .vsync_end = 768 + 4 + 4,
1093 .vtotal = 806,
1094 };
1095
1096 static const struct panel_desc auo_g156xtn01 = {
1097 .modes = &auo_g156xtn01_mode,
1098 .num_modes = 1,
1099 .bpc = 8,
1100 .size = {
1101 .width = 344,
1102 .height = 194,
1103 },
1104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1105 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1106 };
1107
1108 static const struct display_timing auo_g185han01_timings = {
1109 .pixelclock = { 120000000, 144000000, 175000000 },
1110 .hactive = { 1920, 1920, 1920 },
1111 .hfront_porch = { 36, 120, 148 },
1112 .hback_porch = { 24, 88, 108 },
1113 .hsync_len = { 20, 48, 64 },
1114 .vactive = { 1080, 1080, 1080 },
1115 .vfront_porch = { 6, 10, 40 },
1116 .vback_porch = { 2, 5, 20 },
1117 .vsync_len = { 2, 5, 20 },
1118 };
1119
1120 static const struct panel_desc auo_g185han01 = {
1121 .timings = &auo_g185han01_timings,
1122 .num_timings = 1,
1123 .bpc = 8,
1124 .size = {
1125 .width = 409,
1126 .height = 230,
1127 },
1128 .delay = {
1129 .prepare = 50,
1130 .enable = 200,
1131 .disable = 110,
1132 .unprepare = 1000,
1133 },
1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1135 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1136 };
1137
1138 static const struct display_timing auo_g190ean01_timings = {
1139 .pixelclock = { 90000000, 108000000, 135000000 },
1140 .hactive = { 1280, 1280, 1280 },
1141 .hfront_porch = { 126, 184, 1266 },
1142 .hback_porch = { 84, 122, 844 },
1143 .hsync_len = { 70, 102, 704 },
1144 .vactive = { 1024, 1024, 1024 },
1145 .vfront_porch = { 4, 26, 76 },
1146 .vback_porch = { 2, 8, 25 },
1147 .vsync_len = { 2, 8, 25 },
1148 };
1149
1150 static const struct panel_desc auo_g190ean01 = {
1151 .timings = &auo_g190ean01_timings,
1152 .num_timings = 1,
1153 .bpc = 8,
1154 .size = {
1155 .width = 376,
1156 .height = 301,
1157 },
1158 .delay = {
1159 .prepare = 50,
1160 .enable = 200,
1161 .disable = 110,
1162 .unprepare = 1000,
1163 },
1164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1165 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1166 };
1167
1168 static const struct display_timing auo_p320hvn03_timings = {
1169 .pixelclock = { 106000000, 148500000, 164000000 },
1170 .hactive = { 1920, 1920, 1920 },
1171 .hfront_porch = { 25, 50, 130 },
1172 .hback_porch = { 25, 50, 130 },
1173 .hsync_len = { 20, 40, 105 },
1174 .vactive = { 1080, 1080, 1080 },
1175 .vfront_porch = { 8, 17, 150 },
1176 .vback_porch = { 8, 17, 150 },
1177 .vsync_len = { 4, 11, 100 },
1178 };
1179
1180 static const struct panel_desc auo_p320hvn03 = {
1181 .timings = &auo_p320hvn03_timings,
1182 .num_timings = 1,
1183 .bpc = 8,
1184 .size = {
1185 .width = 698,
1186 .height = 393,
1187 },
1188 .delay = {
1189 .prepare = 1,
1190 .enable = 450,
1191 .unprepare = 500,
1192 },
1193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1194 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1195 };
1196
1197 static const struct drm_display_mode auo_t215hvn01_mode = {
1198 .clock = 148800,
1199 .hdisplay = 1920,
1200 .hsync_start = 1920 + 88,
1201 .hsync_end = 1920 + 88 + 44,
1202 .htotal = 1920 + 88 + 44 + 148,
1203 .vdisplay = 1080,
1204 .vsync_start = 1080 + 4,
1205 .vsync_end = 1080 + 4 + 5,
1206 .vtotal = 1080 + 4 + 5 + 36,
1207 };
1208
1209 static const struct panel_desc auo_t215hvn01 = {
1210 .modes = &auo_t215hvn01_mode,
1211 .num_modes = 1,
1212 .bpc = 8,
1213 .size = {
1214 .width = 430,
1215 .height = 270,
1216 },
1217 .delay = {
1218 .disable = 5,
1219 .unprepare = 1000,
1220 },
1221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1222 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1223 };
1224
1225 static const struct drm_display_mode avic_tm070ddh03_mode = {
1226 .clock = 51200,
1227 .hdisplay = 1024,
1228 .hsync_start = 1024 + 160,
1229 .hsync_end = 1024 + 160 + 4,
1230 .htotal = 1024 + 160 + 4 + 156,
1231 .vdisplay = 600,
1232 .vsync_start = 600 + 17,
1233 .vsync_end = 600 + 17 + 1,
1234 .vtotal = 600 + 17 + 1 + 17,
1235 };
1236
1237 static const struct panel_desc avic_tm070ddh03 = {
1238 .modes = &avic_tm070ddh03_mode,
1239 .num_modes = 1,
1240 .bpc = 8,
1241 .size = {
1242 .width = 154,
1243 .height = 90,
1244 },
1245 .delay = {
1246 .prepare = 20,
1247 .enable = 200,
1248 .disable = 200,
1249 },
1250 };
1251
1252 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1253 .clock = 30000,
1254 .hdisplay = 800,
1255 .hsync_start = 800 + 40,
1256 .hsync_end = 800 + 40 + 48,
1257 .htotal = 800 + 40 + 48 + 40,
1258 .vdisplay = 480,
1259 .vsync_start = 480 + 13,
1260 .vsync_end = 480 + 13 + 3,
1261 .vtotal = 480 + 13 + 3 + 29,
1262 };
1263
1264 static const struct panel_desc bananapi_s070wv20_ct16 = {
1265 .modes = &bananapi_s070wv20_ct16_mode,
1266 .num_modes = 1,
1267 .bpc = 6,
1268 .size = {
1269 .width = 154,
1270 .height = 86,
1271 },
1272 };
1273
1274 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1275 .pixelclock = { 69922000, 71000000, 72293000 },
1276 .hactive = { 1280, 1280, 1280 },
1277 .hfront_porch = { 48, 48, 48 },
1278 .hback_porch = { 80, 80, 80 },
1279 .hsync_len = { 32, 32, 32 },
1280 .vactive = { 800, 800, 800 },
1281 .vfront_porch = { 3, 3, 3 },
1282 .vback_porch = { 14, 14, 14 },
1283 .vsync_len = { 6, 6, 6 },
1284 };
1285
1286 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1287 .timings = &boe_ev121wxm_n10_1850_timing,
1288 .num_timings = 1,
1289 .bpc = 8,
1290 .size = {
1291 .width = 261,
1292 .height = 163,
1293 },
1294 .delay = {
1295 .prepare = 9,
1296 .enable = 300,
1297 .unprepare = 300,
1298 .disable = 560,
1299 },
1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1301 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1302 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1303 };
1304
1305 static const struct drm_display_mode boe_hv070wsa_mode = {
1306 .clock = 42105,
1307 .hdisplay = 1024,
1308 .hsync_start = 1024 + 30,
1309 .hsync_end = 1024 + 30 + 30,
1310 .htotal = 1024 + 30 + 30 + 30,
1311 .vdisplay = 600,
1312 .vsync_start = 600 + 10,
1313 .vsync_end = 600 + 10 + 10,
1314 .vtotal = 600 + 10 + 10 + 10,
1315 };
1316
1317 static const struct panel_desc boe_hv070wsa = {
1318 .modes = &boe_hv070wsa_mode,
1319 .num_modes = 1,
1320 .bpc = 8,
1321 .size = {
1322 .width = 154,
1323 .height = 90,
1324 },
1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1326 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1327 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1328 };
1329
1330 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1331 .clock = 9000,
1332 .hdisplay = 480,
1333 .hsync_start = 480 + 5,
1334 .hsync_end = 480 + 5 + 5,
1335 .htotal = 480 + 5 + 5 + 40,
1336 .vdisplay = 272,
1337 .vsync_start = 272 + 8,
1338 .vsync_end = 272 + 8 + 8,
1339 .vtotal = 272 + 8 + 8 + 8,
1340 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1341 };
1342
1343 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1344 .modes = &cdtech_s043wq26h_ct7_mode,
1345 .num_modes = 1,
1346 .bpc = 8,
1347 .size = {
1348 .width = 95,
1349 .height = 54,
1350 },
1351 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1352 };
1353
1354 /* S070PWS19HP-FC21 2017/04/22 */
1355 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1356 .clock = 51200,
1357 .hdisplay = 1024,
1358 .hsync_start = 1024 + 160,
1359 .hsync_end = 1024 + 160 + 20,
1360 .htotal = 1024 + 160 + 20 + 140,
1361 .vdisplay = 600,
1362 .vsync_start = 600 + 12,
1363 .vsync_end = 600 + 12 + 3,
1364 .vtotal = 600 + 12 + 3 + 20,
1365 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1366 };
1367
1368 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1369 .modes = &cdtech_s070pws19hp_fc21_mode,
1370 .num_modes = 1,
1371 .bpc = 6,
1372 .size = {
1373 .width = 154,
1374 .height = 86,
1375 },
1376 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1377 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1378 .connector_type = DRM_MODE_CONNECTOR_DPI,
1379 };
1380
1381 /* S070SWV29HG-DC44 2017/09/21 */
1382 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1383 .clock = 33300,
1384 .hdisplay = 800,
1385 .hsync_start = 800 + 210,
1386 .hsync_end = 800 + 210 + 2,
1387 .htotal = 800 + 210 + 2 + 44,
1388 .vdisplay = 480,
1389 .vsync_start = 480 + 22,
1390 .vsync_end = 480 + 22 + 2,
1391 .vtotal = 480 + 22 + 2 + 21,
1392 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1393 };
1394
1395 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1396 .modes = &cdtech_s070swv29hg_dc44_mode,
1397 .num_modes = 1,
1398 .bpc = 6,
1399 .size = {
1400 .width = 154,
1401 .height = 86,
1402 },
1403 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1404 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1405 .connector_type = DRM_MODE_CONNECTOR_DPI,
1406 };
1407
1408 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1409 .clock = 35000,
1410 .hdisplay = 800,
1411 .hsync_start = 800 + 40,
1412 .hsync_end = 800 + 40 + 40,
1413 .htotal = 800 + 40 + 40 + 48,
1414 .vdisplay = 480,
1415 .vsync_start = 480 + 29,
1416 .vsync_end = 480 + 29 + 13,
1417 .vtotal = 480 + 29 + 13 + 3,
1418 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1419 };
1420
1421 static const struct panel_desc cdtech_s070wv95_ct16 = {
1422 .modes = &cdtech_s070wv95_ct16_mode,
1423 .num_modes = 1,
1424 .bpc = 8,
1425 .size = {
1426 .width = 154,
1427 .height = 85,
1428 },
1429 };
1430
1431 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1432 .pixelclock = { 68900000, 71100000, 73400000 },
1433 .hactive = { 1280, 1280, 1280 },
1434 .hfront_porch = { 65, 80, 95 },
1435 .hback_porch = { 64, 79, 94 },
1436 .hsync_len = { 1, 1, 1 },
1437 .vactive = { 800, 800, 800 },
1438 .vfront_porch = { 7, 11, 14 },
1439 .vback_porch = { 7, 11, 14 },
1440 .vsync_len = { 1, 1, 1 },
1441 .flags = DISPLAY_FLAGS_DE_HIGH,
1442 };
1443
1444 static const struct panel_desc chefree_ch101olhlwh_002 = {
1445 .timings = &chefree_ch101olhlwh_002_timing,
1446 .num_timings = 1,
1447 .bpc = 8,
1448 .size = {
1449 .width = 217,
1450 .height = 135,
1451 },
1452 .delay = {
1453 .enable = 200,
1454 .disable = 200,
1455 },
1456 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1457 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1458 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1459 };
1460
1461 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1462 .clock = 66770,
1463 .hdisplay = 800,
1464 .hsync_start = 800 + 49,
1465 .hsync_end = 800 + 49 + 33,
1466 .htotal = 800 + 49 + 33 + 17,
1467 .vdisplay = 1280,
1468 .vsync_start = 1280 + 1,
1469 .vsync_end = 1280 + 1 + 7,
1470 .vtotal = 1280 + 1 + 7 + 15,
1471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1472 };
1473
1474 static const struct panel_desc chunghwa_claa070wp03xg = {
1475 .modes = &chunghwa_claa070wp03xg_mode,
1476 .num_modes = 1,
1477 .bpc = 6,
1478 .size = {
1479 .width = 94,
1480 .height = 150,
1481 },
1482 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1483 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1484 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1485 };
1486
1487 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1488 .clock = 72070,
1489 .hdisplay = 1366,
1490 .hsync_start = 1366 + 58,
1491 .hsync_end = 1366 + 58 + 58,
1492 .htotal = 1366 + 58 + 58 + 58,
1493 .vdisplay = 768,
1494 .vsync_start = 768 + 4,
1495 .vsync_end = 768 + 4 + 4,
1496 .vtotal = 768 + 4 + 4 + 4,
1497 };
1498
1499 static const struct panel_desc chunghwa_claa101wa01a = {
1500 .modes = &chunghwa_claa101wa01a_mode,
1501 .num_modes = 1,
1502 .bpc = 6,
1503 .size = {
1504 .width = 220,
1505 .height = 120,
1506 },
1507 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1508 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1509 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1510 };
1511
1512 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1513 .clock = 69300,
1514 .hdisplay = 1366,
1515 .hsync_start = 1366 + 48,
1516 .hsync_end = 1366 + 48 + 32,
1517 .htotal = 1366 + 48 + 32 + 20,
1518 .vdisplay = 768,
1519 .vsync_start = 768 + 16,
1520 .vsync_end = 768 + 16 + 8,
1521 .vtotal = 768 + 16 + 8 + 16,
1522 };
1523
1524 static const struct panel_desc chunghwa_claa101wb01 = {
1525 .modes = &chunghwa_claa101wb01_mode,
1526 .num_modes = 1,
1527 .bpc = 6,
1528 .size = {
1529 .width = 223,
1530 .height = 125,
1531 },
1532 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1533 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1534 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1535 };
1536
1537 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1538 .pixelclock = { 5000000, 9000000, 12000000 },
1539 .hactive = { 480, 480, 480 },
1540 .hfront_porch = { 12, 12, 12 },
1541 .hback_porch = { 12, 12, 12 },
1542 .hsync_len = { 21, 21, 21 },
1543 .vactive = { 272, 272, 272 },
1544 .vfront_porch = { 4, 4, 4 },
1545 .vback_porch = { 4, 4, 4 },
1546 .vsync_len = { 8, 8, 8 },
1547 };
1548
1549 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1550 .timings = &dataimage_fg040346dsswbg04_timing,
1551 .num_timings = 1,
1552 .bpc = 8,
1553 .size = {
1554 .width = 95,
1555 .height = 54,
1556 },
1557 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1558 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1559 .connector_type = DRM_MODE_CONNECTOR_DPI,
1560 };
1561
1562 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1563 .pixelclock = { 68900000, 71110000, 73400000 },
1564 .hactive = { 1280, 1280, 1280 },
1565 .vactive = { 800, 800, 800 },
1566 .hback_porch = { 100, 100, 100 },
1567 .hfront_porch = { 100, 100, 100 },
1568 .vback_porch = { 5, 5, 5 },
1569 .vfront_porch = { 5, 5, 5 },
1570 .hsync_len = { 24, 24, 24 },
1571 .vsync_len = { 3, 3, 3 },
1572 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1573 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1574 };
1575
1576 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1577 .timings = &dataimage_fg1001l0dsswmg01_timing,
1578 .num_timings = 1,
1579 .bpc = 8,
1580 .size = {
1581 .width = 217,
1582 .height = 136,
1583 },
1584 };
1585
1586 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1587 .clock = 33260,
1588 .hdisplay = 800,
1589 .hsync_start = 800 + 40,
1590 .hsync_end = 800 + 40 + 128,
1591 .htotal = 800 + 40 + 128 + 88,
1592 .vdisplay = 480,
1593 .vsync_start = 480 + 10,
1594 .vsync_end = 480 + 10 + 2,
1595 .vtotal = 480 + 10 + 2 + 33,
1596 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1597 };
1598
1599 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1600 .modes = &dataimage_scf0700c48ggu18_mode,
1601 .num_modes = 1,
1602 .bpc = 8,
1603 .size = {
1604 .width = 152,
1605 .height = 91,
1606 },
1607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1608 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1609 };
1610
1611 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1612 .pixelclock = { 45000000, 51200000, 57000000 },
1613 .hactive = { 1024, 1024, 1024 },
1614 .hfront_porch = { 100, 106, 113 },
1615 .hback_porch = { 100, 106, 113 },
1616 .hsync_len = { 100, 108, 114 },
1617 .vactive = { 600, 600, 600 },
1618 .vfront_porch = { 8, 11, 15 },
1619 .vback_porch = { 8, 11, 15 },
1620 .vsync_len = { 9, 13, 15 },
1621 .flags = DISPLAY_FLAGS_DE_HIGH,
1622 };
1623
1624 static const struct panel_desc dlc_dlc0700yzg_1 = {
1625 .timings = &dlc_dlc0700yzg_1_timing,
1626 .num_timings = 1,
1627 .bpc = 6,
1628 .size = {
1629 .width = 154,
1630 .height = 86,
1631 },
1632 .delay = {
1633 .prepare = 30,
1634 .enable = 200,
1635 .disable = 200,
1636 },
1637 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1638 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1639 };
1640
1641 static const struct display_timing dlc_dlc1010gig_timing = {
1642 .pixelclock = { 68900000, 71100000, 73400000 },
1643 .hactive = { 1280, 1280, 1280 },
1644 .hfront_porch = { 43, 53, 63 },
1645 .hback_porch = { 43, 53, 63 },
1646 .hsync_len = { 44, 54, 64 },
1647 .vactive = { 800, 800, 800 },
1648 .vfront_porch = { 5, 8, 11 },
1649 .vback_porch = { 5, 8, 11 },
1650 .vsync_len = { 5, 7, 11 },
1651 .flags = DISPLAY_FLAGS_DE_HIGH,
1652 };
1653
1654 static const struct panel_desc dlc_dlc1010gig = {
1655 .timings = &dlc_dlc1010gig_timing,
1656 .num_timings = 1,
1657 .bpc = 8,
1658 .size = {
1659 .width = 216,
1660 .height = 135,
1661 },
1662 .delay = {
1663 .prepare = 60,
1664 .enable = 150,
1665 .disable = 100,
1666 .unprepare = 60,
1667 },
1668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1669 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1670 };
1671
1672 static const struct drm_display_mode edt_et035012dm6_mode = {
1673 .clock = 6500,
1674 .hdisplay = 320,
1675 .hsync_start = 320 + 20,
1676 .hsync_end = 320 + 20 + 30,
1677 .htotal = 320 + 20 + 68,
1678 .vdisplay = 240,
1679 .vsync_start = 240 + 4,
1680 .vsync_end = 240 + 4 + 4,
1681 .vtotal = 240 + 4 + 4 + 14,
1682 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1683 };
1684
1685 static const struct panel_desc edt_et035012dm6 = {
1686 .modes = &edt_et035012dm6_mode,
1687 .num_modes = 1,
1688 .bpc = 8,
1689 .size = {
1690 .width = 70,
1691 .height = 52,
1692 },
1693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1694 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1695 };
1696
1697 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1698 .clock = 6520,
1699 .hdisplay = 320,
1700 .hsync_start = 320 + 20,
1701 .hsync_end = 320 + 20 + 68,
1702 .htotal = 320 + 20 + 68,
1703 .vdisplay = 240,
1704 .vsync_start = 240 + 4,
1705 .vsync_end = 240 + 4 + 18,
1706 .vtotal = 240 + 4 + 18,
1707 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1708 };
1709
1710 static const struct panel_desc edt_etm0350g0dh6 = {
1711 .modes = &edt_etm0350g0dh6_mode,
1712 .num_modes = 1,
1713 .bpc = 6,
1714 .size = {
1715 .width = 70,
1716 .height = 53,
1717 },
1718 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1719 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1720 .connector_type = DRM_MODE_CONNECTOR_DPI,
1721 };
1722
1723 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1724 .clock = 10870,
1725 .hdisplay = 480,
1726 .hsync_start = 480 + 8,
1727 .hsync_end = 480 + 8 + 4,
1728 .htotal = 480 + 8 + 4 + 41,
1729
1730 /*
1731 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1732 * fb_align
1733 */
1734
1735 .vdisplay = 288,
1736 .vsync_start = 288 + 2,
1737 .vsync_end = 288 + 2 + 4,
1738 .vtotal = 288 + 2 + 4 + 10,
1739 };
1740
1741 static const struct panel_desc edt_etm043080dh6gp = {
1742 .modes = &edt_etm043080dh6gp_mode,
1743 .num_modes = 1,
1744 .bpc = 8,
1745 .size = {
1746 .width = 100,
1747 .height = 65,
1748 },
1749 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1750 .connector_type = DRM_MODE_CONNECTOR_DPI,
1751 };
1752
1753 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1754 .clock = 9000,
1755 .hdisplay = 480,
1756 .hsync_start = 480 + 2,
1757 .hsync_end = 480 + 2 + 41,
1758 .htotal = 480 + 2 + 41 + 2,
1759 .vdisplay = 272,
1760 .vsync_start = 272 + 2,
1761 .vsync_end = 272 + 2 + 10,
1762 .vtotal = 272 + 2 + 10 + 2,
1763 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1764 };
1765
1766 static const struct panel_desc edt_etm0430g0dh6 = {
1767 .modes = &edt_etm0430g0dh6_mode,
1768 .num_modes = 1,
1769 .bpc = 6,
1770 .size = {
1771 .width = 95,
1772 .height = 54,
1773 },
1774 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1776 .connector_type = DRM_MODE_CONNECTOR_DPI,
1777 };
1778
1779 static const struct drm_display_mode edt_et057090dhu_mode = {
1780 .clock = 25175,
1781 .hdisplay = 640,
1782 .hsync_start = 640 + 16,
1783 .hsync_end = 640 + 16 + 30,
1784 .htotal = 640 + 16 + 30 + 114,
1785 .vdisplay = 480,
1786 .vsync_start = 480 + 10,
1787 .vsync_end = 480 + 10 + 3,
1788 .vtotal = 480 + 10 + 3 + 32,
1789 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1790 };
1791
1792 static const struct panel_desc edt_et057090dhu = {
1793 .modes = &edt_et057090dhu_mode,
1794 .num_modes = 1,
1795 .bpc = 6,
1796 .size = {
1797 .width = 115,
1798 .height = 86,
1799 },
1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1802 .connector_type = DRM_MODE_CONNECTOR_DPI,
1803 };
1804
1805 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1806 .clock = 33260,
1807 .hdisplay = 800,
1808 .hsync_start = 800 + 40,
1809 .hsync_end = 800 + 40 + 128,
1810 .htotal = 800 + 40 + 128 + 88,
1811 .vdisplay = 480,
1812 .vsync_start = 480 + 10,
1813 .vsync_end = 480 + 10 + 2,
1814 .vtotal = 480 + 10 + 2 + 33,
1815 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1816 };
1817
1818 static const struct panel_desc edt_etm0700g0dh6 = {
1819 .modes = &edt_etm0700g0dh6_mode,
1820 .num_modes = 1,
1821 .bpc = 6,
1822 .size = {
1823 .width = 152,
1824 .height = 91,
1825 },
1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1828 .connector_type = DRM_MODE_CONNECTOR_DPI,
1829 };
1830
1831 static const struct panel_desc edt_etm0700g0bdh6 = {
1832 .modes = &edt_etm0700g0dh6_mode,
1833 .num_modes = 1,
1834 .bpc = 6,
1835 .size = {
1836 .width = 152,
1837 .height = 91,
1838 },
1839 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1840 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1841 .connector_type = DRM_MODE_CONNECTOR_DPI,
1842 };
1843
1844 static const struct display_timing edt_etml0700y5dha_timing = {
1845 .pixelclock = { 40800000, 51200000, 67200000 },
1846 .hactive = { 1024, 1024, 1024 },
1847 .hfront_porch = { 30, 106, 125 },
1848 .hback_porch = { 30, 106, 125 },
1849 .hsync_len = { 30, 108, 126 },
1850 .vactive = { 600, 600, 600 },
1851 .vfront_porch = { 3, 12, 67},
1852 .vback_porch = { 3, 12, 67 },
1853 .vsync_len = { 4, 11, 66 },
1854 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1855 DISPLAY_FLAGS_DE_HIGH,
1856 };
1857
1858 static const struct panel_desc edt_etml0700y5dha = {
1859 .timings = &edt_etml0700y5dha_timing,
1860 .num_timings = 1,
1861 .bpc = 8,
1862 .size = {
1863 .width = 155,
1864 .height = 86,
1865 },
1866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1867 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1868 };
1869
1870 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1871 .clock = 25175,
1872 .hdisplay = 640,
1873 .hsync_start = 640,
1874 .hsync_end = 640 + 16,
1875 .htotal = 640 + 16 + 30 + 114,
1876 .vdisplay = 480,
1877 .vsync_start = 480 + 10,
1878 .vsync_end = 480 + 10 + 3,
1879 .vtotal = 480 + 10 + 3 + 35,
1880 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1881 };
1882
1883 static const struct panel_desc edt_etmv570g2dhu = {
1884 .modes = &edt_etmv570g2dhu_mode,
1885 .num_modes = 1,
1886 .bpc = 6,
1887 .size = {
1888 .width = 115,
1889 .height = 86,
1890 },
1891 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1892 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1893 .connector_type = DRM_MODE_CONNECTOR_DPI,
1894 };
1895
1896 static const struct display_timing eink_vb3300_kca_timing = {
1897 .pixelclock = { 40000000, 40000000, 40000000 },
1898 .hactive = { 334, 334, 334 },
1899 .hfront_porch = { 1, 1, 1 },
1900 .hback_porch = { 1, 1, 1 },
1901 .hsync_len = { 1, 1, 1 },
1902 .vactive = { 1405, 1405, 1405 },
1903 .vfront_porch = { 1, 1, 1 },
1904 .vback_porch = { 1, 1, 1 },
1905 .vsync_len = { 1, 1, 1 },
1906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1908 };
1909
1910 static const struct panel_desc eink_vb3300_kca = {
1911 .timings = &eink_vb3300_kca_timing,
1912 .num_timings = 1,
1913 .bpc = 6,
1914 .size = {
1915 .width = 157,
1916 .height = 209,
1917 },
1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1920 .connector_type = DRM_MODE_CONNECTOR_DPI,
1921 };
1922
1923 static const struct display_timing evervision_vgg804821_timing = {
1924 .pixelclock = { 27600000, 33300000, 50000000 },
1925 .hactive = { 800, 800, 800 },
1926 .hfront_porch = { 40, 66, 70 },
1927 .hback_porch = { 40, 67, 70 },
1928 .hsync_len = { 40, 67, 70 },
1929 .vactive = { 480, 480, 480 },
1930 .vfront_porch = { 6, 10, 10 },
1931 .vback_porch = { 7, 11, 11 },
1932 .vsync_len = { 7, 11, 11 },
1933 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1934 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1935 DISPLAY_FLAGS_SYNC_NEGEDGE,
1936 };
1937
1938 static const struct panel_desc evervision_vgg804821 = {
1939 .timings = &evervision_vgg804821_timing,
1940 .num_timings = 1,
1941 .bpc = 8,
1942 .size = {
1943 .width = 108,
1944 .height = 64,
1945 },
1946 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1947 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1948 };
1949
1950 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1951 .clock = 32260,
1952 .hdisplay = 800,
1953 .hsync_start = 800 + 168,
1954 .hsync_end = 800 + 168 + 64,
1955 .htotal = 800 + 168 + 64 + 88,
1956 .vdisplay = 480,
1957 .vsync_start = 480 + 37,
1958 .vsync_end = 480 + 37 + 2,
1959 .vtotal = 480 + 37 + 2 + 8,
1960 };
1961
1962 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1963 .modes = &foxlink_fl500wvr00_a0t_mode,
1964 .num_modes = 1,
1965 .bpc = 8,
1966 .size = {
1967 .width = 108,
1968 .height = 65,
1969 },
1970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1971 };
1972
1973 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1974 { /* 60 Hz */
1975 .clock = 6000,
1976 .hdisplay = 320,
1977 .hsync_start = 320 + 44,
1978 .hsync_end = 320 + 44 + 16,
1979 .htotal = 320 + 44 + 16 + 20,
1980 .vdisplay = 240,
1981 .vsync_start = 240 + 2,
1982 .vsync_end = 240 + 2 + 6,
1983 .vtotal = 240 + 2 + 6 + 2,
1984 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1985 },
1986 { /* 50 Hz */
1987 .clock = 5400,
1988 .hdisplay = 320,
1989 .hsync_start = 320 + 56,
1990 .hsync_end = 320 + 56 + 16,
1991 .htotal = 320 + 56 + 16 + 40,
1992 .vdisplay = 240,
1993 .vsync_start = 240 + 2,
1994 .vsync_end = 240 + 2 + 6,
1995 .vtotal = 240 + 2 + 6 + 2,
1996 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1997 },
1998 };
1999
2000 static const struct panel_desc frida_frd350h54004 = {
2001 .modes = frida_frd350h54004_modes,
2002 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2003 .bpc = 8,
2004 .size = {
2005 .width = 77,
2006 .height = 64,
2007 },
2008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2010 .connector_type = DRM_MODE_CONNECTOR_DPI,
2011 };
2012
2013 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2014 .clock = 67185,
2015 .hdisplay = 800,
2016 .hsync_start = 800 + 20,
2017 .hsync_end = 800 + 20 + 24,
2018 .htotal = 800 + 20 + 24 + 20,
2019 .vdisplay = 1280,
2020 .vsync_start = 1280 + 4,
2021 .vsync_end = 1280 + 4 + 8,
2022 .vtotal = 1280 + 4 + 8 + 4,
2023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2024 };
2025
2026 static const struct panel_desc friendlyarm_hd702e = {
2027 .modes = &friendlyarm_hd702e_mode,
2028 .num_modes = 1,
2029 .size = {
2030 .width = 94,
2031 .height = 151,
2032 },
2033 };
2034
2035 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2036 .clock = 9000,
2037 .hdisplay = 480,
2038 .hsync_start = 480 + 5,
2039 .hsync_end = 480 + 5 + 1,
2040 .htotal = 480 + 5 + 1 + 40,
2041 .vdisplay = 272,
2042 .vsync_start = 272 + 8,
2043 .vsync_end = 272 + 8 + 1,
2044 .vtotal = 272 + 8 + 1 + 8,
2045 };
2046
2047 static const struct panel_desc giantplus_gpg482739qs5 = {
2048 .modes = &giantplus_gpg482739qs5_mode,
2049 .num_modes = 1,
2050 .bpc = 8,
2051 .size = {
2052 .width = 95,
2053 .height = 54,
2054 },
2055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2056 };
2057
2058 static const struct display_timing giantplus_gpm940b0_timing = {
2059 .pixelclock = { 13500000, 27000000, 27500000 },
2060 .hactive = { 320, 320, 320 },
2061 .hfront_porch = { 14, 686, 718 },
2062 .hback_porch = { 50, 70, 255 },
2063 .hsync_len = { 1, 1, 1 },
2064 .vactive = { 240, 240, 240 },
2065 .vfront_porch = { 1, 1, 179 },
2066 .vback_porch = { 1, 21, 31 },
2067 .vsync_len = { 1, 1, 6 },
2068 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2069 };
2070
2071 static const struct panel_desc giantplus_gpm940b0 = {
2072 .timings = &giantplus_gpm940b0_timing,
2073 .num_timings = 1,
2074 .bpc = 8,
2075 .size = {
2076 .width = 60,
2077 .height = 45,
2078 },
2079 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2080 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2081 };
2082
2083 static const struct display_timing hannstar_hsd070pww1_timing = {
2084 .pixelclock = { 64300000, 71100000, 82000000 },
2085 .hactive = { 1280, 1280, 1280 },
2086 .hfront_porch = { 1, 1, 10 },
2087 .hback_porch = { 1, 1, 10 },
2088 /*
2089 * According to the data sheet, the minimum horizontal blanking interval
2090 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2091 * minimum working horizontal blanking interval to be 60 clocks.
2092 */
2093 .hsync_len = { 58, 158, 661 },
2094 .vactive = { 800, 800, 800 },
2095 .vfront_porch = { 1, 1, 10 },
2096 .vback_porch = { 1, 1, 10 },
2097 .vsync_len = { 1, 21, 203 },
2098 .flags = DISPLAY_FLAGS_DE_HIGH,
2099 };
2100
2101 static const struct panel_desc hannstar_hsd070pww1 = {
2102 .timings = &hannstar_hsd070pww1_timing,
2103 .num_timings = 1,
2104 .bpc = 6,
2105 .size = {
2106 .width = 151,
2107 .height = 94,
2108 },
2109 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2110 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2111 };
2112
2113 static const struct display_timing hannstar_hsd100pxn1_timing = {
2114 .pixelclock = { 55000000, 65000000, 75000000 },
2115 .hactive = { 1024, 1024, 1024 },
2116 .hfront_porch = { 40, 40, 40 },
2117 .hback_porch = { 220, 220, 220 },
2118 .hsync_len = { 20, 60, 100 },
2119 .vactive = { 768, 768, 768 },
2120 .vfront_porch = { 7, 7, 7 },
2121 .vback_porch = { 21, 21, 21 },
2122 .vsync_len = { 10, 10, 10 },
2123 .flags = DISPLAY_FLAGS_DE_HIGH,
2124 };
2125
2126 static const struct panel_desc hannstar_hsd100pxn1 = {
2127 .timings = &hannstar_hsd100pxn1_timing,
2128 .num_timings = 1,
2129 .bpc = 6,
2130 .size = {
2131 .width = 203,
2132 .height = 152,
2133 },
2134 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2135 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2136 };
2137
2138 static const struct display_timing hannstar_hsd101pww2_timing = {
2139 .pixelclock = { 64300000, 71100000, 82000000 },
2140 .hactive = { 1280, 1280, 1280 },
2141 .hfront_porch = { 1, 1, 10 },
2142 .hback_porch = { 1, 1, 10 },
2143 .hsync_len = { 58, 158, 661 },
2144 .vactive = { 800, 800, 800 },
2145 .vfront_porch = { 1, 1, 10 },
2146 .vback_porch = { 1, 1, 10 },
2147 .vsync_len = { 1, 21, 203 },
2148 .flags = DISPLAY_FLAGS_DE_HIGH,
2149 };
2150
2151 static const struct panel_desc hannstar_hsd101pww2 = {
2152 .timings = &hannstar_hsd101pww2_timing,
2153 .num_timings = 1,
2154 .bpc = 8,
2155 .size = {
2156 .width = 217,
2157 .height = 136,
2158 },
2159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2160 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2161 };
2162
2163 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2164 .clock = 33333,
2165 .hdisplay = 800,
2166 .hsync_start = 800 + 85,
2167 .hsync_end = 800 + 85 + 86,
2168 .htotal = 800 + 85 + 86 + 85,
2169 .vdisplay = 480,
2170 .vsync_start = 480 + 16,
2171 .vsync_end = 480 + 16 + 13,
2172 .vtotal = 480 + 16 + 13 + 16,
2173 };
2174
2175 static const struct panel_desc hitachi_tx23d38vm0caa = {
2176 .modes = &hitachi_tx23d38vm0caa_mode,
2177 .num_modes = 1,
2178 .bpc = 6,
2179 .size = {
2180 .width = 195,
2181 .height = 117,
2182 },
2183 .delay = {
2184 .enable = 160,
2185 .disable = 160,
2186 },
2187 };
2188
2189 static const struct drm_display_mode innolux_at043tn24_mode = {
2190 .clock = 9000,
2191 .hdisplay = 480,
2192 .hsync_start = 480 + 2,
2193 .hsync_end = 480 + 2 + 41,
2194 .htotal = 480 + 2 + 41 + 2,
2195 .vdisplay = 272,
2196 .vsync_start = 272 + 2,
2197 .vsync_end = 272 + 2 + 10,
2198 .vtotal = 272 + 2 + 10 + 2,
2199 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2200 };
2201
2202 static const struct panel_desc innolux_at043tn24 = {
2203 .modes = &innolux_at043tn24_mode,
2204 .num_modes = 1,
2205 .bpc = 8,
2206 .size = {
2207 .width = 95,
2208 .height = 54,
2209 },
2210 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2211 .connector_type = DRM_MODE_CONNECTOR_DPI,
2212 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2213 };
2214
2215 static const struct drm_display_mode innolux_at070tn92_mode = {
2216 .clock = 33333,
2217 .hdisplay = 800,
2218 .hsync_start = 800 + 210,
2219 .hsync_end = 800 + 210 + 20,
2220 .htotal = 800 + 210 + 20 + 46,
2221 .vdisplay = 480,
2222 .vsync_start = 480 + 22,
2223 .vsync_end = 480 + 22 + 10,
2224 .vtotal = 480 + 22 + 23 + 10,
2225 };
2226
2227 static const struct panel_desc innolux_at070tn92 = {
2228 .modes = &innolux_at070tn92_mode,
2229 .num_modes = 1,
2230 .size = {
2231 .width = 154,
2232 .height = 86,
2233 },
2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2235 };
2236
2237 static const struct display_timing innolux_g070ace_l01_timing = {
2238 .pixelclock = { 25200000, 35000000, 35700000 },
2239 .hactive = { 800, 800, 800 },
2240 .hfront_porch = { 30, 32, 87 },
2241 .hback_porch = { 30, 32, 87 },
2242 .hsync_len = { 1, 1, 1 },
2243 .vactive = { 480, 480, 480 },
2244 .vfront_porch = { 3, 3, 3 },
2245 .vback_porch = { 13, 13, 13 },
2246 .vsync_len = { 1, 1, 4 },
2247 .flags = DISPLAY_FLAGS_DE_HIGH,
2248 };
2249
2250 static const struct panel_desc innolux_g070ace_l01 = {
2251 .timings = &innolux_g070ace_l01_timing,
2252 .num_timings = 1,
2253 .bpc = 8,
2254 .size = {
2255 .width = 152,
2256 .height = 91,
2257 },
2258 .delay = {
2259 .prepare = 10,
2260 .enable = 50,
2261 .disable = 50,
2262 .unprepare = 500,
2263 },
2264 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2265 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2266 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2267 };
2268
2269 static const struct display_timing innolux_g070y2_l01_timing = {
2270 .pixelclock = { 28000000, 29500000, 32000000 },
2271 .hactive = { 800, 800, 800 },
2272 .hfront_porch = { 61, 91, 141 },
2273 .hback_porch = { 60, 90, 140 },
2274 .hsync_len = { 12, 12, 12 },
2275 .vactive = { 480, 480, 480 },
2276 .vfront_porch = { 4, 9, 30 },
2277 .vback_porch = { 4, 8, 28 },
2278 .vsync_len = { 2, 2, 2 },
2279 .flags = DISPLAY_FLAGS_DE_HIGH,
2280 };
2281
2282 static const struct panel_desc innolux_g070y2_l01 = {
2283 .timings = &innolux_g070y2_l01_timing,
2284 .num_timings = 1,
2285 .bpc = 8,
2286 .size = {
2287 .width = 152,
2288 .height = 91,
2289 },
2290 .delay = {
2291 .prepare = 10,
2292 .enable = 100,
2293 .disable = 100,
2294 .unprepare = 800,
2295 },
2296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2298 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2299 };
2300
2301 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2302 .clock = 33333,
2303 .hdisplay = 800,
2304 .hsync_start = 800 + 210,
2305 .hsync_end = 800 + 210 + 20,
2306 .htotal = 800 + 210 + 20 + 46,
2307 .vdisplay = 480,
2308 .vsync_start = 480 + 22,
2309 .vsync_end = 480 + 22 + 10,
2310 .vtotal = 480 + 22 + 23 + 10,
2311 };
2312
2313 static const struct panel_desc innolux_g070y2_t02 = {
2314 .modes = &innolux_g070y2_t02_mode,
2315 .num_modes = 1,
2316 .bpc = 8,
2317 .size = {
2318 .width = 152,
2319 .height = 92,
2320 },
2321 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2322 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2323 .connector_type = DRM_MODE_CONNECTOR_DPI,
2324 };
2325
2326 static const struct display_timing innolux_g101ice_l01_timing = {
2327 .pixelclock = { 60400000, 71100000, 74700000 },
2328 .hactive = { 1280, 1280, 1280 },
2329 .hfront_porch = { 30, 60, 70 },
2330 .hback_porch = { 30, 60, 70 },
2331 .hsync_len = { 22, 40, 60 },
2332 .vactive = { 800, 800, 800 },
2333 .vfront_porch = { 3, 8, 14 },
2334 .vback_porch = { 3, 8, 14 },
2335 .vsync_len = { 4, 7, 12 },
2336 .flags = DISPLAY_FLAGS_DE_HIGH,
2337 };
2338
2339 static const struct panel_desc innolux_g101ice_l01 = {
2340 .timings = &innolux_g101ice_l01_timing,
2341 .num_timings = 1,
2342 .bpc = 8,
2343 .size = {
2344 .width = 217,
2345 .height = 135,
2346 },
2347 .delay = {
2348 .enable = 200,
2349 .disable = 200,
2350 },
2351 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2352 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2353 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2354 };
2355
2356 static const struct display_timing innolux_g121i1_l01_timing = {
2357 .pixelclock = { 67450000, 71000000, 74550000 },
2358 .hactive = { 1280, 1280, 1280 },
2359 .hfront_porch = { 40, 80, 160 },
2360 .hback_porch = { 39, 79, 159 },
2361 .hsync_len = { 1, 1, 1 },
2362 .vactive = { 800, 800, 800 },
2363 .vfront_porch = { 5, 11, 100 },
2364 .vback_porch = { 4, 11, 99 },
2365 .vsync_len = { 1, 1, 1 },
2366 };
2367
2368 static const struct panel_desc innolux_g121i1_l01 = {
2369 .timings = &innolux_g121i1_l01_timing,
2370 .num_timings = 1,
2371 .bpc = 6,
2372 .size = {
2373 .width = 261,
2374 .height = 163,
2375 },
2376 .delay = {
2377 .enable = 200,
2378 .disable = 20,
2379 },
2380 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2381 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2382 };
2383
2384 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2385 .clock = 65000,
2386 .hdisplay = 1024,
2387 .hsync_start = 1024 + 0,
2388 .hsync_end = 1024 + 1,
2389 .htotal = 1024 + 0 + 1 + 320,
2390 .vdisplay = 768,
2391 .vsync_start = 768 + 38,
2392 .vsync_end = 768 + 38 + 1,
2393 .vtotal = 768 + 38 + 1 + 0,
2394 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2395 };
2396
2397 static const struct panel_desc innolux_g121x1_l03 = {
2398 .modes = &innolux_g121x1_l03_mode,
2399 .num_modes = 1,
2400 .bpc = 6,
2401 .size = {
2402 .width = 246,
2403 .height = 185,
2404 },
2405 .delay = {
2406 .enable = 200,
2407 .unprepare = 200,
2408 .disable = 400,
2409 },
2410 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2411 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2412 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2413 };
2414
2415 static const struct display_timing innolux_g156hce_l01_timings = {
2416 .pixelclock = { 120000000, 141860000, 150000000 },
2417 .hactive = { 1920, 1920, 1920 },
2418 .hfront_porch = { 80, 90, 100 },
2419 .hback_porch = { 80, 90, 100 },
2420 .hsync_len = { 20, 30, 30 },
2421 .vactive = { 1080, 1080, 1080 },
2422 .vfront_porch = { 3, 10, 20 },
2423 .vback_porch = { 3, 10, 20 },
2424 .vsync_len = { 4, 10, 10 },
2425 };
2426
2427 static const struct panel_desc innolux_g156hce_l01 = {
2428 .timings = &innolux_g156hce_l01_timings,
2429 .num_timings = 1,
2430 .bpc = 8,
2431 .size = {
2432 .width = 344,
2433 .height = 194,
2434 },
2435 .delay = {
2436 .prepare = 1, /* T1+T2 */
2437 .enable = 450, /* T5 */
2438 .disable = 200, /* T6 */
2439 .unprepare = 10, /* T3+T7 */
2440 },
2441 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2442 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2443 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2444 };
2445
2446 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2447 .clock = 69300,
2448 .hdisplay = 1366,
2449 .hsync_start = 1366 + 16,
2450 .hsync_end = 1366 + 16 + 34,
2451 .htotal = 1366 + 16 + 34 + 50,
2452 .vdisplay = 768,
2453 .vsync_start = 768 + 2,
2454 .vsync_end = 768 + 2 + 6,
2455 .vtotal = 768 + 2 + 6 + 12,
2456 };
2457
2458 static const struct panel_desc innolux_n156bge_l21 = {
2459 .modes = &innolux_n156bge_l21_mode,
2460 .num_modes = 1,
2461 .bpc = 6,
2462 .size = {
2463 .width = 344,
2464 .height = 193,
2465 },
2466 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2467 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2468 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2469 };
2470
2471 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2472 .clock = 51501,
2473 .hdisplay = 1024,
2474 .hsync_start = 1024 + 128,
2475 .hsync_end = 1024 + 128 + 64,
2476 .htotal = 1024 + 128 + 64 + 128,
2477 .vdisplay = 600,
2478 .vsync_start = 600 + 16,
2479 .vsync_end = 600 + 16 + 4,
2480 .vtotal = 600 + 16 + 4 + 16,
2481 };
2482
2483 static const struct panel_desc innolux_zj070na_01p = {
2484 .modes = &innolux_zj070na_01p_mode,
2485 .num_modes = 1,
2486 .bpc = 6,
2487 .size = {
2488 .width = 154,
2489 .height = 90,
2490 },
2491 };
2492
2493 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2494 .pixelclock = { 5580000, 5850000, 6200000 },
2495 .hactive = { 320, 320, 320 },
2496 .hfront_porch = { 30, 30, 30 },
2497 .hback_porch = { 30, 30, 30 },
2498 .hsync_len = { 1, 5, 17 },
2499 .vactive = { 240, 240, 240 },
2500 .vfront_porch = { 6, 6, 6 },
2501 .vback_porch = { 5, 5, 5 },
2502 .vsync_len = { 1, 2, 11 },
2503 .flags = DISPLAY_FLAGS_DE_HIGH,
2504 };
2505
2506 static const struct panel_desc koe_tx14d24vm1bpa = {
2507 .timings = &koe_tx14d24vm1bpa_timing,
2508 .num_timings = 1,
2509 .bpc = 6,
2510 .size = {
2511 .width = 115,
2512 .height = 86,
2513 },
2514 };
2515
2516 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2517 .pixelclock = { 151820000, 156720000, 159780000 },
2518 .hactive = { 1920, 1920, 1920 },
2519 .hfront_porch = { 105, 130, 142 },
2520 .hback_porch = { 45, 70, 82 },
2521 .hsync_len = { 30, 30, 30 },
2522 .vactive = { 1200, 1200, 1200},
2523 .vfront_porch = { 3, 5, 10 },
2524 .vback_porch = { 2, 5, 10 },
2525 .vsync_len = { 5, 5, 5 },
2526 .flags = DISPLAY_FLAGS_DE_HIGH,
2527 };
2528
2529 static const struct panel_desc koe_tx26d202vm0bwa = {
2530 .timings = &koe_tx26d202vm0bwa_timing,
2531 .num_timings = 1,
2532 .bpc = 8,
2533 .size = {
2534 .width = 217,
2535 .height = 136,
2536 },
2537 .delay = {
2538 .prepare = 1000,
2539 .enable = 1000,
2540 .unprepare = 1000,
2541 .disable = 1000,
2542 },
2543 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2544 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2545 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2546 };
2547
2548 static const struct display_timing koe_tx31d200vm0baa_timing = {
2549 .pixelclock = { 39600000, 43200000, 48000000 },
2550 .hactive = { 1280, 1280, 1280 },
2551 .hfront_porch = { 16, 36, 56 },
2552 .hback_porch = { 16, 36, 56 },
2553 .hsync_len = { 8, 8, 8 },
2554 .vactive = { 480, 480, 480 },
2555 .vfront_porch = { 6, 21, 33 },
2556 .vback_porch = { 6, 21, 33 },
2557 .vsync_len = { 8, 8, 8 },
2558 .flags = DISPLAY_FLAGS_DE_HIGH,
2559 };
2560
2561 static const struct panel_desc koe_tx31d200vm0baa = {
2562 .timings = &koe_tx31d200vm0baa_timing,
2563 .num_timings = 1,
2564 .bpc = 6,
2565 .size = {
2566 .width = 292,
2567 .height = 109,
2568 },
2569 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2570 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2571 };
2572
2573 static const struct display_timing kyo_tcg121xglp_timing = {
2574 .pixelclock = { 52000000, 65000000, 71000000 },
2575 .hactive = { 1024, 1024, 1024 },
2576 .hfront_porch = { 2, 2, 2 },
2577 .hback_porch = { 2, 2, 2 },
2578 .hsync_len = { 86, 124, 244 },
2579 .vactive = { 768, 768, 768 },
2580 .vfront_porch = { 2, 2, 2 },
2581 .vback_porch = { 2, 2, 2 },
2582 .vsync_len = { 6, 34, 73 },
2583 .flags = DISPLAY_FLAGS_DE_HIGH,
2584 };
2585
2586 static const struct panel_desc kyo_tcg121xglp = {
2587 .timings = &kyo_tcg121xglp_timing,
2588 .num_timings = 1,
2589 .bpc = 8,
2590 .size = {
2591 .width = 246,
2592 .height = 184,
2593 },
2594 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2595 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2596 };
2597
2598 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2599 .clock = 7000,
2600 .hdisplay = 320,
2601 .hsync_start = 320 + 20,
2602 .hsync_end = 320 + 20 + 30,
2603 .htotal = 320 + 20 + 30 + 38,
2604 .vdisplay = 240,
2605 .vsync_start = 240 + 4,
2606 .vsync_end = 240 + 4 + 3,
2607 .vtotal = 240 + 4 + 3 + 15,
2608 };
2609
2610 static const struct panel_desc lemaker_bl035_rgb_002 = {
2611 .modes = &lemaker_bl035_rgb_002_mode,
2612 .num_modes = 1,
2613 .size = {
2614 .width = 70,
2615 .height = 52,
2616 },
2617 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2618 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2619 };
2620
2621 static const struct drm_display_mode lg_lb070wv8_mode = {
2622 .clock = 33246,
2623 .hdisplay = 800,
2624 .hsync_start = 800 + 88,
2625 .hsync_end = 800 + 88 + 80,
2626 .htotal = 800 + 88 + 80 + 88,
2627 .vdisplay = 480,
2628 .vsync_start = 480 + 10,
2629 .vsync_end = 480 + 10 + 25,
2630 .vtotal = 480 + 10 + 25 + 10,
2631 };
2632
2633 static const struct panel_desc lg_lb070wv8 = {
2634 .modes = &lg_lb070wv8_mode,
2635 .num_modes = 1,
2636 .bpc = 8,
2637 .size = {
2638 .width = 151,
2639 .height = 91,
2640 },
2641 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2642 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2643 };
2644
2645 static const struct display_timing logictechno_lt161010_2nh_timing = {
2646 .pixelclock = { 26400000, 33300000, 46800000 },
2647 .hactive = { 800, 800, 800 },
2648 .hfront_porch = { 16, 210, 354 },
2649 .hback_porch = { 46, 46, 46 },
2650 .hsync_len = { 1, 20, 40 },
2651 .vactive = { 480, 480, 480 },
2652 .vfront_porch = { 7, 22, 147 },
2653 .vback_porch = { 23, 23, 23 },
2654 .vsync_len = { 1, 10, 20 },
2655 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2656 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2657 DISPLAY_FLAGS_SYNC_POSEDGE,
2658 };
2659
2660 static const struct panel_desc logictechno_lt161010_2nh = {
2661 .timings = &logictechno_lt161010_2nh_timing,
2662 .num_timings = 1,
2663 .bpc = 6,
2664 .size = {
2665 .width = 154,
2666 .height = 86,
2667 },
2668 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2669 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2670 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2671 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2672 .connector_type = DRM_MODE_CONNECTOR_DPI,
2673 };
2674
2675 static const struct display_timing logictechno_lt170410_2whc_timing = {
2676 .pixelclock = { 68900000, 71100000, 73400000 },
2677 .hactive = { 1280, 1280, 1280 },
2678 .hfront_porch = { 23, 60, 71 },
2679 .hback_porch = { 23, 60, 71 },
2680 .hsync_len = { 15, 40, 47 },
2681 .vactive = { 800, 800, 800 },
2682 .vfront_porch = { 5, 7, 10 },
2683 .vback_porch = { 5, 7, 10 },
2684 .vsync_len = { 6, 9, 12 },
2685 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2686 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2687 DISPLAY_FLAGS_SYNC_POSEDGE,
2688 };
2689
2690 static const struct panel_desc logictechno_lt170410_2whc = {
2691 .timings = &logictechno_lt170410_2whc_timing,
2692 .num_timings = 1,
2693 .bpc = 8,
2694 .size = {
2695 .width = 217,
2696 .height = 136,
2697 },
2698 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2699 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2700 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2701 };
2702
2703 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2704 .clock = 33000,
2705 .hdisplay = 800,
2706 .hsync_start = 800 + 112,
2707 .hsync_end = 800 + 112 + 3,
2708 .htotal = 800 + 112 + 3 + 85,
2709 .vdisplay = 480,
2710 .vsync_start = 480 + 38,
2711 .vsync_end = 480 + 38 + 3,
2712 .vtotal = 480 + 38 + 3 + 29,
2713 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2714 };
2715
2716 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2717 .modes = &logictechno_lttd800480070_l2rt_mode,
2718 .num_modes = 1,
2719 .bpc = 8,
2720 .size = {
2721 .width = 154,
2722 .height = 86,
2723 },
2724 .delay = {
2725 .prepare = 45,
2726 .enable = 100,
2727 .disable = 100,
2728 .unprepare = 45
2729 },
2730 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2731 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2732 .connector_type = DRM_MODE_CONNECTOR_DPI,
2733 };
2734
2735 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2736 .clock = 33000,
2737 .hdisplay = 800,
2738 .hsync_start = 800 + 154,
2739 .hsync_end = 800 + 154 + 3,
2740 .htotal = 800 + 154 + 3 + 43,
2741 .vdisplay = 480,
2742 .vsync_start = 480 + 47,
2743 .vsync_end = 480 + 47 + 3,
2744 .vtotal = 480 + 47 + 3 + 20,
2745 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2746 };
2747
2748 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2749 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2750 .num_modes = 1,
2751 .bpc = 8,
2752 .size = {
2753 .width = 154,
2754 .height = 86,
2755 },
2756 .delay = {
2757 .prepare = 45,
2758 .enable = 100,
2759 .disable = 100,
2760 .unprepare = 45
2761 },
2762 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2763 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2764 .connector_type = DRM_MODE_CONNECTOR_DPI,
2765 };
2766
2767 static const struct drm_display_mode logicpd_type_28_mode = {
2768 .clock = 9107,
2769 .hdisplay = 480,
2770 .hsync_start = 480 + 3,
2771 .hsync_end = 480 + 3 + 42,
2772 .htotal = 480 + 3 + 42 + 2,
2773
2774 .vdisplay = 272,
2775 .vsync_start = 272 + 2,
2776 .vsync_end = 272 + 2 + 11,
2777 .vtotal = 272 + 2 + 11 + 3,
2778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2779 };
2780
2781 static const struct panel_desc logicpd_type_28 = {
2782 .modes = &logicpd_type_28_mode,
2783 .num_modes = 1,
2784 .bpc = 8,
2785 .size = {
2786 .width = 105,
2787 .height = 67,
2788 },
2789 .delay = {
2790 .prepare = 200,
2791 .enable = 200,
2792 .unprepare = 200,
2793 .disable = 200,
2794 },
2795 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2796 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2797 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2798 .connector_type = DRM_MODE_CONNECTOR_DPI,
2799 };
2800
2801 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2802 .clock = 30400,
2803 .hdisplay = 800,
2804 .hsync_start = 800 + 0,
2805 .hsync_end = 800 + 1,
2806 .htotal = 800 + 0 + 1 + 160,
2807 .vdisplay = 480,
2808 .vsync_start = 480 + 0,
2809 .vsync_end = 480 + 48 + 1,
2810 .vtotal = 480 + 48 + 1 + 0,
2811 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2812 };
2813
2814 static const struct panel_desc mitsubishi_aa070mc01 = {
2815 .modes = &mitsubishi_aa070mc01_mode,
2816 .num_modes = 1,
2817 .bpc = 8,
2818 .size = {
2819 .width = 152,
2820 .height = 91,
2821 },
2822
2823 .delay = {
2824 .enable = 200,
2825 .unprepare = 200,
2826 .disable = 400,
2827 },
2828 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2829 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2830 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2831 };
2832
2833 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2834 .pixelclock = { 29000000, 33000000, 38000000 },
2835 .hactive = { 800, 800, 800 },
2836 .hfront_porch = { 180, 210, 240 },
2837 .hback_porch = { 16, 16, 16 },
2838 .hsync_len = { 30, 30, 30 },
2839 .vactive = { 480, 480, 480 },
2840 .vfront_porch = { 12, 22, 32 },
2841 .vback_porch = { 10, 10, 10 },
2842 .vsync_len = { 13, 13, 13 },
2843 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2844 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2845 DISPLAY_FLAGS_SYNC_POSEDGE,
2846 };
2847
2848 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2849 .timings = &multi_inno_mi0700s4t_6_timing,
2850 .num_timings = 1,
2851 .bpc = 8,
2852 .size = {
2853 .width = 154,
2854 .height = 86,
2855 },
2856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2857 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2858 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2859 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2860 .connector_type = DRM_MODE_CONNECTOR_DPI,
2861 };
2862
2863 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2864 .pixelclock = { 32000000, 40000000, 50000000 },
2865 .hactive = { 800, 800, 800 },
2866 .hfront_porch = { 16, 210, 354 },
2867 .hback_porch = { 6, 26, 45 },
2868 .hsync_len = { 1, 20, 40 },
2869 .vactive = { 600, 600, 600 },
2870 .vfront_porch = { 1, 12, 77 },
2871 .vback_porch = { 3, 13, 22 },
2872 .vsync_len = { 1, 10, 20 },
2873 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2874 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2875 DISPLAY_FLAGS_SYNC_POSEDGE,
2876 };
2877
2878 static const struct panel_desc multi_inno_mi0800ft_9 = {
2879 .timings = &multi_inno_mi0800ft_9_timing,
2880 .num_timings = 1,
2881 .bpc = 8,
2882 .size = {
2883 .width = 162,
2884 .height = 122,
2885 },
2886 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2887 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2888 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2889 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2890 .connector_type = DRM_MODE_CONNECTOR_DPI,
2891 };
2892
2893 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2894 .pixelclock = { 68900000, 70000000, 73400000 },
2895 .hactive = { 1280, 1280, 1280 },
2896 .hfront_porch = { 30, 60, 71 },
2897 .hback_porch = { 30, 60, 71 },
2898 .hsync_len = { 10, 10, 48 },
2899 .vactive = { 800, 800, 800 },
2900 .vfront_porch = { 5, 10, 10 },
2901 .vback_porch = { 5, 10, 10 },
2902 .vsync_len = { 5, 6, 13 },
2903 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2904 DISPLAY_FLAGS_DE_HIGH,
2905 };
2906
2907 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2908 .timings = &multi_inno_mi1010ait_1cp_timing,
2909 .num_timings = 1,
2910 .bpc = 8,
2911 .size = {
2912 .width = 217,
2913 .height = 136,
2914 },
2915 .delay = {
2916 .enable = 50,
2917 .disable = 50,
2918 },
2919 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2920 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2921 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2922 };
2923
2924 static const struct display_timing nec_nl12880bc20_05_timing = {
2925 .pixelclock = { 67000000, 71000000, 75000000 },
2926 .hactive = { 1280, 1280, 1280 },
2927 .hfront_porch = { 2, 30, 30 },
2928 .hback_porch = { 6, 100, 100 },
2929 .hsync_len = { 2, 30, 30 },
2930 .vactive = { 800, 800, 800 },
2931 .vfront_porch = { 5, 5, 5 },
2932 .vback_porch = { 11, 11, 11 },
2933 .vsync_len = { 7, 7, 7 },
2934 };
2935
2936 static const struct panel_desc nec_nl12880bc20_05 = {
2937 .timings = &nec_nl12880bc20_05_timing,
2938 .num_timings = 1,
2939 .bpc = 8,
2940 .size = {
2941 .width = 261,
2942 .height = 163,
2943 },
2944 .delay = {
2945 .enable = 50,
2946 .disable = 50,
2947 },
2948 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2949 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2950 };
2951
2952 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2953 .clock = 10870,
2954 .hdisplay = 480,
2955 .hsync_start = 480 + 2,
2956 .hsync_end = 480 + 2 + 41,
2957 .htotal = 480 + 2 + 41 + 2,
2958 .vdisplay = 272,
2959 .vsync_start = 272 + 2,
2960 .vsync_end = 272 + 2 + 4,
2961 .vtotal = 272 + 2 + 4 + 2,
2962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2963 };
2964
2965 static const struct panel_desc nec_nl4827hc19_05b = {
2966 .modes = &nec_nl4827hc19_05b_mode,
2967 .num_modes = 1,
2968 .bpc = 8,
2969 .size = {
2970 .width = 95,
2971 .height = 54,
2972 },
2973 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2974 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2975 };
2976
2977 static const struct drm_display_mode netron_dy_e231732_mode = {
2978 .clock = 66000,
2979 .hdisplay = 1024,
2980 .hsync_start = 1024 + 160,
2981 .hsync_end = 1024 + 160 + 70,
2982 .htotal = 1024 + 160 + 70 + 90,
2983 .vdisplay = 600,
2984 .vsync_start = 600 + 127,
2985 .vsync_end = 600 + 127 + 20,
2986 .vtotal = 600 + 127 + 20 + 3,
2987 };
2988
2989 static const struct panel_desc netron_dy_e231732 = {
2990 .modes = &netron_dy_e231732_mode,
2991 .num_modes = 1,
2992 .size = {
2993 .width = 154,
2994 .height = 87,
2995 },
2996 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2997 };
2998
2999 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3000 .clock = 9000,
3001 .hdisplay = 480,
3002 .hsync_start = 480 + 2,
3003 .hsync_end = 480 + 2 + 41,
3004 .htotal = 480 + 2 + 41 + 2,
3005 .vdisplay = 272,
3006 .vsync_start = 272 + 2,
3007 .vsync_end = 272 + 2 + 10,
3008 .vtotal = 272 + 2 + 10 + 2,
3009 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3010 };
3011
3012 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3013 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3014 .num_modes = 1,
3015 .bpc = 8,
3016 .size = {
3017 .width = 95,
3018 .height = 54,
3019 },
3020 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3021 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3022 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3023 .connector_type = DRM_MODE_CONNECTOR_DPI,
3024 };
3025
3026 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3027 .pixelclock = { 130000000, 148350000, 163000000 },
3028 .hactive = { 1920, 1920, 1920 },
3029 .hfront_porch = { 80, 100, 100 },
3030 .hback_porch = { 100, 120, 120 },
3031 .hsync_len = { 50, 60, 60 },
3032 .vactive = { 1080, 1080, 1080 },
3033 .vfront_porch = { 12, 30, 30 },
3034 .vback_porch = { 4, 10, 10 },
3035 .vsync_len = { 4, 5, 5 },
3036 };
3037
3038 static const struct panel_desc nlt_nl192108ac18_02d = {
3039 .timings = &nlt_nl192108ac18_02d_timing,
3040 .num_timings = 1,
3041 .bpc = 8,
3042 .size = {
3043 .width = 344,
3044 .height = 194,
3045 },
3046 .delay = {
3047 .unprepare = 500,
3048 },
3049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3050 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3051 };
3052
3053 static const struct drm_display_mode nvd_9128_mode = {
3054 .clock = 29500,
3055 .hdisplay = 800,
3056 .hsync_start = 800 + 130,
3057 .hsync_end = 800 + 130 + 98,
3058 .htotal = 800 + 0 + 130 + 98,
3059 .vdisplay = 480,
3060 .vsync_start = 480 + 10,
3061 .vsync_end = 480 + 10 + 50,
3062 .vtotal = 480 + 0 + 10 + 50,
3063 };
3064
3065 static const struct panel_desc nvd_9128 = {
3066 .modes = &nvd_9128_mode,
3067 .num_modes = 1,
3068 .bpc = 8,
3069 .size = {
3070 .width = 156,
3071 .height = 88,
3072 },
3073 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3074 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3075 };
3076
3077 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3078 .pixelclock = { 30000000, 30000000, 40000000 },
3079 .hactive = { 800, 800, 800 },
3080 .hfront_porch = { 40, 40, 40 },
3081 .hback_porch = { 40, 40, 40 },
3082 .hsync_len = { 1, 48, 48 },
3083 .vactive = { 480, 480, 480 },
3084 .vfront_porch = { 13, 13, 13 },
3085 .vback_porch = { 29, 29, 29 },
3086 .vsync_len = { 3, 3, 3 },
3087 .flags = DISPLAY_FLAGS_DE_HIGH,
3088 };
3089
3090 static const struct panel_desc okaya_rs800480t_7x0gp = {
3091 .timings = &okaya_rs800480t_7x0gp_timing,
3092 .num_timings = 1,
3093 .bpc = 6,
3094 .size = {
3095 .width = 154,
3096 .height = 87,
3097 },
3098 .delay = {
3099 .prepare = 41,
3100 .enable = 50,
3101 .unprepare = 41,
3102 .disable = 50,
3103 },
3104 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3105 };
3106
3107 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3108 .clock = 9000,
3109 .hdisplay = 480,
3110 .hsync_start = 480 + 5,
3111 .hsync_end = 480 + 5 + 30,
3112 .htotal = 480 + 5 + 30 + 10,
3113 .vdisplay = 272,
3114 .vsync_start = 272 + 8,
3115 .vsync_end = 272 + 8 + 5,
3116 .vtotal = 272 + 8 + 5 + 3,
3117 };
3118
3119 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3120 .modes = &olimex_lcd_olinuxino_43ts_mode,
3121 .num_modes = 1,
3122 .size = {
3123 .width = 95,
3124 .height = 54,
3125 },
3126 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3127 };
3128
3129 /*
3130 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3131 * pixel clocks, but this is the timing that was being used in the Adafruit
3132 * installation instructions.
3133 */
3134 static const struct drm_display_mode ontat_yx700wv03_mode = {
3135 .clock = 29500,
3136 .hdisplay = 800,
3137 .hsync_start = 824,
3138 .hsync_end = 896,
3139 .htotal = 992,
3140 .vdisplay = 480,
3141 .vsync_start = 483,
3142 .vsync_end = 493,
3143 .vtotal = 500,
3144 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3145 };
3146
3147 /*
3148 * Specification at:
3149 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3150 */
3151 static const struct panel_desc ontat_yx700wv03 = {
3152 .modes = &ontat_yx700wv03_mode,
3153 .num_modes = 1,
3154 .bpc = 8,
3155 .size = {
3156 .width = 154,
3157 .height = 83,
3158 },
3159 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3160 };
3161
3162 static const struct drm_display_mode ortustech_com37h3m_mode = {
3163 .clock = 22230,
3164 .hdisplay = 480,
3165 .hsync_start = 480 + 40,
3166 .hsync_end = 480 + 40 + 10,
3167 .htotal = 480 + 40 + 10 + 40,
3168 .vdisplay = 640,
3169 .vsync_start = 640 + 4,
3170 .vsync_end = 640 + 4 + 2,
3171 .vtotal = 640 + 4 + 2 + 4,
3172 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3173 };
3174
3175 static const struct panel_desc ortustech_com37h3m = {
3176 .modes = &ortustech_com37h3m_mode,
3177 .num_modes = 1,
3178 .bpc = 8,
3179 .size = {
3180 .width = 56, /* 56.16mm */
3181 .height = 75, /* 74.88mm */
3182 },
3183 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3184 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3185 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3186 };
3187
3188 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3189 .clock = 25000,
3190 .hdisplay = 480,
3191 .hsync_start = 480 + 10,
3192 .hsync_end = 480 + 10 + 10,
3193 .htotal = 480 + 10 + 10 + 15,
3194 .vdisplay = 800,
3195 .vsync_start = 800 + 3,
3196 .vsync_end = 800 + 3 + 3,
3197 .vtotal = 800 + 3 + 3 + 3,
3198 };
3199
3200 static const struct panel_desc ortustech_com43h4m85ulc = {
3201 .modes = &ortustech_com43h4m85ulc_mode,
3202 .num_modes = 1,
3203 .bpc = 6,
3204 .size = {
3205 .width = 56,
3206 .height = 93,
3207 },
3208 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3209 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3210 .connector_type = DRM_MODE_CONNECTOR_DPI,
3211 };
3212
3213 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3214 .clock = 33000,
3215 .hdisplay = 800,
3216 .hsync_start = 800 + 210,
3217 .hsync_end = 800 + 210 + 30,
3218 .htotal = 800 + 210 + 30 + 16,
3219 .vdisplay = 480,
3220 .vsync_start = 480 + 22,
3221 .vsync_end = 480 + 22 + 13,
3222 .vtotal = 480 + 22 + 13 + 10,
3223 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3224 };
3225
3226 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3227 .modes = &osddisplays_osd070t1718_19ts_mode,
3228 .num_modes = 1,
3229 .bpc = 8,
3230 .size = {
3231 .width = 152,
3232 .height = 91,
3233 },
3234 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3235 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3236 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3237 .connector_type = DRM_MODE_CONNECTOR_DPI,
3238 };
3239
3240 static const struct drm_display_mode pda_91_00156_a0_mode = {
3241 .clock = 33300,
3242 .hdisplay = 800,
3243 .hsync_start = 800 + 1,
3244 .hsync_end = 800 + 1 + 64,
3245 .htotal = 800 + 1 + 64 + 64,
3246 .vdisplay = 480,
3247 .vsync_start = 480 + 1,
3248 .vsync_end = 480 + 1 + 23,
3249 .vtotal = 480 + 1 + 23 + 22,
3250 };
3251
3252 static const struct panel_desc pda_91_00156_a0 = {
3253 .modes = &pda_91_00156_a0_mode,
3254 .num_modes = 1,
3255 .size = {
3256 .width = 152,
3257 .height = 91,
3258 },
3259 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3260 };
3261
3262 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3263 .clock = 24750,
3264 .hdisplay = 800,
3265 .hsync_start = 800 + 54,
3266 .hsync_end = 800 + 54 + 2,
3267 .htotal = 800 + 54 + 2 + 44,
3268 .vdisplay = 480,
3269 .vsync_start = 480 + 49,
3270 .vsync_end = 480 + 49 + 2,
3271 .vtotal = 480 + 49 + 2 + 22,
3272 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3273 };
3274
3275 static const struct panel_desc powertip_ph800480t013_idf02 = {
3276 .modes = &powertip_ph800480t013_idf02_mode,
3277 .num_modes = 1,
3278 .bpc = 8,
3279 .size = {
3280 .width = 152,
3281 .height = 91,
3282 },
3283 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3284 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3285 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3286 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3287 .connector_type = DRM_MODE_CONNECTOR_DPI,
3288 };
3289
3290 static const struct drm_display_mode qd43003c0_40_mode = {
3291 .clock = 9000,
3292 .hdisplay = 480,
3293 .hsync_start = 480 + 8,
3294 .hsync_end = 480 + 8 + 4,
3295 .htotal = 480 + 8 + 4 + 39,
3296 .vdisplay = 272,
3297 .vsync_start = 272 + 4,
3298 .vsync_end = 272 + 4 + 10,
3299 .vtotal = 272 + 4 + 10 + 2,
3300 };
3301
3302 static const struct panel_desc qd43003c0_40 = {
3303 .modes = &qd43003c0_40_mode,
3304 .num_modes = 1,
3305 .bpc = 8,
3306 .size = {
3307 .width = 95,
3308 .height = 53,
3309 },
3310 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3311 };
3312
3313 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3314 { /* 60 Hz */
3315 .clock = 10800,
3316 .hdisplay = 480,
3317 .hsync_start = 480 + 77,
3318 .hsync_end = 480 + 77 + 41,
3319 .htotal = 480 + 77 + 41 + 2,
3320 .vdisplay = 272,
3321 .vsync_start = 272 + 16,
3322 .vsync_end = 272 + 16 + 10,
3323 .vtotal = 272 + 16 + 10 + 2,
3324 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3325 },
3326 { /* 50 Hz */
3327 .clock = 10800,
3328 .hdisplay = 480,
3329 .hsync_start = 480 + 17,
3330 .hsync_end = 480 + 17 + 41,
3331 .htotal = 480 + 17 + 41 + 2,
3332 .vdisplay = 272,
3333 .vsync_start = 272 + 116,
3334 .vsync_end = 272 + 116 + 10,
3335 .vtotal = 272 + 116 + 10 + 2,
3336 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3337 },
3338 };
3339
3340 static const struct panel_desc qishenglong_gopher2b_lcd = {
3341 .modes = qishenglong_gopher2b_lcd_modes,
3342 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3343 .bpc = 8,
3344 .size = {
3345 .width = 95,
3346 .height = 54,
3347 },
3348 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3349 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3350 .connector_type = DRM_MODE_CONNECTOR_DPI,
3351 };
3352
3353 static const struct display_timing rocktech_rk043fn48h_timing = {
3354 .pixelclock = { 6000000, 9000000, 12000000 },
3355 .hactive = { 480, 480, 480 },
3356 .hback_porch = { 8, 43, 43 },
3357 .hfront_porch = { 2, 8, 8 },
3358 .hsync_len = { 1, 1, 1 },
3359 .vactive = { 272, 272, 272 },
3360 .vback_porch = { 2, 12, 12 },
3361 .vfront_porch = { 1, 4, 4 },
3362 .vsync_len = { 1, 10, 10 },
3363 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3364 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3365 };
3366
3367 static const struct panel_desc rocktech_rk043fn48h = {
3368 .timings = &rocktech_rk043fn48h_timing,
3369 .num_timings = 1,
3370 .bpc = 8,
3371 .size = {
3372 .width = 95,
3373 .height = 54,
3374 },
3375 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3376 .connector_type = DRM_MODE_CONNECTOR_DPI,
3377 };
3378
3379 static const struct display_timing rocktech_rk070er9427_timing = {
3380 .pixelclock = { 26400000, 33300000, 46800000 },
3381 .hactive = { 800, 800, 800 },
3382 .hfront_porch = { 16, 210, 354 },
3383 .hback_porch = { 46, 46, 46 },
3384 .hsync_len = { 1, 1, 1 },
3385 .vactive = { 480, 480, 480 },
3386 .vfront_porch = { 7, 22, 147 },
3387 .vback_porch = { 23, 23, 23 },
3388 .vsync_len = { 1, 1, 1 },
3389 .flags = DISPLAY_FLAGS_DE_HIGH,
3390 };
3391
3392 static const struct panel_desc rocktech_rk070er9427 = {
3393 .timings = &rocktech_rk070er9427_timing,
3394 .num_timings = 1,
3395 .bpc = 6,
3396 .size = {
3397 .width = 154,
3398 .height = 86,
3399 },
3400 .delay = {
3401 .prepare = 41,
3402 .enable = 50,
3403 .unprepare = 41,
3404 .disable = 50,
3405 },
3406 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3407 };
3408
3409 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3410 .clock = 71100,
3411 .hdisplay = 1280,
3412 .hsync_start = 1280 + 48,
3413 .hsync_end = 1280 + 48 + 32,
3414 .htotal = 1280 + 48 + 32 + 80,
3415 .vdisplay = 800,
3416 .vsync_start = 800 + 2,
3417 .vsync_end = 800 + 2 + 5,
3418 .vtotal = 800 + 2 + 5 + 16,
3419 };
3420
3421 static const struct panel_desc rocktech_rk101ii01d_ct = {
3422 .modes = &rocktech_rk101ii01d_ct_mode,
3423 .bpc = 8,
3424 .num_modes = 1,
3425 .size = {
3426 .width = 217,
3427 .height = 136,
3428 },
3429 .delay = {
3430 .prepare = 50,
3431 .disable = 50,
3432 },
3433 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3434 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3435 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3436 };
3437
3438 static const struct display_timing samsung_ltl101al01_timing = {
3439 .pixelclock = { 66663000, 66663000, 66663000 },
3440 .hactive = { 1280, 1280, 1280 },
3441 .hfront_porch = { 18, 18, 18 },
3442 .hback_porch = { 36, 36, 36 },
3443 .hsync_len = { 16, 16, 16 },
3444 .vactive = { 800, 800, 800 },
3445 .vfront_porch = { 4, 4, 4 },
3446 .vback_porch = { 16, 16, 16 },
3447 .vsync_len = { 3, 3, 3 },
3448 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3449 };
3450
3451 static const struct panel_desc samsung_ltl101al01 = {
3452 .timings = &samsung_ltl101al01_timing,
3453 .num_timings = 1,
3454 .bpc = 8,
3455 .size = {
3456 .width = 217,
3457 .height = 135,
3458 },
3459 .delay = {
3460 .prepare = 40,
3461 .enable = 300,
3462 .disable = 200,
3463 .unprepare = 600,
3464 },
3465 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3466 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3467 };
3468
3469 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3470 .clock = 54030,
3471 .hdisplay = 1024,
3472 .hsync_start = 1024 + 24,
3473 .hsync_end = 1024 + 24 + 136,
3474 .htotal = 1024 + 24 + 136 + 160,
3475 .vdisplay = 600,
3476 .vsync_start = 600 + 3,
3477 .vsync_end = 600 + 3 + 6,
3478 .vtotal = 600 + 3 + 6 + 61,
3479 };
3480
3481 static const struct panel_desc samsung_ltn101nt05 = {
3482 .modes = &samsung_ltn101nt05_mode,
3483 .num_modes = 1,
3484 .bpc = 6,
3485 .size = {
3486 .width = 223,
3487 .height = 125,
3488 },
3489 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3490 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3491 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3492 };
3493
3494 static const struct display_timing satoz_sat050at40h12r2_timing = {
3495 .pixelclock = {33300000, 33300000, 50000000},
3496 .hactive = {800, 800, 800},
3497 .hfront_porch = {16, 210, 354},
3498 .hback_porch = {46, 46, 46},
3499 .hsync_len = {1, 1, 40},
3500 .vactive = {480, 480, 480},
3501 .vfront_porch = {7, 22, 147},
3502 .vback_porch = {23, 23, 23},
3503 .vsync_len = {1, 1, 20},
3504 };
3505
3506 static const struct panel_desc satoz_sat050at40h12r2 = {
3507 .timings = &satoz_sat050at40h12r2_timing,
3508 .num_timings = 1,
3509 .bpc = 8,
3510 .size = {
3511 .width = 108,
3512 .height = 65,
3513 },
3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3515 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3516 };
3517
3518 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3519 .clock = 33260,
3520 .hdisplay = 800,
3521 .hsync_start = 800 + 64,
3522 .hsync_end = 800 + 64 + 128,
3523 .htotal = 800 + 64 + 128 + 64,
3524 .vdisplay = 480,
3525 .vsync_start = 480 + 8,
3526 .vsync_end = 480 + 8 + 2,
3527 .vtotal = 480 + 8 + 2 + 35,
3528 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3529 };
3530
3531 static const struct panel_desc sharp_lq070y3dg3b = {
3532 .modes = &sharp_lq070y3dg3b_mode,
3533 .num_modes = 1,
3534 .bpc = 8,
3535 .size = {
3536 .width = 152, /* 152.4mm */
3537 .height = 91, /* 91.4mm */
3538 },
3539 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3540 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3541 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3542 };
3543
3544 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3545 .clock = 5500,
3546 .hdisplay = 240,
3547 .hsync_start = 240 + 16,
3548 .hsync_end = 240 + 16 + 7,
3549 .htotal = 240 + 16 + 7 + 5,
3550 .vdisplay = 320,
3551 .vsync_start = 320 + 9,
3552 .vsync_end = 320 + 9 + 1,
3553 .vtotal = 320 + 9 + 1 + 7,
3554 };
3555
3556 static const struct panel_desc sharp_lq035q7db03 = {
3557 .modes = &sharp_lq035q7db03_mode,
3558 .num_modes = 1,
3559 .bpc = 6,
3560 .size = {
3561 .width = 54,
3562 .height = 72,
3563 },
3564 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3565 };
3566
3567 static const struct display_timing sharp_lq101k1ly04_timing = {
3568 .pixelclock = { 60000000, 65000000, 80000000 },
3569 .hactive = { 1280, 1280, 1280 },
3570 .hfront_porch = { 20, 20, 20 },
3571 .hback_porch = { 20, 20, 20 },
3572 .hsync_len = { 10, 10, 10 },
3573 .vactive = { 800, 800, 800 },
3574 .vfront_porch = { 4, 4, 4 },
3575 .vback_porch = { 4, 4, 4 },
3576 .vsync_len = { 4, 4, 4 },
3577 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3578 };
3579
3580 static const struct panel_desc sharp_lq101k1ly04 = {
3581 .timings = &sharp_lq101k1ly04_timing,
3582 .num_timings = 1,
3583 .bpc = 8,
3584 .size = {
3585 .width = 217,
3586 .height = 136,
3587 },
3588 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3589 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3590 };
3591
3592 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3593 { /* 50 Hz */
3594 .clock = 3000,
3595 .hdisplay = 240,
3596 .hsync_start = 240 + 58,
3597 .hsync_end = 240 + 58 + 1,
3598 .htotal = 240 + 58 + 1 + 1,
3599 .vdisplay = 160,
3600 .vsync_start = 160 + 24,
3601 .vsync_end = 160 + 24 + 10,
3602 .vtotal = 160 + 24 + 10 + 6,
3603 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3604 },
3605 { /* 60 Hz */
3606 .clock = 3000,
3607 .hdisplay = 240,
3608 .hsync_start = 240 + 8,
3609 .hsync_end = 240 + 8 + 1,
3610 .htotal = 240 + 8 + 1 + 1,
3611 .vdisplay = 160,
3612 .vsync_start = 160 + 24,
3613 .vsync_end = 160 + 24 + 10,
3614 .vtotal = 160 + 24 + 10 + 6,
3615 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3616 },
3617 };
3618
3619 static const struct panel_desc sharp_ls020b1dd01d = {
3620 .modes = sharp_ls020b1dd01d_modes,
3621 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3622 .bpc = 6,
3623 .size = {
3624 .width = 42,
3625 .height = 28,
3626 },
3627 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3628 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3629 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3630 | DRM_BUS_FLAG_SHARP_SIGNALS,
3631 };
3632
3633 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3634 .clock = 33300,
3635 .hdisplay = 800,
3636 .hsync_start = 800 + 1,
3637 .hsync_end = 800 + 1 + 64,
3638 .htotal = 800 + 1 + 64 + 64,
3639 .vdisplay = 480,
3640 .vsync_start = 480 + 1,
3641 .vsync_end = 480 + 1 + 23,
3642 .vtotal = 480 + 1 + 23 + 22,
3643 };
3644
3645 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3646 .modes = &shelly_sca07010_bfn_lnn_mode,
3647 .num_modes = 1,
3648 .size = {
3649 .width = 152,
3650 .height = 91,
3651 },
3652 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3653 };
3654
3655 static const struct drm_display_mode starry_kr070pe2t_mode = {
3656 .clock = 33000,
3657 .hdisplay = 800,
3658 .hsync_start = 800 + 209,
3659 .hsync_end = 800 + 209 + 1,
3660 .htotal = 800 + 209 + 1 + 45,
3661 .vdisplay = 480,
3662 .vsync_start = 480 + 22,
3663 .vsync_end = 480 + 22 + 1,
3664 .vtotal = 480 + 22 + 1 + 22,
3665 };
3666
3667 static const struct panel_desc starry_kr070pe2t = {
3668 .modes = &starry_kr070pe2t_mode,
3669 .num_modes = 1,
3670 .bpc = 8,
3671 .size = {
3672 .width = 152,
3673 .height = 86,
3674 },
3675 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3676 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3677 .connector_type = DRM_MODE_CONNECTOR_DPI,
3678 };
3679
3680 static const struct display_timing startek_kd070wvfpa_mode = {
3681 .pixelclock = { 25200000, 27200000, 30500000 },
3682 .hactive = { 800, 800, 800 },
3683 .hfront_porch = { 19, 44, 115 },
3684 .hback_porch = { 5, 16, 101 },
3685 .hsync_len = { 1, 2, 100 },
3686 .vactive = { 480, 480, 480 },
3687 .vfront_porch = { 5, 43, 67 },
3688 .vback_porch = { 5, 5, 67 },
3689 .vsync_len = { 1, 2, 66 },
3690 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3691 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3692 DISPLAY_FLAGS_SYNC_POSEDGE,
3693 };
3694
3695 static const struct panel_desc startek_kd070wvfpa = {
3696 .timings = &startek_kd070wvfpa_mode,
3697 .num_timings = 1,
3698 .bpc = 8,
3699 .size = {
3700 .width = 152,
3701 .height = 91,
3702 },
3703 .delay = {
3704 .prepare = 20,
3705 .enable = 200,
3706 .disable = 200,
3707 },
3708 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3709 .connector_type = DRM_MODE_CONNECTOR_DPI,
3710 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3711 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3712 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3713 };
3714
3715 static const struct display_timing tsd_tst043015cmhx_timing = {
3716 .pixelclock = { 5000000, 9000000, 12000000 },
3717 .hactive = { 480, 480, 480 },
3718 .hfront_porch = { 4, 5, 65 },
3719 .hback_porch = { 36, 40, 255 },
3720 .hsync_len = { 1, 1, 1 },
3721 .vactive = { 272, 272, 272 },
3722 .vfront_porch = { 2, 8, 97 },
3723 .vback_porch = { 3, 8, 31 },
3724 .vsync_len = { 1, 1, 1 },
3725
3726 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3727 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3728 };
3729
3730 static const struct panel_desc tsd_tst043015cmhx = {
3731 .timings = &tsd_tst043015cmhx_timing,
3732 .num_timings = 1,
3733 .bpc = 8,
3734 .size = {
3735 .width = 105,
3736 .height = 67,
3737 },
3738 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3740 };
3741
3742 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3743 .clock = 30000,
3744 .hdisplay = 800,
3745 .hsync_start = 800 + 39,
3746 .hsync_end = 800 + 39 + 47,
3747 .htotal = 800 + 39 + 47 + 39,
3748 .vdisplay = 480,
3749 .vsync_start = 480 + 13,
3750 .vsync_end = 480 + 13 + 2,
3751 .vtotal = 480 + 13 + 2 + 29,
3752 };
3753
3754 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3755 .modes = &tfc_s9700rtwv43tr_01b_mode,
3756 .num_modes = 1,
3757 .bpc = 8,
3758 .size = {
3759 .width = 155,
3760 .height = 90,
3761 },
3762 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3763 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3764 };
3765
3766 static const struct display_timing tianma_tm070jdhg30_timing = {
3767 .pixelclock = { 62600000, 68200000, 78100000 },
3768 .hactive = { 1280, 1280, 1280 },
3769 .hfront_porch = { 15, 64, 159 },
3770 .hback_porch = { 5, 5, 5 },
3771 .hsync_len = { 1, 1, 256 },
3772 .vactive = { 800, 800, 800 },
3773 .vfront_porch = { 3, 40, 99 },
3774 .vback_porch = { 2, 2, 2 },
3775 .vsync_len = { 1, 1, 128 },
3776 .flags = DISPLAY_FLAGS_DE_HIGH,
3777 };
3778
3779 static const struct panel_desc tianma_tm070jdhg30 = {
3780 .timings = &tianma_tm070jdhg30_timing,
3781 .num_timings = 1,
3782 .bpc = 8,
3783 .size = {
3784 .width = 151,
3785 .height = 95,
3786 },
3787 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3788 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3789 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3790 };
3791
3792 static const struct panel_desc tianma_tm070jvhg33 = {
3793 .timings = &tianma_tm070jdhg30_timing,
3794 .num_timings = 1,
3795 .bpc = 8,
3796 .size = {
3797 .width = 150,
3798 .height = 94,
3799 },
3800 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3801 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3802 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3803 };
3804
3805 static const struct display_timing tianma_tm070rvhg71_timing = {
3806 .pixelclock = { 27700000, 29200000, 39600000 },
3807 .hactive = { 800, 800, 800 },
3808 .hfront_porch = { 12, 40, 212 },
3809 .hback_porch = { 88, 88, 88 },
3810 .hsync_len = { 1, 1, 40 },
3811 .vactive = { 480, 480, 480 },
3812 .vfront_porch = { 1, 13, 88 },
3813 .vback_porch = { 32, 32, 32 },
3814 .vsync_len = { 1, 1, 3 },
3815 .flags = DISPLAY_FLAGS_DE_HIGH,
3816 };
3817
3818 static const struct panel_desc tianma_tm070rvhg71 = {
3819 .timings = &tianma_tm070rvhg71_timing,
3820 .num_timings = 1,
3821 .bpc = 8,
3822 .size = {
3823 .width = 154,
3824 .height = 86,
3825 },
3826 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3827 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3828 };
3829
3830 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3831 {
3832 .clock = 10000,
3833 .hdisplay = 320,
3834 .hsync_start = 320 + 50,
3835 .hsync_end = 320 + 50 + 6,
3836 .htotal = 320 + 50 + 6 + 38,
3837 .vdisplay = 240,
3838 .vsync_start = 240 + 3,
3839 .vsync_end = 240 + 3 + 1,
3840 .vtotal = 240 + 3 + 1 + 17,
3841 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3842 },
3843 };
3844
3845 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3846 .modes = ti_nspire_cx_lcd_mode,
3847 .num_modes = 1,
3848 .bpc = 8,
3849 .size = {
3850 .width = 65,
3851 .height = 49,
3852 },
3853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3854 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3855 };
3856
3857 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3858 {
3859 .clock = 10000,
3860 .hdisplay = 320,
3861 .hsync_start = 320 + 6,
3862 .hsync_end = 320 + 6 + 6,
3863 .htotal = 320 + 6 + 6 + 6,
3864 .vdisplay = 240,
3865 .vsync_start = 240 + 0,
3866 .vsync_end = 240 + 0 + 1,
3867 .vtotal = 240 + 0 + 1 + 0,
3868 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3869 },
3870 };
3871
3872 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3873 .modes = ti_nspire_classic_lcd_mode,
3874 .num_modes = 1,
3875 /* The grayscale panel has 8 bit for the color .. Y (black) */
3876 .bpc = 8,
3877 .size = {
3878 .width = 71,
3879 .height = 53,
3880 },
3881 /* This is the grayscale bus format */
3882 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3883 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3884 };
3885
3886 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3887 .clock = 79500,
3888 .hdisplay = 1280,
3889 .hsync_start = 1280 + 192,
3890 .hsync_end = 1280 + 192 + 128,
3891 .htotal = 1280 + 192 + 128 + 64,
3892 .vdisplay = 768,
3893 .vsync_start = 768 + 20,
3894 .vsync_end = 768 + 20 + 7,
3895 .vtotal = 768 + 20 + 7 + 3,
3896 };
3897
3898 static const struct panel_desc toshiba_lt089ac29000 = {
3899 .modes = &toshiba_lt089ac29000_mode,
3900 .num_modes = 1,
3901 .size = {
3902 .width = 194,
3903 .height = 116,
3904 },
3905 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3906 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3907 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3908 };
3909
3910 static const struct drm_display_mode tpk_f07a_0102_mode = {
3911 .clock = 33260,
3912 .hdisplay = 800,
3913 .hsync_start = 800 + 40,
3914 .hsync_end = 800 + 40 + 128,
3915 .htotal = 800 + 40 + 128 + 88,
3916 .vdisplay = 480,
3917 .vsync_start = 480 + 10,
3918 .vsync_end = 480 + 10 + 2,
3919 .vtotal = 480 + 10 + 2 + 33,
3920 };
3921
3922 static const struct panel_desc tpk_f07a_0102 = {
3923 .modes = &tpk_f07a_0102_mode,
3924 .num_modes = 1,
3925 .size = {
3926 .width = 152,
3927 .height = 91,
3928 },
3929 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3930 };
3931
3932 static const struct drm_display_mode tpk_f10a_0102_mode = {
3933 .clock = 45000,
3934 .hdisplay = 1024,
3935 .hsync_start = 1024 + 176,
3936 .hsync_end = 1024 + 176 + 5,
3937 .htotal = 1024 + 176 + 5 + 88,
3938 .vdisplay = 600,
3939 .vsync_start = 600 + 20,
3940 .vsync_end = 600 + 20 + 5,
3941 .vtotal = 600 + 20 + 5 + 25,
3942 };
3943
3944 static const struct panel_desc tpk_f10a_0102 = {
3945 .modes = &tpk_f10a_0102_mode,
3946 .num_modes = 1,
3947 .size = {
3948 .width = 223,
3949 .height = 125,
3950 },
3951 };
3952
3953 static const struct display_timing urt_umsh_8596md_timing = {
3954 .pixelclock = { 33260000, 33260000, 33260000 },
3955 .hactive = { 800, 800, 800 },
3956 .hfront_porch = { 41, 41, 41 },
3957 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3958 .hsync_len = { 71, 128, 128 },
3959 .vactive = { 480, 480, 480 },
3960 .vfront_porch = { 10, 10, 10 },
3961 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3962 .vsync_len = { 2, 2, 2 },
3963 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3964 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3965 };
3966
3967 static const struct panel_desc urt_umsh_8596md_lvds = {
3968 .timings = &urt_umsh_8596md_timing,
3969 .num_timings = 1,
3970 .bpc = 6,
3971 .size = {
3972 .width = 152,
3973 .height = 91,
3974 },
3975 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3976 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3977 };
3978
3979 static const struct panel_desc urt_umsh_8596md_parallel = {
3980 .timings = &urt_umsh_8596md_timing,
3981 .num_timings = 1,
3982 .bpc = 6,
3983 .size = {
3984 .width = 152,
3985 .height = 91,
3986 },
3987 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3988 };
3989
3990 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3991 .clock = 60000,
3992 .hdisplay = 1024,
3993 .hsync_start = 1024 + 160,
3994 .hsync_end = 1024 + 160 + 100,
3995 .htotal = 1024 + 160 + 100 + 60,
3996 .vdisplay = 600,
3997 .vsync_start = 600 + 12,
3998 .vsync_end = 600 + 12 + 10,
3999 .vtotal = 600 + 12 + 10 + 13,
4000 };
4001
4002 static const struct panel_desc vivax_tpc9150_panel = {
4003 .modes = &vivax_tpc9150_panel_mode,
4004 .num_modes = 1,
4005 .bpc = 6,
4006 .size = {
4007 .width = 200,
4008 .height = 115,
4009 },
4010 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4011 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4012 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4013 };
4014
4015 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4016 .clock = 33333,
4017 .hdisplay = 800,
4018 .hsync_start = 800 + 210,
4019 .hsync_end = 800 + 210 + 20,
4020 .htotal = 800 + 210 + 20 + 46,
4021 .vdisplay = 480,
4022 .vsync_start = 480 + 22,
4023 .vsync_end = 480 + 22 + 10,
4024 .vtotal = 480 + 22 + 10 + 23,
4025 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4026 };
4027
4028 static const struct panel_desc vl050_8048nt_c01 = {
4029 .modes = &vl050_8048nt_c01_mode,
4030 .num_modes = 1,
4031 .bpc = 8,
4032 .size = {
4033 .width = 120,
4034 .height = 76,
4035 },
4036 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4037 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4038 };
4039
4040 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4041 .clock = 6410,
4042 .hdisplay = 320,
4043 .hsync_start = 320 + 20,
4044 .hsync_end = 320 + 20 + 30,
4045 .htotal = 320 + 20 + 30 + 38,
4046 .vdisplay = 240,
4047 .vsync_start = 240 + 4,
4048 .vsync_end = 240 + 4 + 3,
4049 .vtotal = 240 + 4 + 3 + 15,
4050 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4051 };
4052
4053 static const struct panel_desc winstar_wf35ltiacd = {
4054 .modes = &winstar_wf35ltiacd_mode,
4055 .num_modes = 1,
4056 .bpc = 8,
4057 .size = {
4058 .width = 70,
4059 .height = 53,
4060 },
4061 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4062 };
4063
4064 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4065 .clock = 51200,
4066 .hdisplay = 1024,
4067 .hsync_start = 1024 + 100,
4068 .hsync_end = 1024 + 100 + 100,
4069 .htotal = 1024 + 100 + 100 + 120,
4070 .vdisplay = 600,
4071 .vsync_start = 600 + 10,
4072 .vsync_end = 600 + 10 + 10,
4073 .vtotal = 600 + 10 + 10 + 15,
4074 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4075 };
4076
4077 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4078 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4079 .num_modes = 1,
4080 .bpc = 8,
4081 .size = {
4082 .width = 154,
4083 .height = 90,
4084 },
4085 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4086 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4087 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4088 };
4089
4090 static const struct drm_display_mode mchp_ac69t88a_mode = {
4091 .clock = 25000,
4092 .hdisplay = 800,
4093 .hsync_start = 800 + 88,
4094 .hsync_end = 800 + 88 + 5,
4095 .htotal = 800 + 88 + 5 + 40,
4096 .vdisplay = 480,
4097 .vsync_start = 480 + 23,
4098 .vsync_end = 480 + 23 + 5,
4099 .vtotal = 480 + 23 + 5 + 1,
4100 };
4101
4102 static const struct panel_desc mchp_ac69t88a = {
4103 .modes = &mchp_ac69t88a_mode,
4104 .num_modes = 1,
4105 .bpc = 8,
4106 .size = {
4107 .width = 108,
4108 .height = 65,
4109 },
4110 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4111 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4112 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4113 };
4114
4115 static const struct drm_display_mode arm_rtsm_mode[] = {
4116 {
4117 .clock = 65000,
4118 .hdisplay = 1024,
4119 .hsync_start = 1024 + 24,
4120 .hsync_end = 1024 + 24 + 136,
4121 .htotal = 1024 + 24 + 136 + 160,
4122 .vdisplay = 768,
4123 .vsync_start = 768 + 3,
4124 .vsync_end = 768 + 3 + 6,
4125 .vtotal = 768 + 3 + 6 + 29,
4126 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4127 },
4128 };
4129
4130 static const struct panel_desc arm_rtsm = {
4131 .modes = arm_rtsm_mode,
4132 .num_modes = 1,
4133 .bpc = 8,
4134 .size = {
4135 .width = 400,
4136 .height = 300,
4137 },
4138 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4139 };
4140
4141 static const struct of_device_id platform_of_match[] = {
4142 {
4143 .compatible = "ampire,am-1280800n3tzqw-t00h",
4144 .data = &ire_am_1280800n3tzqw_t00h,
4145 }, {
4146 .compatible = "ampire,am-480272h3tmqw-t01h",
4147 .data = &ire_am_480272h3tmqw_t01h,
4148 }, {
4149 .compatible = "ampire,am-800480l1tmqw-t00h",
4150 .data = &ire_am_800480l1tmqw_t00h,
4151 }, {
4152 .compatible = "ampire,am800480r3tmqwa1h",
4153 .data = &ire_am800480r3tmqwa1h,
4154 }, {
4155 .compatible = "ampire,am800600p5tmqw-tb8h",
4156 .data = &ire_am800600p5tmqwtb8h,
4157 }, {
4158 .compatible = "arm,rtsm-display",
4159 .data = &arm_rtsm,
4160 }, {
4161 .compatible = "armadeus,st0700-adapt",
4162 .data = &armadeus_st0700_adapt,
4163 }, {
4164 .compatible = "auo,b101aw03",
4165 .data = &auo_b101aw03,
4166 }, {
4167 .compatible = "auo,b101xtn01",
4168 .data = &auo_b101xtn01,
4169 }, {
4170 .compatible = "auo,b116xw03",
4171 .data = &auo_b116xw03,
4172 }, {
4173 .compatible = "auo,g070vvn01",
4174 .data = &auo_g070vvn01,
4175 }, {
4176 .compatible = "auo,g101evn010",
4177 .data = &auo_g101evn010,
4178 }, {
4179 .compatible = "auo,g104sn02",
4180 .data = &auo_g104sn02,
4181 }, {
4182 .compatible = "auo,g121ean01",
4183 .data = &auo_g121ean01,
4184 }, {
4185 .compatible = "auo,g133han01",
4186 .data = &auo_g133han01,
4187 }, {
4188 .compatible = "auo,g156xtn01",
4189 .data = &auo_g156xtn01,
4190 }, {
4191 .compatible = "auo,g185han01",
4192 .data = &auo_g185han01,
4193 }, {
4194 .compatible = "auo,g190ean01",
4195 .data = &auo_g190ean01,
4196 }, {
4197 .compatible = "auo,p320hvn03",
4198 .data = &auo_p320hvn03,
4199 }, {
4200 .compatible = "auo,t215hvn01",
4201 .data = &auo_t215hvn01,
4202 }, {
4203 .compatible = "avic,tm070ddh03",
4204 .data = &avic_tm070ddh03,
4205 }, {
4206 .compatible = "bananapi,s070wv20-ct16",
4207 .data = &bananapi_s070wv20_ct16,
4208 }, {
4209 .compatible = "boe,ev121wxm-n10-1850",
4210 .data = &boe_ev121wxm_n10_1850,
4211 }, {
4212 .compatible = "boe,hv070wsa-100",
4213 .data = &boe_hv070wsa
4214 }, {
4215 .compatible = "cdtech,s043wq26h-ct7",
4216 .data = &cdtech_s043wq26h_ct7,
4217 }, {
4218 .compatible = "cdtech,s070pws19hp-fc21",
4219 .data = &cdtech_s070pws19hp_fc21,
4220 }, {
4221 .compatible = "cdtech,s070swv29hg-dc44",
4222 .data = &cdtech_s070swv29hg_dc44,
4223 }, {
4224 .compatible = "cdtech,s070wv95-ct16",
4225 .data = &cdtech_s070wv95_ct16,
4226 }, {
4227 .compatible = "chefree,ch101olhlwh-002",
4228 .data = &chefree_ch101olhlwh_002,
4229 }, {
4230 .compatible = "chunghwa,claa070wp03xg",
4231 .data = &chunghwa_claa070wp03xg,
4232 }, {
4233 .compatible = "chunghwa,claa101wa01a",
4234 .data = &chunghwa_claa101wa01a
4235 }, {
4236 .compatible = "chunghwa,claa101wb01",
4237 .data = &chunghwa_claa101wb01
4238 }, {
4239 .compatible = "dataimage,fg040346dsswbg04",
4240 .data = &dataimage_fg040346dsswbg04,
4241 }, {
4242 .compatible = "dataimage,fg1001l0dsswmg01",
4243 .data = &dataimage_fg1001l0dsswmg01,
4244 }, {
4245 .compatible = "dataimage,scf0700c48ggu18",
4246 .data = &dataimage_scf0700c48ggu18,
4247 }, {
4248 .compatible = "dlc,dlc0700yzg-1",
4249 .data = &dlc_dlc0700yzg_1,
4250 }, {
4251 .compatible = "dlc,dlc1010gig",
4252 .data = &dlc_dlc1010gig,
4253 }, {
4254 .compatible = "edt,et035012dm6",
4255 .data = &edt_et035012dm6,
4256 }, {
4257 .compatible = "edt,etm0350g0dh6",
4258 .data = &edt_etm0350g0dh6,
4259 }, {
4260 .compatible = "edt,etm043080dh6gp",
4261 .data = &edt_etm043080dh6gp,
4262 }, {
4263 .compatible = "edt,etm0430g0dh6",
4264 .data = &edt_etm0430g0dh6,
4265 }, {
4266 .compatible = "edt,et057090dhu",
4267 .data = &edt_et057090dhu,
4268 }, {
4269 .compatible = "edt,et070080dh6",
4270 .data = &edt_etm0700g0dh6,
4271 }, {
4272 .compatible = "edt,etm0700g0dh6",
4273 .data = &edt_etm0700g0dh6,
4274 }, {
4275 .compatible = "edt,etm0700g0bdh6",
4276 .data = &edt_etm0700g0bdh6,
4277 }, {
4278 .compatible = "edt,etm0700g0edh6",
4279 .data = &edt_etm0700g0bdh6,
4280 }, {
4281 .compatible = "edt,etml0700y5dha",
4282 .data = &edt_etml0700y5dha,
4283 }, {
4284 .compatible = "edt,etmv570g2dhu",
4285 .data = &edt_etmv570g2dhu,
4286 }, {
4287 .compatible = "eink,vb3300-kca",
4288 .data = &eink_vb3300_kca,
4289 }, {
4290 .compatible = "evervision,vgg804821",
4291 .data = &evervision_vgg804821,
4292 }, {
4293 .compatible = "foxlink,fl500wvr00-a0t",
4294 .data = &foxlink_fl500wvr00_a0t,
4295 }, {
4296 .compatible = "frida,frd350h54004",
4297 .data = &frida_frd350h54004,
4298 }, {
4299 .compatible = "friendlyarm,hd702e",
4300 .data = &friendlyarm_hd702e,
4301 }, {
4302 .compatible = "giantplus,gpg482739qs5",
4303 .data = &giantplus_gpg482739qs5
4304 }, {
4305 .compatible = "giantplus,gpm940b0",
4306 .data = &giantplus_gpm940b0,
4307 }, {
4308 .compatible = "hannstar,hsd070pww1",
4309 .data = &hannstar_hsd070pww1,
4310 }, {
4311 .compatible = "hannstar,hsd100pxn1",
4312 .data = &hannstar_hsd100pxn1,
4313 }, {
4314 .compatible = "hannstar,hsd101pww2",
4315 .data = &hannstar_hsd101pww2,
4316 }, {
4317 .compatible = "hit,tx23d38vm0caa",
4318 .data = &hitachi_tx23d38vm0caa
4319 }, {
4320 .compatible = "innolux,at043tn24",
4321 .data = &innolux_at043tn24,
4322 }, {
4323 .compatible = "innolux,at070tn92",
4324 .data = &innolux_at070tn92,
4325 }, {
4326 .compatible = "innolux,g070ace-l01",
4327 .data = &innolux_g070ace_l01,
4328 }, {
4329 .compatible = "innolux,g070y2-l01",
4330 .data = &innolux_g070y2_l01,
4331 }, {
4332 .compatible = "innolux,g070y2-t02",
4333 .data = &innolux_g070y2_t02,
4334 }, {
4335 .compatible = "innolux,g101ice-l01",
4336 .data = &innolux_g101ice_l01
4337 }, {
4338 .compatible = "innolux,g121i1-l01",
4339 .data = &innolux_g121i1_l01
4340 }, {
4341 .compatible = "innolux,g121x1-l03",
4342 .data = &innolux_g121x1_l03,
4343 }, {
4344 .compatible = "innolux,g156hce-l01",
4345 .data = &innolux_g156hce_l01,
4346 }, {
4347 .compatible = "innolux,n156bge-l21",
4348 .data = &innolux_n156bge_l21,
4349 }, {
4350 .compatible = "innolux,zj070na-01p",
4351 .data = &innolux_zj070na_01p,
4352 }, {
4353 .compatible = "koe,tx14d24vm1bpa",
4354 .data = &koe_tx14d24vm1bpa,
4355 }, {
4356 .compatible = "koe,tx26d202vm0bwa",
4357 .data = &koe_tx26d202vm0bwa,
4358 }, {
4359 .compatible = "koe,tx31d200vm0baa",
4360 .data = &koe_tx31d200vm0baa,
4361 }, {
4362 .compatible = "kyo,tcg121xglp",
4363 .data = &kyo_tcg121xglp,
4364 }, {
4365 .compatible = "lemaker,bl035-rgb-002",
4366 .data = &lemaker_bl035_rgb_002,
4367 }, {
4368 .compatible = "lg,lb070wv8",
4369 .data = &lg_lb070wv8,
4370 }, {
4371 .compatible = "logicpd,type28",
4372 .data = &logicpd_type_28,
4373 }, {
4374 .compatible = "logictechno,lt161010-2nhc",
4375 .data = &logictechno_lt161010_2nh,
4376 }, {
4377 .compatible = "logictechno,lt161010-2nhr",
4378 .data = &logictechno_lt161010_2nh,
4379 }, {
4380 .compatible = "logictechno,lt170410-2whc",
4381 .data = &logictechno_lt170410_2whc,
4382 }, {
4383 .compatible = "logictechno,lttd800480070-l2rt",
4384 .data = &logictechno_lttd800480070_l2rt,
4385 }, {
4386 .compatible = "logictechno,lttd800480070-l6wh-rt",
4387 .data = &logictechno_lttd800480070_l6wh_rt,
4388 }, {
4389 .compatible = "mitsubishi,aa070mc01-ca1",
4390 .data = &mitsubishi_aa070mc01,
4391 }, {
4392 .compatible = "multi-inno,mi0700s4t-6",
4393 .data = &multi_inno_mi0700s4t_6,
4394 }, {
4395 .compatible = "multi-inno,mi0800ft-9",
4396 .data = &multi_inno_mi0800ft_9,
4397 }, {
4398 .compatible = "multi-inno,mi1010ait-1cp",
4399 .data = &multi_inno_mi1010ait_1cp,
4400 }, {
4401 .compatible = "nec,nl12880bc20-05",
4402 .data = &nec_nl12880bc20_05,
4403 }, {
4404 .compatible = "nec,nl4827hc19-05b",
4405 .data = &nec_nl4827hc19_05b,
4406 }, {
4407 .compatible = "netron-dy,e231732",
4408 .data = &netron_dy_e231732,
4409 }, {
4410 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4411 .data = &newhaven_nhd_43_480272ef_atxl,
4412 }, {
4413 .compatible = "nlt,nl192108ac18-02d",
4414 .data = &nlt_nl192108ac18_02d,
4415 }, {
4416 .compatible = "nvd,9128",
4417 .data = &nvd_9128,
4418 }, {
4419 .compatible = "okaya,rs800480t-7x0gp",
4420 .data = &okaya_rs800480t_7x0gp,
4421 }, {
4422 .compatible = "olimex,lcd-olinuxino-43-ts",
4423 .data = &olimex_lcd_olinuxino_43ts,
4424 }, {
4425 .compatible = "ontat,yx700wv03",
4426 .data = &ontat_yx700wv03,
4427 }, {
4428 .compatible = "ortustech,com37h3m05dtc",
4429 .data = &ortustech_com37h3m,
4430 }, {
4431 .compatible = "ortustech,com37h3m99dtc",
4432 .data = &ortustech_com37h3m,
4433 }, {
4434 .compatible = "ortustech,com43h4m85ulc",
4435 .data = &ortustech_com43h4m85ulc,
4436 }, {
4437 .compatible = "osddisplays,osd070t1718-19ts",
4438 .data = &osddisplays_osd070t1718_19ts,
4439 }, {
4440 .compatible = "pda,91-00156-a0",
4441 .data = &pda_91_00156_a0,
4442 }, {
4443 .compatible = "powertip,ph800480t013-idf02",
4444 .data = &powertip_ph800480t013_idf02,
4445 }, {
4446 .compatible = "qiaodian,qd43003c0-40",
4447 .data = &qd43003c0_40,
4448 }, {
4449 .compatible = "qishenglong,gopher2b-lcd",
4450 .data = &qishenglong_gopher2b_lcd,
4451 }, {
4452 .compatible = "rocktech,rk043fn48h",
4453 .data = &rocktech_rk043fn48h,
4454 }, {
4455 .compatible = "rocktech,rk070er9427",
4456 .data = &rocktech_rk070er9427,
4457 }, {
4458 .compatible = "rocktech,rk101ii01d-ct",
4459 .data = &rocktech_rk101ii01d_ct,
4460 }, {
4461 .compatible = "samsung,ltl101al01",
4462 .data = &samsung_ltl101al01,
4463 }, {
4464 .compatible = "samsung,ltn101nt05",
4465 .data = &samsung_ltn101nt05,
4466 }, {
4467 .compatible = "satoz,sat050at40h12r2",
4468 .data = &satoz_sat050at40h12r2,
4469 }, {
4470 .compatible = "sharp,lq035q7db03",
4471 .data = &sharp_lq035q7db03,
4472 }, {
4473 .compatible = "sharp,lq070y3dg3b",
4474 .data = &sharp_lq070y3dg3b,
4475 }, {
4476 .compatible = "sharp,lq101k1ly04",
4477 .data = &sharp_lq101k1ly04,
4478 }, {
4479 .compatible = "sharp,ls020b1dd01d",
4480 .data = &sharp_ls020b1dd01d,
4481 }, {
4482 .compatible = "shelly,sca07010-bfn-lnn",
4483 .data = &shelly_sca07010_bfn_lnn,
4484 }, {
4485 .compatible = "starry,kr070pe2t",
4486 .data = &starry_kr070pe2t,
4487 }, {
4488 .compatible = "startek,kd070wvfpa",
4489 .data = &startek_kd070wvfpa,
4490 }, {
4491 .compatible = "team-source-display,tst043015cmhx",
4492 .data = &tsd_tst043015cmhx,
4493 }, {
4494 .compatible = "tfc,s9700rtwv43tr-01b",
4495 .data = &tfc_s9700rtwv43tr_01b,
4496 }, {
4497 .compatible = "tianma,tm070jdhg30",
4498 .data = &tianma_tm070jdhg30,
4499 }, {
4500 .compatible = "tianma,tm070jvhg33",
4501 .data = &tianma_tm070jvhg33,
4502 }, {
4503 .compatible = "tianma,tm070rvhg71",
4504 .data = &tianma_tm070rvhg71,
4505 }, {
4506 .compatible = "ti,nspire-cx-lcd-panel",
4507 .data = &ti_nspire_cx_lcd_panel,
4508 }, {
4509 .compatible = "ti,nspire-classic-lcd-panel",
4510 .data = &ti_nspire_classic_lcd_panel,
4511 }, {
4512 .compatible = "toshiba,lt089ac29000",
4513 .data = &toshiba_lt089ac29000,
4514 }, {
4515 .compatible = "tpk,f07a-0102",
4516 .data = &tpk_f07a_0102,
4517 }, {
4518 .compatible = "tpk,f10a-0102",
4519 .data = &tpk_f10a_0102,
4520 }, {
4521 .compatible = "urt,umsh-8596md-t",
4522 .data = &urt_umsh_8596md_parallel,
4523 }, {
4524 .compatible = "urt,umsh-8596md-1t",
4525 .data = &urt_umsh_8596md_parallel,
4526 }, {
4527 .compatible = "urt,umsh-8596md-7t",
4528 .data = &urt_umsh_8596md_parallel,
4529 }, {
4530 .compatible = "urt,umsh-8596md-11t",
4531 .data = &urt_umsh_8596md_lvds,
4532 }, {
4533 .compatible = "urt,umsh-8596md-19t",
4534 .data = &urt_umsh_8596md_lvds,
4535 }, {
4536 .compatible = "urt,umsh-8596md-20t",
4537 .data = &urt_umsh_8596md_parallel,
4538 }, {
4539 .compatible = "vivax,tpc9150-panel",
4540 .data = &vivax_tpc9150_panel,
4541 }, {
4542 .compatible = "vxt,vl050-8048nt-c01",
4543 .data = &vl050_8048nt_c01,
4544 }, {
4545 .compatible = "winstar,wf35ltiacd",
4546 .data = &winstar_wf35ltiacd,
4547 }, {
4548 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4549 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4550 }, {
4551 .compatible = "microchip,ac69t88a",
4552 .data = &mchp_ac69t88a,
4553 }, {
4554 /* Must be the last entry */
4555 .compatible = "panel-dpi",
4556 .data = &panel_dpi,
4557 }, {
4558 /* sentinel */
4559 }
4560 };
4561 MODULE_DEVICE_TABLE(of, platform_of_match);
4562
panel_simple_platform_probe(struct platform_device * pdev)4563 static int panel_simple_platform_probe(struct platform_device *pdev)
4564 {
4565 const struct panel_desc *desc;
4566
4567 desc = of_device_get_match_data(&pdev->dev);
4568 if (!desc)
4569 return -ENODEV;
4570
4571 return panel_simple_probe(&pdev->dev, desc);
4572 }
4573
panel_simple_platform_remove(struct platform_device * pdev)4574 static void panel_simple_platform_remove(struct platform_device *pdev)
4575 {
4576 panel_simple_remove(&pdev->dev);
4577 }
4578
panel_simple_platform_shutdown(struct platform_device * pdev)4579 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4580 {
4581 panel_simple_shutdown(&pdev->dev);
4582 }
4583
4584 static const struct dev_pm_ops panel_simple_pm_ops = {
4585 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4586 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4587 pm_runtime_force_resume)
4588 };
4589
4590 static struct platform_driver panel_simple_platform_driver = {
4591 .driver = {
4592 .name = "panel-simple",
4593 .of_match_table = platform_of_match,
4594 .pm = &panel_simple_pm_ops,
4595 },
4596 .probe = panel_simple_platform_probe,
4597 .remove_new = panel_simple_platform_remove,
4598 .shutdown = panel_simple_platform_shutdown,
4599 };
4600
4601 struct panel_desc_dsi {
4602 struct panel_desc desc;
4603
4604 unsigned long flags;
4605 enum mipi_dsi_pixel_format format;
4606 unsigned int lanes;
4607 };
4608
4609 static const struct drm_display_mode auo_b080uan01_mode = {
4610 .clock = 154500,
4611 .hdisplay = 1200,
4612 .hsync_start = 1200 + 62,
4613 .hsync_end = 1200 + 62 + 4,
4614 .htotal = 1200 + 62 + 4 + 62,
4615 .vdisplay = 1920,
4616 .vsync_start = 1920 + 9,
4617 .vsync_end = 1920 + 9 + 2,
4618 .vtotal = 1920 + 9 + 2 + 8,
4619 };
4620
4621 static const struct panel_desc_dsi auo_b080uan01 = {
4622 .desc = {
4623 .modes = &auo_b080uan01_mode,
4624 .num_modes = 1,
4625 .bpc = 8,
4626 .size = {
4627 .width = 108,
4628 .height = 272,
4629 },
4630 .connector_type = DRM_MODE_CONNECTOR_DSI,
4631 },
4632 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4633 .format = MIPI_DSI_FMT_RGB888,
4634 .lanes = 4,
4635 };
4636
4637 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4638 .clock = 160000,
4639 .hdisplay = 1200,
4640 .hsync_start = 1200 + 120,
4641 .hsync_end = 1200 + 120 + 20,
4642 .htotal = 1200 + 120 + 20 + 21,
4643 .vdisplay = 1920,
4644 .vsync_start = 1920 + 21,
4645 .vsync_end = 1920 + 21 + 3,
4646 .vtotal = 1920 + 21 + 3 + 18,
4647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4648 };
4649
4650 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4651 .desc = {
4652 .modes = &boe_tv080wum_nl0_mode,
4653 .num_modes = 1,
4654 .size = {
4655 .width = 107,
4656 .height = 172,
4657 },
4658 .connector_type = DRM_MODE_CONNECTOR_DSI,
4659 },
4660 .flags = MIPI_DSI_MODE_VIDEO |
4661 MIPI_DSI_MODE_VIDEO_BURST |
4662 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4663 .format = MIPI_DSI_FMT_RGB888,
4664 .lanes = 4,
4665 };
4666
4667 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4668 .clock = 71000,
4669 .hdisplay = 800,
4670 .hsync_start = 800 + 32,
4671 .hsync_end = 800 + 32 + 1,
4672 .htotal = 800 + 32 + 1 + 57,
4673 .vdisplay = 1280,
4674 .vsync_start = 1280 + 28,
4675 .vsync_end = 1280 + 28 + 1,
4676 .vtotal = 1280 + 28 + 1 + 14,
4677 };
4678
4679 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4680 .desc = {
4681 .modes = &lg_ld070wx3_sl01_mode,
4682 .num_modes = 1,
4683 .bpc = 8,
4684 .size = {
4685 .width = 94,
4686 .height = 151,
4687 },
4688 .connector_type = DRM_MODE_CONNECTOR_DSI,
4689 },
4690 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4691 .format = MIPI_DSI_FMT_RGB888,
4692 .lanes = 4,
4693 };
4694
4695 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4696 .clock = 67000,
4697 .hdisplay = 720,
4698 .hsync_start = 720 + 12,
4699 .hsync_end = 720 + 12 + 4,
4700 .htotal = 720 + 12 + 4 + 112,
4701 .vdisplay = 1280,
4702 .vsync_start = 1280 + 8,
4703 .vsync_end = 1280 + 8 + 4,
4704 .vtotal = 1280 + 8 + 4 + 12,
4705 };
4706
4707 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4708 .desc = {
4709 .modes = &lg_lh500wx1_sd03_mode,
4710 .num_modes = 1,
4711 .bpc = 8,
4712 .size = {
4713 .width = 62,
4714 .height = 110,
4715 },
4716 .connector_type = DRM_MODE_CONNECTOR_DSI,
4717 },
4718 .flags = MIPI_DSI_MODE_VIDEO,
4719 .format = MIPI_DSI_FMT_RGB888,
4720 .lanes = 4,
4721 };
4722
4723 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4724 .clock = 157200,
4725 .hdisplay = 1920,
4726 .hsync_start = 1920 + 154,
4727 .hsync_end = 1920 + 154 + 16,
4728 .htotal = 1920 + 154 + 16 + 32,
4729 .vdisplay = 1200,
4730 .vsync_start = 1200 + 17,
4731 .vsync_end = 1200 + 17 + 2,
4732 .vtotal = 1200 + 17 + 2 + 16,
4733 };
4734
4735 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4736 .desc = {
4737 .modes = &panasonic_vvx10f004b00_mode,
4738 .num_modes = 1,
4739 .bpc = 8,
4740 .size = {
4741 .width = 217,
4742 .height = 136,
4743 },
4744 .connector_type = DRM_MODE_CONNECTOR_DSI,
4745 },
4746 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4747 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4748 .format = MIPI_DSI_FMT_RGB888,
4749 .lanes = 4,
4750 };
4751
4752 static const struct drm_display_mode lg_acx467akm_7_mode = {
4753 .clock = 150000,
4754 .hdisplay = 1080,
4755 .hsync_start = 1080 + 2,
4756 .hsync_end = 1080 + 2 + 2,
4757 .htotal = 1080 + 2 + 2 + 2,
4758 .vdisplay = 1920,
4759 .vsync_start = 1920 + 2,
4760 .vsync_end = 1920 + 2 + 2,
4761 .vtotal = 1920 + 2 + 2 + 2,
4762 };
4763
4764 static const struct panel_desc_dsi lg_acx467akm_7 = {
4765 .desc = {
4766 .modes = &lg_acx467akm_7_mode,
4767 .num_modes = 1,
4768 .bpc = 8,
4769 .size = {
4770 .width = 62,
4771 .height = 110,
4772 },
4773 .connector_type = DRM_MODE_CONNECTOR_DSI,
4774 },
4775 .flags = 0,
4776 .format = MIPI_DSI_FMT_RGB888,
4777 .lanes = 4,
4778 };
4779
4780 static const struct drm_display_mode osd101t2045_53ts_mode = {
4781 .clock = 154500,
4782 .hdisplay = 1920,
4783 .hsync_start = 1920 + 112,
4784 .hsync_end = 1920 + 112 + 16,
4785 .htotal = 1920 + 112 + 16 + 32,
4786 .vdisplay = 1200,
4787 .vsync_start = 1200 + 16,
4788 .vsync_end = 1200 + 16 + 2,
4789 .vtotal = 1200 + 16 + 2 + 16,
4790 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4791 };
4792
4793 static const struct panel_desc_dsi osd101t2045_53ts = {
4794 .desc = {
4795 .modes = &osd101t2045_53ts_mode,
4796 .num_modes = 1,
4797 .bpc = 8,
4798 .size = {
4799 .width = 217,
4800 .height = 136,
4801 },
4802 .connector_type = DRM_MODE_CONNECTOR_DSI,
4803 },
4804 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4805 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4806 MIPI_DSI_MODE_NO_EOT_PACKET,
4807 .format = MIPI_DSI_FMT_RGB888,
4808 .lanes = 4,
4809 };
4810
4811 static const struct of_device_id dsi_of_match[] = {
4812 {
4813 .compatible = "auo,b080uan01",
4814 .data = &auo_b080uan01
4815 }, {
4816 .compatible = "boe,tv080wum-nl0",
4817 .data = &boe_tv080wum_nl0
4818 }, {
4819 .compatible = "lg,ld070wx3-sl01",
4820 .data = &lg_ld070wx3_sl01
4821 }, {
4822 .compatible = "lg,lh500wx1-sd03",
4823 .data = &lg_lh500wx1_sd03
4824 }, {
4825 .compatible = "panasonic,vvx10f004b00",
4826 .data = &panasonic_vvx10f004b00
4827 }, {
4828 .compatible = "lg,acx467akm-7",
4829 .data = &lg_acx467akm_7
4830 }, {
4831 .compatible = "osddisplays,osd101t2045-53ts",
4832 .data = &osd101t2045_53ts
4833 }, {
4834 /* sentinel */
4835 }
4836 };
4837 MODULE_DEVICE_TABLE(of, dsi_of_match);
4838
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)4839 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4840 {
4841 const struct panel_desc_dsi *desc;
4842 int err;
4843
4844 desc = of_device_get_match_data(&dsi->dev);
4845 if (!desc)
4846 return -ENODEV;
4847
4848 err = panel_simple_probe(&dsi->dev, &desc->desc);
4849 if (err < 0)
4850 return err;
4851
4852 dsi->mode_flags = desc->flags;
4853 dsi->format = desc->format;
4854 dsi->lanes = desc->lanes;
4855
4856 err = mipi_dsi_attach(dsi);
4857 if (err) {
4858 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4859
4860 drm_panel_remove(&panel->base);
4861 }
4862
4863 return err;
4864 }
4865
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)4866 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4867 {
4868 int err;
4869
4870 err = mipi_dsi_detach(dsi);
4871 if (err < 0)
4872 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4873
4874 panel_simple_remove(&dsi->dev);
4875 }
4876
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)4877 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4878 {
4879 panel_simple_shutdown(&dsi->dev);
4880 }
4881
4882 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4883 .driver = {
4884 .name = "panel-simple-dsi",
4885 .of_match_table = dsi_of_match,
4886 .pm = &panel_simple_pm_ops,
4887 },
4888 .probe = panel_simple_dsi_probe,
4889 .remove = panel_simple_dsi_remove,
4890 .shutdown = panel_simple_dsi_shutdown,
4891 };
4892
panel_simple_init(void)4893 static int __init panel_simple_init(void)
4894 {
4895 int err;
4896
4897 err = platform_driver_register(&panel_simple_platform_driver);
4898 if (err < 0)
4899 return err;
4900
4901 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4902 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4903 if (err < 0)
4904 goto err_did_platform_register;
4905 }
4906
4907 return 0;
4908
4909 err_did_platform_register:
4910 platform_driver_unregister(&panel_simple_platform_driver);
4911
4912 return err;
4913 }
4914 module_init(panel_simple_init);
4915
panel_simple_exit(void)4916 static void __exit panel_simple_exit(void)
4917 {
4918 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4919 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4920
4921 platform_driver_unregister(&panel_simple_platform_driver);
4922 }
4923 module_exit(panel_simple_exit);
4924
4925 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4926 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4927 MODULE_LICENSE("GPL and additional rights");
4928