1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Serial Port driver for Tegra devices
4 *
5 * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/clk.h>
10 #include <linux/console.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/reset.h>
16 #include <linux/slab.h>
17
18 #include "8250.h"
19
20 struct tegra_uart {
21 struct clk *clk;
22 struct reset_control *rst;
23 int line;
24 };
25
tegra_uart_handle_break(struct uart_port * p)26 static void tegra_uart_handle_break(struct uart_port *p)
27 {
28 unsigned int status, tmout = 10000;
29
30 while (1) {
31 status = p->serial_in(p, UART_LSR);
32 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)))
33 break;
34
35 p->serial_in(p, UART_RX);
36
37 if (--tmout == 0)
38 break;
39 udelay(1);
40 }
41 }
42
tegra_uart_probe(struct platform_device * pdev)43 static int tegra_uart_probe(struct platform_device *pdev)
44 {
45 struct uart_8250_port port8250;
46 struct tegra_uart *uart;
47 struct uart_port *port;
48 struct resource *res;
49 int ret;
50
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL);
52 if (!uart)
53 return -ENOMEM;
54
55 memset(&port8250, 0, sizeof(port8250));
56
57 port = &port8250.port;
58 spin_lock_init(&port->lock);
59
60 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
61 UPF_FIXED_TYPE;
62 port->iotype = UPIO_MEM32;
63 port->regshift = 2;
64 port->type = PORT_TEGRA;
65 port->irqflags |= IRQF_SHARED;
66 port->dev = &pdev->dev;
67 port->handle_break = tegra_uart_handle_break;
68
69 ret = of_alias_get_id(pdev->dev.of_node, "serial");
70 if (ret >= 0)
71 port->line = ret;
72
73 ret = platform_get_irq(pdev, 0);
74 if (ret < 0)
75 return ret;
76
77 port->irq = ret;
78
79 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
80 if (!res)
81 return -ENODEV;
82
83 port->membase = devm_ioremap(&pdev->dev, res->start,
84 resource_size(res));
85 if (!port->membase)
86 return -ENOMEM;
87
88 port->mapbase = res->start;
89 port->mapsize = resource_size(res);
90
91 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
92 if (IS_ERR(uart->rst))
93 return PTR_ERR(uart->rst);
94
95 if (device_property_read_u32(&pdev->dev, "clock-frequency",
96 &port->uartclk)) {
97 uart->clk = devm_clk_get(&pdev->dev, NULL);
98 if (IS_ERR(uart->clk)) {
99 dev_err(&pdev->dev, "failed to get clock!\n");
100 return -ENODEV;
101 }
102
103 ret = clk_prepare_enable(uart->clk);
104 if (ret < 0)
105 return ret;
106
107 port->uartclk = clk_get_rate(uart->clk);
108 }
109
110 ret = reset_control_deassert(uart->rst);
111 if (ret)
112 goto err_clkdisable;
113
114 ret = serial8250_register_8250_port(&port8250);
115 if (ret < 0)
116 goto err_ctrl_assert;
117
118 platform_set_drvdata(pdev, uart);
119 uart->line = ret;
120
121 return 0;
122
123 err_ctrl_assert:
124 reset_control_assert(uart->rst);
125 err_clkdisable:
126 clk_disable_unprepare(uart->clk);
127
128 return ret;
129 }
130
tegra_uart_remove(struct platform_device * pdev)131 static int tegra_uart_remove(struct platform_device *pdev)
132 {
133 struct tegra_uart *uart = platform_get_drvdata(pdev);
134
135 serial8250_unregister_port(uart->line);
136 reset_control_assert(uart->rst);
137 clk_disable_unprepare(uart->clk);
138
139 return 0;
140 }
141
142 #ifdef CONFIG_PM_SLEEP
tegra_uart_suspend(struct device * dev)143 static int tegra_uart_suspend(struct device *dev)
144 {
145 struct tegra_uart *uart = dev_get_drvdata(dev);
146 struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
147 struct uart_port *port = &port8250->port;
148
149 serial8250_suspend_port(uart->line);
150
151 if (!uart_console(port) || console_suspend_enabled)
152 clk_disable_unprepare(uart->clk);
153
154 return 0;
155 }
156
tegra_uart_resume(struct device * dev)157 static int tegra_uart_resume(struct device *dev)
158 {
159 struct tegra_uart *uart = dev_get_drvdata(dev);
160 struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
161 struct uart_port *port = &port8250->port;
162
163 if (!uart_console(port) || console_suspend_enabled)
164 clk_prepare_enable(uart->clk);
165
166 serial8250_resume_port(uart->line);
167
168 return 0;
169 }
170 #endif
171
172 static SIMPLE_DEV_PM_OPS(tegra_uart_pm_ops, tegra_uart_suspend,
173 tegra_uart_resume);
174
175 static const struct of_device_id tegra_uart_of_match[] = {
176 { .compatible = "nvidia,tegra20-uart", },
177 { },
178 };
179 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
180
181 static const struct acpi_device_id tegra_uart_acpi_match[] __maybe_unused = {
182 { "NVDA0100", 0 },
183 { },
184 };
185 MODULE_DEVICE_TABLE(acpi, tegra_uart_acpi_match);
186
187 static struct platform_driver tegra_uart_driver = {
188 .driver = {
189 .name = "tegra-uart",
190 .pm = &tegra_uart_pm_ops,
191 .of_match_table = tegra_uart_of_match,
192 .acpi_match_table = ACPI_PTR(tegra_uart_acpi_match),
193 },
194 .probe = tegra_uart_probe,
195 .remove = tegra_uart_remove,
196 };
197
198 module_platform_driver(tegra_uart_driver);
199
200 MODULE_AUTHOR("Jeff Brasen <jbrasen@nvidia.com>");
201 MODULE_DESCRIPTION("NVIDIA Tegra 8250 Driver");
202 MODULE_LICENSE("GPL v2");
203