1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/export.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11
12 #include <soc/tegra/common.h>
13 #include <soc/tegra/fuse.h>
14
15 #include "fuse.h"
16
17 #define FUSE_SKU_INFO 0x10
18
19 #define ERD_ERR_CONFIG 0x120c
20 #define ERD_MASK_INBAND_ERR 0x1
21
22 #define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
23 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
24 (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
25 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
26 (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
27
28 static void __iomem *apbmisc_base;
29 static bool long_ram_code;
30 static u32 strapping;
31 static u32 chipid;
32
tegra_read_chipid(void)33 u32 tegra_read_chipid(void)
34 {
35 WARN(!chipid, "Tegra APB MISC not yet available\n");
36
37 return chipid;
38 }
39
tegra_get_chip_id(void)40 u8 tegra_get_chip_id(void)
41 {
42 return (tegra_read_chipid() >> 8) & 0xff;
43 }
44
tegra_get_major_rev(void)45 u8 tegra_get_major_rev(void)
46 {
47 return (tegra_read_chipid() >> 4) & 0xf;
48 }
49
tegra_get_minor_rev(void)50 u8 tegra_get_minor_rev(void)
51 {
52 return (tegra_read_chipid() >> 16) & 0xf;
53 }
54
tegra_get_platform(void)55 u8 tegra_get_platform(void)
56 {
57 return (tegra_read_chipid() >> 20) & 0xf;
58 }
59
tegra_is_silicon(void)60 bool tegra_is_silicon(void)
61 {
62 switch (tegra_get_chip_id()) {
63 case TEGRA194:
64 case TEGRA234:
65 case TEGRA264:
66 if (tegra_get_platform() == 0)
67 return true;
68
69 return false;
70 }
71
72 /*
73 * Chips prior to Tegra194 have a different way of determining whether
74 * they are silicon or not. Since we never supported simulation on the
75 * older Tegra chips, don't bother extracting the information and just
76 * report that we're running on silicon.
77 */
78 return true;
79 }
80
tegra_read_straps(void)81 u32 tegra_read_straps(void)
82 {
83 WARN(!chipid, "Tegra ABP MISC not yet available\n");
84
85 return strapping;
86 }
87
tegra_read_ram_code(void)88 u32 tegra_read_ram_code(void)
89 {
90 u32 straps = tegra_read_straps();
91
92 if (long_ram_code)
93 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
94 else
95 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
96
97 return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
98 }
99 EXPORT_SYMBOL_GPL(tegra_read_ram_code);
100
101 /*
102 * The function sets ERD(Error Response Disable) bit.
103 * This allows to mask inband errors and always send an
104 * OKAY response from CBB to the master which caused error.
105 */
tegra194_miscreg_mask_serror(void)106 int tegra194_miscreg_mask_serror(void)
107 {
108 if (!apbmisc_base)
109 return -EPROBE_DEFER;
110
111 if (!of_machine_is_compatible("nvidia,tegra194")) {
112 WARN(1, "Only supported for Tegra194 devices!\n");
113 return -EOPNOTSUPP;
114 }
115
116 writel_relaxed(ERD_MASK_INBAND_ERR,
117 apbmisc_base + ERD_ERR_CONFIG);
118
119 return 0;
120 }
121 EXPORT_SYMBOL(tegra194_miscreg_mask_serror);
122
123 static const struct of_device_id apbmisc_match[] __initconst = {
124 { .compatible = "nvidia,tegra20-apbmisc", },
125 { .compatible = "nvidia,tegra186-misc", },
126 { .compatible = "nvidia,tegra194-misc", },
127 { .compatible = "nvidia,tegra234-misc", },
128 {},
129 };
130
tegra_init_revision(void)131 void __init tegra_init_revision(void)
132 {
133 u8 chip_id, minor_rev;
134
135 chip_id = tegra_get_chip_id();
136 minor_rev = tegra_get_minor_rev();
137
138 switch (minor_rev) {
139 case 1:
140 tegra_sku_info.revision = TEGRA_REVISION_A01;
141 break;
142 case 2:
143 tegra_sku_info.revision = TEGRA_REVISION_A02;
144 break;
145 case 3:
146 if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
147 tegra_fuse_read_spare(19)))
148 tegra_sku_info.revision = TEGRA_REVISION_A03p;
149 else
150 tegra_sku_info.revision = TEGRA_REVISION_A03;
151 break;
152 case 4:
153 tegra_sku_info.revision = TEGRA_REVISION_A04;
154 break;
155 default:
156 tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
157 }
158
159 tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
160 tegra_sku_info.platform = tegra_get_platform();
161 }
162
tegra_init_apbmisc(void)163 void __init tegra_init_apbmisc(void)
164 {
165 void __iomem *strapping_base;
166 struct resource apbmisc, straps;
167 struct device_node *np;
168
169 np = of_find_matching_node(NULL, apbmisc_match);
170 if (!np) {
171 /*
172 * Fall back to legacy initialization for 32-bit ARM only. All
173 * 64-bit ARM device tree files for Tegra are required to have
174 * an APBMISC node.
175 *
176 * This is for backwards-compatibility with old device trees
177 * that didn't contain an APBMISC node.
178 */
179 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
180 /* APBMISC registers (chip revision, ...) */
181 apbmisc.start = 0x70000800;
182 apbmisc.end = 0x70000863;
183 apbmisc.flags = IORESOURCE_MEM;
184
185 /* strapping options */
186 if (of_machine_is_compatible("nvidia,tegra124")) {
187 straps.start = 0x7000e864;
188 straps.end = 0x7000e867;
189 } else {
190 straps.start = 0x70000008;
191 straps.end = 0x7000000b;
192 }
193
194 straps.flags = IORESOURCE_MEM;
195
196 pr_warn("Using APBMISC region %pR\n", &apbmisc);
197 pr_warn("Using strapping options registers %pR\n",
198 &straps);
199 } else {
200 /*
201 * At this point we're not running on Tegra, so play
202 * nice with multi-platform kernels.
203 */
204 return;
205 }
206 } else {
207 /*
208 * Extract information from the device tree if we've found a
209 * matching node.
210 */
211 if (of_address_to_resource(np, 0, &apbmisc) < 0) {
212 pr_err("failed to get APBMISC registers\n");
213 goto put;
214 }
215
216 if (of_address_to_resource(np, 1, &straps) < 0) {
217 pr_err("failed to get strapping options registers\n");
218 goto put;
219 }
220 }
221
222 apbmisc_base = ioremap(apbmisc.start, resource_size(&apbmisc));
223 if (!apbmisc_base) {
224 pr_err("failed to map APBMISC registers\n");
225 } else {
226 chipid = readl_relaxed(apbmisc_base + 4);
227 }
228
229 strapping_base = ioremap(straps.start, resource_size(&straps));
230 if (!strapping_base) {
231 pr_err("failed to map strapping options registers\n");
232 } else {
233 strapping = readl_relaxed(strapping_base);
234 iounmap(strapping_base);
235 }
236
237 long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
238
239 put:
240 of_node_put(np);
241 }
242