1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <misc.h>
10 #include <asm/arch-tegra/bpmp_abi.h>
11
tegra186_clk_get_rate(struct clk * clk)12 static ulong tegra186_clk_get_rate(struct clk *clk)
13 {
14 struct mrq_clk_request req;
15 struct mrq_clk_response resp;
16 int ret;
17
18 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
19 clk->id);
20
21 req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
22
23 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
24 sizeof(resp));
25 if (ret < 0)
26 return ret;
27
28 return resp.clk_get_rate.rate;
29 }
30
tegra186_clk_set_rate(struct clk * clk,ulong rate)31 static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)
32 {
33 struct mrq_clk_request req;
34 struct mrq_clk_response resp;
35 int ret;
36
37 debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
38 clk->dev, clk->id);
39
40 req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id;
41 req.clk_set_rate.rate = rate;
42
43 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
44 sizeof(resp));
45 if (ret < 0)
46 return ret;
47
48 return resp.clk_set_rate.rate;
49 }
50
tegra186_clk_en_dis(struct clk * clk,enum mrq_reset_commands cmd)51 static int tegra186_clk_en_dis(struct clk *clk,
52 enum mrq_reset_commands cmd)
53 {
54 struct mrq_clk_request req;
55 struct mrq_clk_response resp;
56 int ret;
57
58 req.cmd_and_id = (cmd << 24) | clk->id;
59
60 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
61 sizeof(resp));
62 if (ret < 0)
63 return ret;
64
65 return 0;
66 }
67
tegra186_clk_enable(struct clk * clk)68 static int tegra186_clk_enable(struct clk *clk)
69 {
70 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
71 clk->id);
72
73 return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE);
74 }
75
tegra186_clk_disable(struct clk * clk)76 static int tegra186_clk_disable(struct clk *clk)
77 {
78 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
79 clk->id);
80
81 return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);
82 }
83
84 static struct clk_ops tegra186_clk_ops = {
85 .get_rate = tegra186_clk_get_rate,
86 .set_rate = tegra186_clk_set_rate,
87 .enable = tegra186_clk_enable,
88 .disable = tegra186_clk_disable,
89 };
90
tegra186_clk_probe(struct udevice * dev)91 static int tegra186_clk_probe(struct udevice *dev)
92 {
93 debug("%s(dev=%p)\n", __func__, dev);
94
95 return 0;
96 }
97
98 U_BOOT_DRIVER(tegra186_clk) = {
99 .name = "tegra186_clk",
100 .id = UCLASS_CLK,
101 .probe = tegra186_clk_probe,
102 .ops = &tegra186_clk_ops,
103 };
104