1 /*
2 * QEMU TCG vCPU common functionality
3 *
4 * Functionality common to all TCG vCPU variants: mttcg, rr and icount.
5 *
6 * Copyright (c) 2003-2008 Fabrice Bellard
7 * Copyright (c) 2014 Red Hat Inc.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include "qemu/osdep.h"
29 #include "accel/accel-ops.h"
30 #include "accel/accel-cpu-ops.h"
31 #include "system/tcg.h"
32 #include "system/replay.h"
33 #include "exec/icount.h"
34 #include "qemu/main-loop.h"
35 #include "qemu/guest-random.h"
36 #include "qemu/timer.h"
37 #include "exec/cputlb.h"
38 #include "exec/hwaddr.h"
39 #include "exec/tb-flush.h"
40 #include "exec/translation-block.h"
41 #include "exec/watchpoint.h"
42 #include "gdbstub/enums.h"
43
44 #include "hw/core/cpu.h"
45
46 #include "tcg-accel-ops.h"
47 #include "tcg-accel-ops-mttcg.h"
48 #include "tcg-accel-ops-rr.h"
49 #include "tcg-accel-ops-icount.h"
50
51 /* common functionality among all TCG variants */
52
tcg_cpu_init_cflags(CPUState * cpu,bool parallel)53 void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
54 {
55 uint32_t cflags;
56
57 /*
58 * Include the cluster number in the hash we use to look up TBs.
59 * This is important because a TB that is valid for one cluster at
60 * a given physical address and set of CPU flags is not necessarily
61 * valid for another:
62 * the two clusters may have different views of physical memory, or
63 * may have different CPU features (eg FPU present or absent).
64 */
65 cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
66
67 cflags |= parallel ? CF_PARALLEL : 0;
68 cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
69 tcg_cflags_set(cpu, cflags);
70 }
71
tcg_cpu_destroy(CPUState * cpu)72 void tcg_cpu_destroy(CPUState *cpu)
73 {
74 cpu_thread_signal_destroyed(cpu);
75 }
76
tcg_cpu_exec(CPUState * cpu)77 int tcg_cpu_exec(CPUState *cpu)
78 {
79 int ret;
80 assert(tcg_enabled());
81 cpu_exec_start(cpu);
82 ret = cpu_exec(cpu);
83 cpu_exec_end(cpu);
84
85 qatomic_set_mb(&cpu->exit_request, 0);
86
87 return ret;
88 }
89
tcg_cpu_reset_hold(CPUState * cpu)90 static void tcg_cpu_reset_hold(CPUState *cpu)
91 {
92 tcg_flush_jmp_cache(cpu);
93
94 tlb_flush(cpu);
95 }
96
97 /* mask must never be zero, except for A20 change call */
tcg_handle_interrupt(CPUState * cpu,int mask)98 void tcg_handle_interrupt(CPUState *cpu, int mask)
99 {
100 cpu->interrupt_request |= mask;
101
102 /*
103 * If called from iothread context, wake the target cpu in
104 * case its halted.
105 */
106 if (!qemu_cpu_is_self(cpu)) {
107 qemu_cpu_kick(cpu);
108 } else {
109 qatomic_set(&cpu->neg.icount_decr.u16.high, -1);
110 }
111 }
112
tcg_supports_guest_debug(void)113 static bool tcg_supports_guest_debug(void)
114 {
115 return true;
116 }
117
118 /* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */
xlat_gdb_type(CPUState * cpu,int gdbtype)119 static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
120 {
121 static const int xlat[] = {
122 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
123 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
124 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
125 };
126
127 int cputype = xlat[gdbtype];
128
129 if (cpu->cc->gdb_stop_before_watchpoint) {
130 cputype |= BP_STOP_BEFORE_ACCESS;
131 }
132 return cputype;
133 }
134
tcg_insert_breakpoint(CPUState * cs,int type,vaddr addr,vaddr len)135 static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
136 {
137 CPUState *cpu;
138 int err = 0;
139
140 switch (type) {
141 case GDB_BREAKPOINT_SW:
142 case GDB_BREAKPOINT_HW:
143 CPU_FOREACH(cpu) {
144 err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL);
145 if (err) {
146 break;
147 }
148 }
149 return err;
150 case GDB_WATCHPOINT_WRITE:
151 case GDB_WATCHPOINT_READ:
152 case GDB_WATCHPOINT_ACCESS:
153 CPU_FOREACH(cpu) {
154 err = cpu_watchpoint_insert(cpu, addr, len,
155 xlat_gdb_type(cpu, type), NULL);
156 if (err) {
157 break;
158 }
159 }
160 return err;
161 default:
162 return -ENOSYS;
163 }
164 }
165
tcg_remove_breakpoint(CPUState * cs,int type,vaddr addr,vaddr len)166 static int tcg_remove_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
167 {
168 CPUState *cpu;
169 int err = 0;
170
171 switch (type) {
172 case GDB_BREAKPOINT_SW:
173 case GDB_BREAKPOINT_HW:
174 CPU_FOREACH(cpu) {
175 err = cpu_breakpoint_remove(cpu, addr, BP_GDB);
176 if (err) {
177 break;
178 }
179 }
180 return err;
181 case GDB_WATCHPOINT_WRITE:
182 case GDB_WATCHPOINT_READ:
183 case GDB_WATCHPOINT_ACCESS:
184 CPU_FOREACH(cpu) {
185 err = cpu_watchpoint_remove(cpu, addr, len,
186 xlat_gdb_type(cpu, type));
187 if (err) {
188 break;
189 }
190 }
191 return err;
192 default:
193 return -ENOSYS;
194 }
195 }
196
tcg_remove_all_breakpoints(CPUState * cpu)197 static inline void tcg_remove_all_breakpoints(CPUState *cpu)
198 {
199 cpu_breakpoint_remove_all(cpu, BP_GDB);
200 cpu_watchpoint_remove_all(cpu, BP_GDB);
201 }
202
tcg_accel_ops_init(AccelClass * ac)203 static void tcg_accel_ops_init(AccelClass *ac)
204 {
205 AccelOpsClass *ops = ac->ops;
206
207 if (qemu_tcg_mttcg_enabled()) {
208 ops->create_vcpu_thread = mttcg_start_vcpu_thread;
209 ops->kick_vcpu_thread = mttcg_kick_vcpu_thread;
210 ops->handle_interrupt = tcg_handle_interrupt;
211 } else {
212 ops->create_vcpu_thread = rr_start_vcpu_thread;
213 ops->kick_vcpu_thread = rr_kick_vcpu_thread;
214
215 if (icount_enabled()) {
216 ops->handle_interrupt = icount_handle_interrupt;
217 ops->get_virtual_clock = icount_get;
218 ops->get_elapsed_ticks = icount_get;
219 } else {
220 ops->handle_interrupt = tcg_handle_interrupt;
221 }
222 }
223
224 ops->cpu_reset_hold = tcg_cpu_reset_hold;
225 ops->supports_guest_debug = tcg_supports_guest_debug;
226 ops->insert_breakpoint = tcg_insert_breakpoint;
227 ops->remove_breakpoint = tcg_remove_breakpoint;
228 ops->remove_all_breakpoints = tcg_remove_all_breakpoints;
229 }
230
tcg_accel_ops_class_init(ObjectClass * oc,const void * data)231 static void tcg_accel_ops_class_init(ObjectClass *oc, const void *data)
232 {
233 AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
234
235 ops->ops_init = tcg_accel_ops_init;
236 }
237
238 static const TypeInfo tcg_accel_ops_type = {
239 .name = ACCEL_OPS_NAME("tcg"),
240
241 .parent = TYPE_ACCEL_OPS,
242 .class_init = tcg_accel_ops_class_init,
243 .abstract = true,
244 };
245 module_obj(ACCEL_OPS_NAME("tcg"));
246
tcg_accel_ops_register_types(void)247 static void tcg_accel_ops_register_types(void)
248 {
249 type_register_static(&tcg_accel_ops_type);
250 }
251 type_init(tcg_accel_ops_register_types);
252