1 /*
2 * SMBIOS Support
3 *
4 * Copyright (C) 2009 Hewlett-Packard Development Company, L.P.
5 * Copyright (C) 2013 Red Hat, Inc.
6 *
7 * Authors:
8 * Alex Williamson <alex.williamson@hp.com>
9 * Markus Armbruster <armbru@redhat.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
13 *
14 * Contributions after 2012-01-13 are licensed under the terms of the
15 * GNU GPL, version 2 or (at your option) any later version.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
21 #include "qemu/config-file.h"
22 #include "qemu/module.h"
23 #include "qemu/option.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu/uuid.h"
26 #include "hw/firmware/smbios.h"
27 #include "hw/loader.h"
28 #include "hw/boards.h"
29 #include "hw/pci/pci_bus.h"
30 #include "hw/pci/pci_device.h"
31 #include "smbios_build.h"
32
33 /*
34 * SMBIOS tables provided by user with '-smbios file=<foo>' option
35 */
36 uint8_t *usr_blobs;
37 size_t usr_blobs_len;
38 static unsigned usr_table_max;
39 static unsigned usr_table_cnt;
40
41 uint8_t *smbios_tables;
42 size_t smbios_tables_len;
43 unsigned smbios_table_max;
44 unsigned smbios_table_cnt;
45
46 static SmbiosEntryPoint ep;
47
48 static int smbios_type4_count = 0;
49 static bool smbios_have_defaults;
50 static uint32_t smbios_cpuid_version, smbios_cpuid_features;
51
52 DECLARE_BITMAP(smbios_have_binfile_bitmap, SMBIOS_MAX_TYPE + 1);
53 DECLARE_BITMAP(smbios_have_fields_bitmap, SMBIOS_MAX_TYPE + 1);
54
55 smbios_type0_t smbios_type0;
56 smbios_type1_t smbios_type1;
57
58 static struct {
59 const char *manufacturer, *product, *version, *serial, *asset, *location;
60 } type2;
61
62 static struct {
63 const char *manufacturer, *version, *serial, *asset, *sku;
64 } type3;
65
66 /*
67 * SVVP requires max_speed and current_speed to be set and not being
68 * 0 which counts as unknown (SMBIOS 3.1.0/Table 21). Set the
69 * default value to 2000MHz as we did before.
70 */
71 #define DEFAULT_CPU_SPEED 2000
72
73 static struct {
74 uint16_t processor_family;
75 const char *sock_pfx, *manufacturer, *version, *serial, *asset, *part;
76 uint64_t max_speed;
77 uint64_t current_speed;
78 uint64_t processor_id;
79 } type4 = {
80 .max_speed = DEFAULT_CPU_SPEED,
81 .current_speed = DEFAULT_CPU_SPEED,
82 .processor_id = 0,
83 .processor_family = 0x01, /* Other */
84 };
85
86 struct type8_instance {
87 const char *internal_reference, *external_reference;
88 uint8_t connector_type, port_type;
89 QTAILQ_ENTRY(type8_instance) next;
90 };
91 static QTAILQ_HEAD(, type8_instance) type8 = QTAILQ_HEAD_INITIALIZER(type8);
92
93 /* type 9 instance for parsing */
94 struct type9_instance {
95 const char *slot_designation, *pcidev;
96 uint8_t slot_type, slot_data_bus_width, current_usage, slot_length,
97 slot_characteristics1, slot_characteristics2;
98 uint16_t slot_id;
99 QTAILQ_ENTRY(type9_instance) next;
100 };
101 static QTAILQ_HEAD(, type9_instance) type9 = QTAILQ_HEAD_INITIALIZER(type9);
102
103 static struct {
104 size_t nvalues;
105 char **values;
106 } type11;
107
108 static struct {
109 const char *loc_pfx, *bank, *manufacturer, *serial, *asset, *part;
110 uint16_t speed;
111 } type17;
112
113 static QEnumLookup type41_kind_lookup = {
114 .array = (const char *const[]) {
115 "other",
116 "unknown",
117 "video",
118 "scsi",
119 "ethernet",
120 "tokenring",
121 "sound",
122 "pata",
123 "sata",
124 "sas",
125 },
126 .size = 10
127 };
128 struct type41_instance {
129 const char *designation, *pcidev;
130 uint8_t instance, kind;
131 QTAILQ_ENTRY(type41_instance) next;
132 };
133 static QTAILQ_HEAD(, type41_instance) type41 = QTAILQ_HEAD_INITIALIZER(type41);
134
135 static QemuOptsList qemu_smbios_opts = {
136 .name = "smbios",
137 .head = QTAILQ_HEAD_INITIALIZER(qemu_smbios_opts.head),
138 .desc = {
139 /*
140 * no elements => accept any params
141 * validation will happen later
142 */
143 { /* end of list */ }
144 }
145 };
146
147 static const QemuOptDesc qemu_smbios_file_opts[] = {
148 {
149 .name = "file",
150 .type = QEMU_OPT_STRING,
151 .help = "binary file containing an SMBIOS element",
152 },
153 { /* end of list */ }
154 };
155
156 static const QemuOptDesc qemu_smbios_type0_opts[] = {
157 {
158 .name = "type",
159 .type = QEMU_OPT_NUMBER,
160 .help = "SMBIOS element type",
161 },{
162 .name = "vendor",
163 .type = QEMU_OPT_STRING,
164 .help = "vendor name",
165 },{
166 .name = "version",
167 .type = QEMU_OPT_STRING,
168 .help = "version number",
169 },{
170 .name = "date",
171 .type = QEMU_OPT_STRING,
172 .help = "release date",
173 },{
174 .name = "release",
175 .type = QEMU_OPT_STRING,
176 .help = "revision number",
177 },{
178 .name = "uefi",
179 .type = QEMU_OPT_BOOL,
180 .help = "uefi support",
181 },
182 { /* end of list */ }
183 };
184
185 static const QemuOptDesc qemu_smbios_type1_opts[] = {
186 {
187 .name = "type",
188 .type = QEMU_OPT_NUMBER,
189 .help = "SMBIOS element type",
190 },{
191 .name = "manufacturer",
192 .type = QEMU_OPT_STRING,
193 .help = "manufacturer name",
194 },{
195 .name = "product",
196 .type = QEMU_OPT_STRING,
197 .help = "product name",
198 },{
199 .name = "version",
200 .type = QEMU_OPT_STRING,
201 .help = "version number",
202 },{
203 .name = "serial",
204 .type = QEMU_OPT_STRING,
205 .help = "serial number",
206 },{
207 .name = "uuid",
208 .type = QEMU_OPT_STRING,
209 .help = "UUID",
210 },{
211 .name = "sku",
212 .type = QEMU_OPT_STRING,
213 .help = "SKU number",
214 },{
215 .name = "family",
216 .type = QEMU_OPT_STRING,
217 .help = "family name",
218 },
219 { /* end of list */ }
220 };
221
222 static const QemuOptDesc qemu_smbios_type2_opts[] = {
223 {
224 .name = "type",
225 .type = QEMU_OPT_NUMBER,
226 .help = "SMBIOS element type",
227 },{
228 .name = "manufacturer",
229 .type = QEMU_OPT_STRING,
230 .help = "manufacturer name",
231 },{
232 .name = "product",
233 .type = QEMU_OPT_STRING,
234 .help = "product name",
235 },{
236 .name = "version",
237 .type = QEMU_OPT_STRING,
238 .help = "version number",
239 },{
240 .name = "serial",
241 .type = QEMU_OPT_STRING,
242 .help = "serial number",
243 },{
244 .name = "asset",
245 .type = QEMU_OPT_STRING,
246 .help = "asset tag number",
247 },{
248 .name = "location",
249 .type = QEMU_OPT_STRING,
250 .help = "location in chassis",
251 },
252 { /* end of list */ }
253 };
254
255 static const QemuOptDesc qemu_smbios_type3_opts[] = {
256 {
257 .name = "type",
258 .type = QEMU_OPT_NUMBER,
259 .help = "SMBIOS element type",
260 },{
261 .name = "manufacturer",
262 .type = QEMU_OPT_STRING,
263 .help = "manufacturer name",
264 },{
265 .name = "version",
266 .type = QEMU_OPT_STRING,
267 .help = "version number",
268 },{
269 .name = "serial",
270 .type = QEMU_OPT_STRING,
271 .help = "serial number",
272 },{
273 .name = "asset",
274 .type = QEMU_OPT_STRING,
275 .help = "asset tag number",
276 },{
277 .name = "sku",
278 .type = QEMU_OPT_STRING,
279 .help = "SKU number",
280 },
281 { /* end of list */ }
282 };
283
284 static const QemuOptDesc qemu_smbios_type4_opts[] = {
285 {
286 .name = "type",
287 .type = QEMU_OPT_NUMBER,
288 .help = "SMBIOS element type",
289 },{
290 .name = "sock_pfx",
291 .type = QEMU_OPT_STRING,
292 .help = "socket designation string prefix",
293 },{
294 .name = "manufacturer",
295 .type = QEMU_OPT_STRING,
296 .help = "manufacturer name",
297 },{
298 .name = "version",
299 .type = QEMU_OPT_STRING,
300 .help = "version number",
301 },{
302 .name = "max-speed",
303 .type = QEMU_OPT_NUMBER,
304 .help = "max speed in MHz",
305 },{
306 .name = "current-speed",
307 .type = QEMU_OPT_NUMBER,
308 .help = "speed at system boot in MHz",
309 },{
310 .name = "serial",
311 .type = QEMU_OPT_STRING,
312 .help = "serial number",
313 },{
314 .name = "asset",
315 .type = QEMU_OPT_STRING,
316 .help = "asset tag number",
317 },{
318 .name = "part",
319 .type = QEMU_OPT_STRING,
320 .help = "part number",
321 }, {
322 .name = "processor-family",
323 .type = QEMU_OPT_NUMBER,
324 .help = "processor family",
325 }, {
326 .name = "processor-id",
327 .type = QEMU_OPT_NUMBER,
328 .help = "processor id",
329 },
330 { /* end of list */ }
331 };
332
333 static const QemuOptDesc qemu_smbios_type8_opts[] = {
334 {
335 .name = "type",
336 .type = QEMU_OPT_NUMBER,
337 .help = "SMBIOS element type",
338 },
339 {
340 .name = "internal_reference",
341 .type = QEMU_OPT_STRING,
342 .help = "internal reference designator",
343 },
344 {
345 .name = "external_reference",
346 .type = QEMU_OPT_STRING,
347 .help = "external reference designator",
348 },
349 {
350 .name = "connector_type",
351 .type = QEMU_OPT_NUMBER,
352 .help = "connector type",
353 },
354 {
355 .name = "port_type",
356 .type = QEMU_OPT_NUMBER,
357 .help = "port type",
358 },
359 { /* end of list */ }
360 };
361
362 static const QemuOptDesc qemu_smbios_type9_opts[] = {
363 {
364 .name = "type",
365 .type = QEMU_OPT_NUMBER,
366 .help = "SMBIOS element type",
367 },
368 {
369 .name = "slot_designation",
370 .type = QEMU_OPT_STRING,
371 .help = "string number for reference designation",
372 },
373 {
374 .name = "slot_type",
375 .type = QEMU_OPT_NUMBER,
376 .help = "connector type",
377 },
378 {
379 .name = "slot_data_bus_width",
380 .type = QEMU_OPT_NUMBER,
381 .help = "port type",
382 },
383 {
384 .name = "current_usage",
385 .type = QEMU_OPT_NUMBER,
386 .help = "current usage",
387 },
388 {
389 .name = "slot_length",
390 .type = QEMU_OPT_NUMBER,
391 .help = "system slot length",
392 },
393 {
394 .name = "slot_id",
395 .type = QEMU_OPT_NUMBER,
396 .help = "system slot id",
397 },
398 {
399 .name = "slot_characteristics1",
400 .type = QEMU_OPT_NUMBER,
401 .help = "slot characteristics1, see the spec",
402 },
403 {
404 .name = "slot_characteristics2",
405 .type = QEMU_OPT_NUMBER,
406 .help = "slot characteristics2, see the spec",
407 },
408 {
409 .name = "pci_device",
410 .type = QEMU_OPT_STRING,
411 .help = "PCI device, if provided."
412 }
413 };
414
415 static const QemuOptDesc qemu_smbios_type11_opts[] = {
416 {
417 .name = "type",
418 .type = QEMU_OPT_NUMBER,
419 .help = "SMBIOS element type",
420 },
421 {
422 .name = "value",
423 .type = QEMU_OPT_STRING,
424 .help = "OEM string data",
425 },
426 {
427 .name = "path",
428 .type = QEMU_OPT_STRING,
429 .help = "OEM string data from file",
430 },
431 { /* end of list */ }
432 };
433
434 static const QemuOptDesc qemu_smbios_type17_opts[] = {
435 {
436 .name = "type",
437 .type = QEMU_OPT_NUMBER,
438 .help = "SMBIOS element type",
439 },{
440 .name = "loc_pfx",
441 .type = QEMU_OPT_STRING,
442 .help = "device locator string prefix",
443 },{
444 .name = "bank",
445 .type = QEMU_OPT_STRING,
446 .help = "bank locator string",
447 },{
448 .name = "manufacturer",
449 .type = QEMU_OPT_STRING,
450 .help = "manufacturer name",
451 },{
452 .name = "serial",
453 .type = QEMU_OPT_STRING,
454 .help = "serial number",
455 },{
456 .name = "asset",
457 .type = QEMU_OPT_STRING,
458 .help = "asset tag number",
459 },{
460 .name = "part",
461 .type = QEMU_OPT_STRING,
462 .help = "part number",
463 },{
464 .name = "speed",
465 .type = QEMU_OPT_NUMBER,
466 .help = "maximum capable speed",
467 },
468 { /* end of list */ }
469 };
470
471 static const QemuOptDesc qemu_smbios_type41_opts[] = {
472 {
473 .name = "type",
474 .type = QEMU_OPT_NUMBER,
475 .help = "SMBIOS element type",
476 },{
477 .name = "designation",
478 .type = QEMU_OPT_STRING,
479 .help = "reference designation string",
480 },{
481 .name = "kind",
482 .type = QEMU_OPT_STRING,
483 .help = "device type",
484 .def_value_str = "other",
485 },{
486 .name = "instance",
487 .type = QEMU_OPT_NUMBER,
488 .help = "device type instance",
489 },{
490 .name = "pcidev",
491 .type = QEMU_OPT_STRING,
492 .help = "PCI device",
493 },
494 { /* end of list */ }
495 };
496
smbios_register_config(void)497 static void smbios_register_config(void)
498 {
499 qemu_add_opts(&qemu_smbios_opts);
500 }
501
502 opts_init(smbios_register_config);
503
504 /*
505 * The SMBIOS 2.1 "structure table length" field in the
506 * entry point uses a 16-bit integer, so we're limited
507 * in total table size
508 */
509 #define SMBIOS_21_MAX_TABLES_LEN 0xffff
510
smbios_check_type4_count(uint32_t expected_t4_count,Error ** errp)511 static bool smbios_check_type4_count(uint32_t expected_t4_count, Error **errp)
512 {
513 if (smbios_type4_count && smbios_type4_count != expected_t4_count) {
514 error_setg(errp, "Expected %d SMBIOS Type 4 tables, got %d instead",
515 expected_t4_count, smbios_type4_count);
516 return false;
517 }
518 return true;
519 }
520
smbios_validate_table(SmbiosEntryPointType ep_type,Error ** errp)521 bool smbios_validate_table(SmbiosEntryPointType ep_type, Error **errp)
522 {
523 if (ep_type == SMBIOS_ENTRY_POINT_TYPE_32 &&
524 smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) {
525 error_setg(errp, "SMBIOS 2.1 table length %zu exceeds %d",
526 smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN);
527 return false;
528 }
529 return true;
530 }
531
smbios_skip_table(uint8_t type,bool required_table)532 bool smbios_skip_table(uint8_t type, bool required_table)
533 {
534 if (test_bit(type, smbios_have_binfile_bitmap)) {
535 return true; /* user provided their own binary blob(s) */
536 }
537 if (test_bit(type, smbios_have_fields_bitmap)) {
538 return false; /* user provided fields via command line */
539 }
540 if (smbios_have_defaults && required_table) {
541 return false; /* we're building tables, and this one's required */
542 }
543 return true;
544 }
545
546 #define T0_BASE 0x000
547 #define T1_BASE 0x100
548 #define T2_BASE 0x200
549 #define T3_BASE 0x300
550 #define T4_BASE 0x400
551 #define T9_BASE 0x900
552 #define T11_BASE 0xe00
553
554 #define T16_BASE 0x1000
555 #define T17_BASE 0x1100
556 #define T19_BASE 0x1300
557 #define T32_BASE 0x2000
558 #define T41_BASE 0x2900
559 #define T127_BASE 0x7F00
560
smbios_build_type_0_table(void)561 static void smbios_build_type_0_table(void)
562 {
563 SMBIOS_BUILD_TABLE_PRE(0, T0_BASE, false); /* optional, leave up to BIOS */
564
565 SMBIOS_TABLE_SET_STR(0, vendor_str, smbios_type0.vendor);
566 SMBIOS_TABLE_SET_STR(0, bios_version_str, smbios_type0.version);
567
568 t->bios_starting_address_segment = cpu_to_le16(0xE800); /* from SeaBIOS */
569
570 SMBIOS_TABLE_SET_STR(0, bios_release_date_str, smbios_type0.date);
571
572 t->bios_rom_size = 0; /* hardcoded in SeaBIOS with FIXME comment */
573
574 t->bios_characteristics = cpu_to_le64(0x08); /* Not supported */
575 t->bios_characteristics_extension_bytes[0] = 0;
576 t->bios_characteristics_extension_bytes[1] = 0x14; /* TCD/SVVP | VM */
577 if (smbios_type0.uefi) {
578 t->bios_characteristics_extension_bytes[1] |= 0x08; /* |= UEFI */
579 }
580
581 if (smbios_type0.have_major_minor) {
582 t->system_bios_major_release = smbios_type0.major;
583 t->system_bios_minor_release = smbios_type0.minor;
584 } else {
585 t->system_bios_major_release = 0;
586 t->system_bios_minor_release = 0;
587 }
588
589 /* hardcoded in SeaBIOS */
590 t->embedded_controller_major_release = 0xFF;
591 t->embedded_controller_minor_release = 0xFF;
592
593 SMBIOS_BUILD_TABLE_POST;
594 }
595
596 /* Encode UUID from the big endian encoding described on RFC4122 to the wire
597 * format specified by SMBIOS version 2.6.
598 */
smbios_encode_uuid(struct smbios_uuid * uuid,QemuUUID * in)599 static void smbios_encode_uuid(struct smbios_uuid *uuid, QemuUUID *in)
600 {
601 memcpy(uuid, in, 16);
602 uuid->time_low = bswap32(uuid->time_low);
603 uuid->time_mid = bswap16(uuid->time_mid);
604 uuid->time_hi_and_version = bswap16(uuid->time_hi_and_version);
605 }
606
smbios_build_type_1_table(void)607 static void smbios_build_type_1_table(void)
608 {
609 SMBIOS_BUILD_TABLE_PRE(1, T1_BASE, true); /* required */
610
611 SMBIOS_TABLE_SET_STR(1, manufacturer_str, smbios_type1.manufacturer);
612 SMBIOS_TABLE_SET_STR(1, product_name_str, smbios_type1.product);
613 SMBIOS_TABLE_SET_STR(1, version_str, smbios_type1.version);
614 SMBIOS_TABLE_SET_STR(1, serial_number_str, smbios_type1.serial);
615 if (qemu_uuid_set) {
616 smbios_encode_uuid(&t->uuid, &qemu_uuid);
617 } else {
618 memset(&t->uuid, 0, 16);
619 }
620 t->wake_up_type = 0x06; /* power switch */
621 SMBIOS_TABLE_SET_STR(1, sku_number_str, smbios_type1.sku);
622 SMBIOS_TABLE_SET_STR(1, family_str, smbios_type1.family);
623
624 SMBIOS_BUILD_TABLE_POST;
625 }
626
smbios_build_type_2_table(void)627 static void smbios_build_type_2_table(void)
628 {
629 SMBIOS_BUILD_TABLE_PRE(2, T2_BASE, false); /* optional */
630
631 SMBIOS_TABLE_SET_STR(2, manufacturer_str, type2.manufacturer);
632 SMBIOS_TABLE_SET_STR(2, product_str, type2.product);
633 SMBIOS_TABLE_SET_STR(2, version_str, type2.version);
634 SMBIOS_TABLE_SET_STR(2, serial_number_str, type2.serial);
635 SMBIOS_TABLE_SET_STR(2, asset_tag_number_str, type2.asset);
636 t->feature_flags = 0x01; /* Motherboard */
637 SMBIOS_TABLE_SET_STR(2, location_str, type2.location);
638 t->chassis_handle = cpu_to_le16(0x300); /* Type 3 (System enclosure) */
639 t->board_type = 0x0A; /* Motherboard */
640 t->contained_element_count = 0;
641
642 SMBIOS_BUILD_TABLE_POST;
643 }
644
smbios_build_type_3_table(void)645 static void smbios_build_type_3_table(void)
646 {
647 SMBIOS_BUILD_TABLE_PRE(3, T3_BASE, true); /* required */
648
649 SMBIOS_TABLE_SET_STR(3, manufacturer_str, type3.manufacturer);
650 t->type = 0x01; /* Other */
651 SMBIOS_TABLE_SET_STR(3, version_str, type3.version);
652 SMBIOS_TABLE_SET_STR(3, serial_number_str, type3.serial);
653 SMBIOS_TABLE_SET_STR(3, asset_tag_number_str, type3.asset);
654 t->boot_up_state = 0x03; /* Safe */
655 t->power_supply_state = 0x03; /* Safe */
656 t->thermal_state = 0x03; /* Safe */
657 t->security_status = 0x02; /* Unknown */
658 t->oem_defined = cpu_to_le32(0);
659 t->height = 0;
660 t->number_of_power_cords = 0;
661 t->contained_element_count = 0;
662 t->contained_element_record_length = 0;
663 SMBIOS_TABLE_SET_STR(3, sku_number_str, type3.sku);
664
665 SMBIOS_BUILD_TABLE_POST;
666 }
667
smbios_build_type_4_table(MachineState * ms,unsigned instance,SmbiosEntryPointType ep_type,Error ** errp)668 static void smbios_build_type_4_table(MachineState *ms, unsigned instance,
669 SmbiosEntryPointType ep_type,
670 Error **errp)
671 {
672 char sock_str[128];
673 size_t tbl_len = SMBIOS_TYPE_4_LEN_V28;
674 unsigned threads_per_socket;
675 unsigned cores_per_socket;
676
677 if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
678 tbl_len = SMBIOS_TYPE_4_LEN_V30;
679 }
680
681 SMBIOS_BUILD_TABLE_PRE_SIZE(4, T4_BASE + instance,
682 true, tbl_len); /* required */
683
684 snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance);
685 SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str);
686 t->processor_type = 0x03; /* CPU */
687 t->processor_family = 0xfe; /* use Processor Family 2 field */
688 SMBIOS_TABLE_SET_STR(4, processor_manufacturer_str, type4.manufacturer);
689 if (type4.processor_id == 0) {
690 t->processor_id[0] = cpu_to_le32(smbios_cpuid_version);
691 t->processor_id[1] = cpu_to_le32(smbios_cpuid_features);
692 } else {
693 t->processor_id[0] = cpu_to_le32((uint32_t)type4.processor_id);
694 t->processor_id[1] = cpu_to_le32(type4.processor_id >> 32);
695 }
696 SMBIOS_TABLE_SET_STR(4, processor_version_str, type4.version);
697 t->voltage = 0;
698 t->external_clock = cpu_to_le16(0); /* Unknown */
699 t->max_speed = cpu_to_le16(type4.max_speed);
700 t->current_speed = cpu_to_le16(type4.current_speed);
701 t->status = 0x41; /* Socket populated, CPU enabled */
702 t->processor_upgrade = 0x01; /* Other */
703 t->l1_cache_handle = cpu_to_le16(0xFFFF); /* N/A */
704 t->l2_cache_handle = cpu_to_le16(0xFFFF); /* N/A */
705 t->l3_cache_handle = cpu_to_le16(0xFFFF); /* N/A */
706 SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial);
707 SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset);
708 SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
709
710 threads_per_socket = machine_topo_get_threads_per_socket(ms);
711 cores_per_socket = machine_topo_get_cores_per_socket(ms);
712
713 t->core_count = (cores_per_socket > 255) ? 0xFF : cores_per_socket;
714 t->core_enabled = t->core_count;
715
716 t->thread_count = (threads_per_socket > 255) ? 0xFF : threads_per_socket;
717
718 t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */
719 t->processor_family2 = cpu_to_le16(type4.processor_family);
720
721 if (tbl_len == SMBIOS_TYPE_4_LEN_V30) {
722 t->core_count2 = t->core_enabled2 = cpu_to_le16(cores_per_socket);
723 t->thread_count2 = cpu_to_le16(threads_per_socket);
724 } else if (t->core_count == 0xFF || t->thread_count == 0xFF) {
725 error_setg(errp, "SMBIOS 2.0 doesn't support number of processor "
726 "cores/threads more than 255, use "
727 "-machine smbios-entry-point-type=64 option to enable "
728 "SMBIOS 3.0 support");
729 return;
730 }
731
732 SMBIOS_BUILD_TABLE_POST;
733 smbios_type4_count++;
734 }
735
smbios_build_type_8_table(void)736 static void smbios_build_type_8_table(void)
737 {
738 unsigned instance = 0;
739 struct type8_instance *t8;
740
741 QTAILQ_FOREACH(t8, &type8, next) {
742 SMBIOS_BUILD_TABLE_PRE(8, T0_BASE + instance, true);
743
744 SMBIOS_TABLE_SET_STR(8, internal_reference_str, t8->internal_reference);
745 SMBIOS_TABLE_SET_STR(8, external_reference_str, t8->external_reference);
746 /* most vendors seem to set this to None */
747 t->internal_connector_type = 0x0;
748 t->external_connector_type = t8->connector_type;
749 t->port_type = t8->port_type;
750
751 SMBIOS_BUILD_TABLE_POST;
752 instance++;
753 }
754 }
755
smbios_build_type_9_table(Error ** errp)756 static void smbios_build_type_9_table(Error **errp)
757 {
758 unsigned instance = 0;
759 struct type9_instance *t9;
760
761 QTAILQ_FOREACH(t9, &type9, next) {
762 SMBIOS_BUILD_TABLE_PRE(9, T9_BASE + instance, true);
763
764 SMBIOS_TABLE_SET_STR(9, slot_designation, t9->slot_designation);
765 t->slot_type = t9->slot_type;
766 t->slot_data_bus_width = t9->slot_data_bus_width;
767 t->current_usage = t9->current_usage;
768 t->slot_length = t9->slot_length;
769 t->slot_id = t9->slot_id;
770 t->slot_characteristics1 = t9->slot_characteristics1;
771 t->slot_characteristics2 = t9->slot_characteristics2;
772
773 if (t9->pcidev) {
774 PCIDevice *pdev = NULL;
775 int rc = pci_qdev_find_device(t9->pcidev, &pdev);
776 if (rc != 0) {
777 error_setg(errp,
778 "No PCI device %s for SMBIOS type 9 entry %s",
779 t9->pcidev, t9->slot_designation);
780 return;
781 }
782 /*
783 * We only handle the case were the device is attached to
784 * the PCI root bus. The general case is more complex as
785 * bridges are enumerated later and the table would need
786 * to be updated at this moment.
787 */
788 if (!pci_bus_is_root(pci_get_bus(pdev))) {
789 error_setg(errp,
790 "Cannot create type 9 entry for PCI device %s: "
791 "not attached to the root bus",
792 t9->pcidev);
793 return;
794 }
795 t->segment_group_number = cpu_to_le16(0);
796 t->bus_number = pci_dev_bus_num(pdev);
797 t->device_number = pdev->devfn;
798 } else {
799 /*
800 * Per SMBIOS spec, For slots that are not of the PCI, AGP, PCI-X,
801 * or PCI-Express type that do not have bus/device/function
802 * information, 0FFh should be populated in the fields of Segment
803 * Group Number, Bus Number, Device/Function Number.
804 */
805 t->segment_group_number = 0xff;
806 t->bus_number = 0xff;
807 t->device_number = 0xff;
808 }
809
810 SMBIOS_BUILD_TABLE_POST;
811 instance++;
812 }
813 }
814
smbios_build_type_11_table(void)815 static void smbios_build_type_11_table(void)
816 {
817 char count_str[128];
818 size_t i;
819
820 if (type11.nvalues == 0) {
821 return;
822 }
823
824 SMBIOS_BUILD_TABLE_PRE(11, T11_BASE, true); /* required */
825
826 snprintf(count_str, sizeof(count_str), "%zu", type11.nvalues);
827 t->count = type11.nvalues;
828
829 for (i = 0; i < type11.nvalues; i++) {
830 SMBIOS_TABLE_SET_STR_LIST(11, type11.values[i]);
831 g_free(type11.values[i]);
832 type11.values[i] = NULL;
833 }
834
835 SMBIOS_BUILD_TABLE_POST;
836 }
837
838 #define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */
839
smbios_build_type_16_table(unsigned dimm_cnt)840 static void smbios_build_type_16_table(unsigned dimm_cnt)
841 {
842 uint64_t size_kb;
843
844 SMBIOS_BUILD_TABLE_PRE(16, T16_BASE, true); /* required */
845
846 t->location = 0x01; /* Other */
847 t->use = 0x03; /* System memory */
848 t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */
849 size_kb = QEMU_ALIGN_UP(current_machine->ram_size, KiB) / KiB;
850 if (size_kb < MAX_T16_STD_SZ) {
851 t->maximum_capacity = cpu_to_le32(size_kb);
852 t->extended_maximum_capacity = cpu_to_le64(0);
853 } else {
854 t->maximum_capacity = cpu_to_le32(MAX_T16_STD_SZ);
855 t->extended_maximum_capacity = cpu_to_le64(current_machine->ram_size);
856 }
857 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
858 t->number_of_memory_devices = cpu_to_le16(dimm_cnt);
859
860 SMBIOS_BUILD_TABLE_POST;
861 }
862
863 #define MAX_T17_STD_SZ 0x7FFF /* (32G - 1M), in Megabytes */
864 #define MAX_T17_EXT_SZ 0x80000000 /* 2P, in Megabytes */
865
smbios_build_type_17_table(unsigned instance,uint64_t size)866 static void smbios_build_type_17_table(unsigned instance, uint64_t size)
867 {
868 char loc_str[128];
869 uint64_t size_mb;
870
871 SMBIOS_BUILD_TABLE_PRE(17, T17_BASE + instance, true); /* required */
872
873 t->physical_memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */
874 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
875 t->total_width = cpu_to_le16(0xFFFF); /* Unknown */
876 t->data_width = cpu_to_le16(0xFFFF); /* Unknown */
877 size_mb = QEMU_ALIGN_UP(size, MiB) / MiB;
878 if (size_mb < MAX_T17_STD_SZ) {
879 t->size = cpu_to_le16(size_mb);
880 t->extended_size = cpu_to_le32(0);
881 } else {
882 assert(size_mb < MAX_T17_EXT_SZ);
883 t->size = cpu_to_le16(MAX_T17_STD_SZ);
884 t->extended_size = cpu_to_le32(size_mb);
885 }
886 t->form_factor = 0x09; /* DIMM */
887 t->device_set = 0; /* Not in a set */
888 snprintf(loc_str, sizeof(loc_str), "%s %d", type17.loc_pfx, instance);
889 SMBIOS_TABLE_SET_STR(17, device_locator_str, loc_str);
890 SMBIOS_TABLE_SET_STR(17, bank_locator_str, type17.bank);
891 t->memory_type = 0x07; /* RAM */
892 t->type_detail = cpu_to_le16(0x02); /* Other */
893 t->speed = cpu_to_le16(type17.speed);
894 SMBIOS_TABLE_SET_STR(17, manufacturer_str, type17.manufacturer);
895 SMBIOS_TABLE_SET_STR(17, serial_number_str, type17.serial);
896 SMBIOS_TABLE_SET_STR(17, asset_tag_number_str, type17.asset);
897 SMBIOS_TABLE_SET_STR(17, part_number_str, type17.part);
898 t->attributes = 0; /* Unknown */
899 t->configured_clock_speed = t->speed; /* reuse value for max speed */
900 t->minimum_voltage = cpu_to_le16(0); /* Unknown */
901 t->maximum_voltage = cpu_to_le16(0); /* Unknown */
902 t->configured_voltage = cpu_to_le16(0); /* Unknown */
903
904 SMBIOS_BUILD_TABLE_POST;
905 }
906
smbios_build_type_19_table(unsigned instance,unsigned offset,uint64_t start,uint64_t size)907 static void smbios_build_type_19_table(unsigned instance, unsigned offset,
908 uint64_t start, uint64_t size)
909 {
910 uint64_t end, start_kb, end_kb;
911
912 SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + offset + instance,
913 true); /* required */
914
915 end = start + size - 1;
916 assert(end > start);
917 start_kb = start / KiB;
918 end_kb = end / KiB;
919 if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) {
920 t->starting_address = cpu_to_le32(start_kb);
921 t->ending_address = cpu_to_le32(end_kb);
922 t->extended_starting_address =
923 t->extended_ending_address = cpu_to_le64(0);
924 } else {
925 t->starting_address = t->ending_address = cpu_to_le32(UINT32_MAX);
926 t->extended_starting_address = cpu_to_le64(start);
927 t->extended_ending_address = cpu_to_le64(end);
928 }
929 t->memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */
930 t->partition_width = 1; /* One device per row */
931
932 SMBIOS_BUILD_TABLE_POST;
933 }
934
smbios_build_type_32_table(void)935 static void smbios_build_type_32_table(void)
936 {
937 SMBIOS_BUILD_TABLE_PRE(32, T32_BASE, true); /* required */
938
939 memset(t->reserved, 0, 6);
940 t->boot_status = 0; /* No errors detected */
941
942 SMBIOS_BUILD_TABLE_POST;
943 }
944
smbios_build_type_41_table(Error ** errp)945 static void smbios_build_type_41_table(Error **errp)
946 {
947 unsigned instance = 0;
948 struct type41_instance *t41;
949
950 QTAILQ_FOREACH(t41, &type41, next) {
951 SMBIOS_BUILD_TABLE_PRE(41, T41_BASE + instance, true);
952
953 SMBIOS_TABLE_SET_STR(41, reference_designation_str, t41->designation);
954 t->device_type = t41->kind;
955 t->device_type_instance = t41->instance;
956 t->segment_group_number = cpu_to_le16(0);
957 t->bus_number = 0;
958 t->device_number = 0;
959
960 if (t41->pcidev) {
961 PCIDevice *pdev = NULL;
962 int rc = pci_qdev_find_device(t41->pcidev, &pdev);
963 if (rc != 0) {
964 error_setg(errp,
965 "No PCI device %s for SMBIOS type 41 entry %s",
966 t41->pcidev, t41->designation);
967 return;
968 }
969 /*
970 * We only handle the case were the device is attached to
971 * the PCI root bus. The general case is more complex as
972 * bridges are enumerated later and the table would need
973 * to be updated at this moment.
974 */
975 if (!pci_bus_is_root(pci_get_bus(pdev))) {
976 error_setg(errp,
977 "Cannot create type 41 entry for PCI device %s: "
978 "not attached to the root bus",
979 t41->pcidev);
980 return;
981 }
982 t->segment_group_number = cpu_to_le16(0);
983 t->bus_number = pci_dev_bus_num(pdev);
984 t->device_number = pdev->devfn;
985 }
986
987 SMBIOS_BUILD_TABLE_POST;
988 instance++;
989 }
990 }
991
smbios_build_type_127_table(void)992 static void smbios_build_type_127_table(void)
993 {
994 SMBIOS_BUILD_TABLE_PRE(127, T127_BASE, true); /* required */
995 SMBIOS_BUILD_TABLE_POST;
996 }
997
smbios_set_cpuid(uint32_t version,uint32_t features)998 void smbios_set_cpuid(uint32_t version, uint32_t features)
999 {
1000 smbios_cpuid_version = version;
1001 smbios_cpuid_features = features;
1002 }
1003
1004 #define SMBIOS_SET_DEFAULT(field, value) \
1005 if (!field) { \
1006 field = value; \
1007 }
1008
smbios_set_default_processor_family(uint16_t processor_family)1009 void smbios_set_default_processor_family(uint16_t processor_family)
1010 {
1011 if (type4.processor_family <= 0x01) {
1012 type4.processor_family = processor_family;
1013 }
1014 }
1015
smbios_set_defaults(const char * manufacturer,const char * product,const char * version)1016 void smbios_set_defaults(const char *manufacturer, const char *product,
1017 const char *version)
1018 {
1019 smbios_have_defaults = true;
1020
1021 SMBIOS_SET_DEFAULT(smbios_type1.manufacturer, manufacturer);
1022 SMBIOS_SET_DEFAULT(smbios_type1.product, product);
1023 SMBIOS_SET_DEFAULT(smbios_type1.version, version);
1024 SMBIOS_SET_DEFAULT(type2.manufacturer, manufacturer);
1025 SMBIOS_SET_DEFAULT(type2.product, product);
1026 SMBIOS_SET_DEFAULT(type2.version, version);
1027 SMBIOS_SET_DEFAULT(type3.manufacturer, manufacturer);
1028 SMBIOS_SET_DEFAULT(type3.version, version);
1029 SMBIOS_SET_DEFAULT(type4.sock_pfx, "CPU");
1030 SMBIOS_SET_DEFAULT(type4.manufacturer, manufacturer);
1031 SMBIOS_SET_DEFAULT(type4.version, version);
1032 SMBIOS_SET_DEFAULT(type17.loc_pfx, "DIMM");
1033 SMBIOS_SET_DEFAULT(type17.manufacturer, manufacturer);
1034 }
1035
smbios_entry_point_setup(SmbiosEntryPointType ep_type)1036 static void smbios_entry_point_setup(SmbiosEntryPointType ep_type)
1037 {
1038 switch (ep_type) {
1039 case SMBIOS_ENTRY_POINT_TYPE_32:
1040 memcpy(ep.ep21.anchor_string, "_SM_", 4);
1041 memcpy(ep.ep21.intermediate_anchor_string, "_DMI_", 5);
1042 ep.ep21.length = sizeof(struct smbios_21_entry_point);
1043 ep.ep21.entry_point_revision = 0; /* formatted_area reserved */
1044 memset(ep.ep21.formatted_area, 0, 5);
1045
1046 /* compliant with smbios spec v2.8 */
1047 ep.ep21.smbios_major_version = 2;
1048 ep.ep21.smbios_minor_version = 8;
1049 ep.ep21.smbios_bcd_revision = 0x28;
1050
1051 /* set during table construction, but BIOS may override: */
1052 ep.ep21.structure_table_length = cpu_to_le16(smbios_tables_len);
1053 ep.ep21.max_structure_size = cpu_to_le16(smbios_table_max);
1054 ep.ep21.number_of_structures = cpu_to_le16(smbios_table_cnt);
1055
1056 /* BIOS must recalculate */
1057 ep.ep21.checksum = 0;
1058 ep.ep21.intermediate_checksum = 0;
1059 ep.ep21.structure_table_address = cpu_to_le32(0);
1060
1061 break;
1062 case SMBIOS_ENTRY_POINT_TYPE_64:
1063 memcpy(ep.ep30.anchor_string, "_SM3_", 5);
1064 ep.ep30.length = sizeof(struct smbios_30_entry_point);
1065 ep.ep30.entry_point_revision = 1;
1066 ep.ep30.reserved = 0;
1067
1068 /* compliant with smbios spec 3.0 */
1069 ep.ep30.smbios_major_version = 3;
1070 ep.ep30.smbios_minor_version = 0;
1071 ep.ep30.smbios_doc_rev = 0;
1072
1073 /* set during table construct, but BIOS might override */
1074 ep.ep30.structure_table_max_size = cpu_to_le32(smbios_tables_len);
1075
1076 /* BIOS must recalculate */
1077 ep.ep30.checksum = 0;
1078 ep.ep30.structure_table_address = cpu_to_le64(0);
1079
1080 break;
1081 default:
1082 abort();
1083 break;
1084 }
1085 }
1086
smbios_get_tables_ep(MachineState * ms,SmbiosEntryPointType ep_type,const struct smbios_phys_mem_area * mem_array,const unsigned int mem_array_size,uint8_t ** tables,size_t * tables_len,uint8_t ** anchor,size_t * anchor_len,Error ** errp)1087 static bool smbios_get_tables_ep(MachineState *ms,
1088 SmbiosEntryPointType ep_type,
1089 const struct smbios_phys_mem_area *mem_array,
1090 const unsigned int mem_array_size,
1091 uint8_t **tables, size_t *tables_len,
1092 uint8_t **anchor, size_t *anchor_len,
1093 Error **errp)
1094 {
1095 unsigned i, dimm_cnt, offset;
1096 MachineClass *mc = MACHINE_GET_CLASS(ms);
1097 ERRP_GUARD();
1098
1099 assert(ep_type == SMBIOS_ENTRY_POINT_TYPE_32 ||
1100 ep_type == SMBIOS_ENTRY_POINT_TYPE_64);
1101
1102 g_free(smbios_tables);
1103 smbios_type4_count = 0;
1104 smbios_tables = g_memdup2(usr_blobs, usr_blobs_len);
1105 smbios_tables_len = usr_blobs_len;
1106 smbios_table_max = usr_table_max;
1107 smbios_table_cnt = usr_table_cnt;
1108
1109 smbios_build_type_0_table();
1110 smbios_build_type_1_table();
1111 smbios_build_type_2_table();
1112 smbios_build_type_3_table();
1113
1114 assert(ms->smp.sockets >= 1);
1115
1116 for (i = 0; i < ms->smp.sockets; i++) {
1117 smbios_build_type_4_table(ms, i, ep_type, errp);
1118 if (*errp) {
1119 goto err_exit;
1120 }
1121 }
1122
1123 smbios_build_type_8_table();
1124 smbios_build_type_9_table(errp);
1125 smbios_build_type_11_table();
1126
1127 #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? mc->smbios_memory_device_size \
1128 : ((current_machine->ram_size - 1) % mc->smbios_memory_device_size) + 1)
1129
1130 dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size,
1131 mc->smbios_memory_device_size) /
1132 mc->smbios_memory_device_size;
1133
1134 /*
1135 * The offset determines if we need to keep additional space between
1136 * table 17 and table 19 header handle numbers so that they do
1137 * not overlap. For example, for a VM with larger than 8 TB guest
1138 * memory and DIMM like chunks of 16 GiB, the default space between
1139 * the two tables (T19_BASE - T17_BASE = 512) is not enough.
1140 */
1141 offset = (dimm_cnt > (T19_BASE - T17_BASE)) ? \
1142 dimm_cnt - (T19_BASE - T17_BASE) : 0;
1143
1144 smbios_build_type_16_table(dimm_cnt);
1145
1146 for (i = 0; i < dimm_cnt; i++) {
1147 smbios_build_type_17_table(i, GET_DIMM_SZ);
1148 }
1149
1150 for (i = 0; i < mem_array_size; i++) {
1151 smbios_build_type_19_table(i, offset, mem_array[i].address,
1152 mem_array[i].length);
1153 }
1154
1155 /*
1156 * make sure 16 bit handle numbers in the headers of tables 19
1157 * and 32 do not overlap.
1158 */
1159 assert((mem_array_size + offset) < (T32_BASE - T19_BASE));
1160
1161 smbios_build_type_32_table();
1162 smbios_build_type_38_table();
1163 smbios_build_type_41_table(errp);
1164 smbios_build_type_127_table();
1165
1166 if (!smbios_check_type4_count(ms->smp.sockets, errp)) {
1167 goto err_exit;
1168 }
1169 if (!smbios_validate_table(ep_type, errp)) {
1170 goto err_exit;
1171 }
1172 smbios_entry_point_setup(ep_type);
1173
1174 /* return tables blob and entry point (anchor), and their sizes */
1175 *tables = smbios_tables;
1176 *tables_len = smbios_tables_len;
1177 *anchor = (uint8_t *)&ep;
1178 /* calculate length based on anchor string */
1179 if (!strncmp((char *)&ep, "_SM_", 4)) {
1180 *anchor_len = sizeof(struct smbios_21_entry_point);
1181 } else if (!strncmp((char *)&ep, "_SM3_", 5)) {
1182 *anchor_len = sizeof(struct smbios_30_entry_point);
1183 } else {
1184 abort();
1185 }
1186
1187 return true;
1188 err_exit:
1189 g_free(smbios_tables);
1190 smbios_tables = NULL;
1191 return false;
1192 }
1193
smbios_get_tables(MachineState * ms,SmbiosEntryPointType ep_type,const struct smbios_phys_mem_area * mem_array,const unsigned int mem_array_size,uint8_t ** tables,size_t * tables_len,uint8_t ** anchor,size_t * anchor_len,Error ** errp)1194 void smbios_get_tables(MachineState *ms,
1195 SmbiosEntryPointType ep_type,
1196 const struct smbios_phys_mem_area *mem_array,
1197 const unsigned int mem_array_size,
1198 uint8_t **tables, size_t *tables_len,
1199 uint8_t **anchor, size_t *anchor_len,
1200 Error **errp)
1201 {
1202 Error *local_err = NULL;
1203 bool is_valid;
1204 ERRP_GUARD();
1205
1206 switch (ep_type) {
1207 case SMBIOS_ENTRY_POINT_TYPE_AUTO:
1208 case SMBIOS_ENTRY_POINT_TYPE_32:
1209 is_valid = smbios_get_tables_ep(ms, SMBIOS_ENTRY_POINT_TYPE_32,
1210 mem_array, mem_array_size,
1211 tables, tables_len,
1212 anchor, anchor_len,
1213 &local_err);
1214 if (is_valid || ep_type != SMBIOS_ENTRY_POINT_TYPE_AUTO) {
1215 break;
1216 }
1217 /*
1218 * fall through in case AUTO endpoint is selected and
1219 * SMBIOS 2.x tables can't be generated, to try if SMBIOS 3.x
1220 * tables would work
1221 */
1222 case SMBIOS_ENTRY_POINT_TYPE_64:
1223 error_free(local_err);
1224 local_err = NULL;
1225 is_valid = smbios_get_tables_ep(ms, SMBIOS_ENTRY_POINT_TYPE_64,
1226 mem_array, mem_array_size,
1227 tables, tables_len,
1228 anchor, anchor_len,
1229 &local_err);
1230 break;
1231 default:
1232 abort();
1233 }
1234 if (!is_valid) {
1235 error_propagate(errp, local_err);
1236 }
1237 }
1238
save_opt(const char ** dest,QemuOpts * opts,const char * name)1239 static void save_opt(const char **dest, QemuOpts *opts, const char *name)
1240 {
1241 const char *val = qemu_opt_get(opts, name);
1242
1243 if (val) {
1244 *dest = val;
1245 }
1246 }
1247
1248
1249 struct opt_list {
1250 size_t *ndest;
1251 char ***dest;
1252 };
1253
save_opt_one(void * opaque,const char * name,const char * value,Error ** errp)1254 static int save_opt_one(void *opaque,
1255 const char *name, const char *value,
1256 Error **errp)
1257 {
1258 struct opt_list *opt = opaque;
1259
1260 if (g_str_equal(name, "path")) {
1261 g_autoptr(GByteArray) data = g_byte_array_new();
1262 g_autofree char *buf = g_new(char, 4096);
1263 ssize_t ret;
1264 int fd = qemu_open(value, O_RDONLY, errp);
1265 if (fd < 0) {
1266 return -1;
1267 }
1268
1269 while (1) {
1270 ret = read(fd, buf, 4096);
1271 if (ret == 0) {
1272 break;
1273 }
1274 if (ret < 0) {
1275 error_setg(errp, "Unable to read from %s: %s",
1276 value, strerror(errno));
1277 qemu_close(fd);
1278 return -1;
1279 }
1280 if (memchr(buf, '\0', ret)) {
1281 error_setg(errp, "NUL in OEM strings value in %s", value);
1282 qemu_close(fd);
1283 return -1;
1284 }
1285 g_byte_array_append(data, (guint8 *)buf, ret);
1286 }
1287
1288 qemu_close(fd);
1289
1290 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1);
1291 (*opt->dest)[*opt->ndest] = (char *)g_byte_array_free(data, FALSE);
1292 (*opt->ndest)++;
1293 data = NULL;
1294 } else if (g_str_equal(name, "value")) {
1295 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1);
1296 (*opt->dest)[*opt->ndest] = g_strdup(value);
1297 (*opt->ndest)++;
1298 } else if (!g_str_equal(name, "type")) {
1299 error_setg(errp, "Unexpected option %s", name);
1300 return -1;
1301 }
1302
1303 return 0;
1304 }
1305
save_opt_list(size_t * ndest,char *** dest,QemuOpts * opts,Error ** errp)1306 static bool save_opt_list(size_t *ndest, char ***dest, QemuOpts *opts,
1307 Error **errp)
1308 {
1309 struct opt_list opt = {
1310 ndest, dest,
1311 };
1312 if (!qemu_opt_foreach(opts, save_opt_one, &opt, errp)) {
1313 return false;
1314 }
1315 return true;
1316 }
1317
smbios_entry_add(QemuOpts * opts,Error ** errp)1318 void smbios_entry_add(QemuOpts *opts, Error **errp)
1319 {
1320 const char *val;
1321
1322 val = qemu_opt_get(opts, "file");
1323 if (val) {
1324 struct smbios_structure_header *header;
1325 size_t size;
1326
1327 if (!qemu_opts_validate(opts, qemu_smbios_file_opts, errp)) {
1328 return;
1329 }
1330
1331 size = get_image_size(val);
1332 if (size == -1 || size < sizeof(struct smbios_structure_header)) {
1333 error_setg(errp, "Cannot read SMBIOS file %s", val);
1334 return;
1335 }
1336
1337 /*
1338 * NOTE: standard double '\0' terminator expected, per smbios spec.
1339 * (except in legacy mode, where the second '\0' is implicit and
1340 * will be inserted by the BIOS).
1341 */
1342 usr_blobs = g_realloc(usr_blobs, usr_blobs_len + size);
1343 header = (struct smbios_structure_header *)(usr_blobs +
1344 usr_blobs_len);
1345
1346 if (load_image_size(val, (uint8_t *)header, size) != size) {
1347 error_setg(errp, "Failed to load SMBIOS file %s", val);
1348 return;
1349 }
1350
1351 if (header->type <= SMBIOS_MAX_TYPE) {
1352 if (test_bit(header->type, smbios_have_fields_bitmap)) {
1353 error_setg(errp,
1354 "can't load type %d struct, fields already specified!",
1355 header->type);
1356 return;
1357 }
1358 set_bit(header->type, smbios_have_binfile_bitmap);
1359 }
1360
1361 if (header->type == 4) {
1362 smbios_type4_count++;
1363 }
1364
1365 /*
1366 * preserve blob size for legacy mode so it could build its
1367 * blobs flavor from 'usr_blobs'
1368 */
1369 smbios_add_usr_blob_size(size);
1370
1371 usr_blobs_len += size;
1372 if (size > usr_table_max) {
1373 usr_table_max = size;
1374 }
1375 usr_table_cnt++;
1376
1377 return;
1378 }
1379
1380 val = qemu_opt_get(opts, "type");
1381 if (val) {
1382 unsigned long type = strtoul(val, NULL, 0);
1383
1384 if (type > SMBIOS_MAX_TYPE) {
1385 error_setg(errp, "out of range!");
1386 return;
1387 }
1388
1389 if (test_bit(type, smbios_have_binfile_bitmap)) {
1390 error_setg(errp, "can't add fields, binary file already loaded!");
1391 return;
1392 }
1393 set_bit(type, smbios_have_fields_bitmap);
1394
1395 switch (type) {
1396 case 0:
1397 if (!qemu_opts_validate(opts, qemu_smbios_type0_opts, errp)) {
1398 return;
1399 }
1400 save_opt(&smbios_type0.vendor, opts, "vendor");
1401 save_opt(&smbios_type0.version, opts, "version");
1402 save_opt(&smbios_type0.date, opts, "date");
1403 smbios_type0.uefi = qemu_opt_get_bool(opts, "uefi", false);
1404
1405 val = qemu_opt_get(opts, "release");
1406 if (val) {
1407 if (sscanf(val, "%hhu.%hhu", &smbios_type0.major,
1408 &smbios_type0.minor) != 2) {
1409 error_setg(errp, "Invalid release");
1410 return;
1411 }
1412 smbios_type0.have_major_minor = true;
1413 }
1414 return;
1415 case 1:
1416 if (!qemu_opts_validate(opts, qemu_smbios_type1_opts, errp)) {
1417 return;
1418 }
1419 save_opt(&smbios_type1.manufacturer, opts, "manufacturer");
1420 save_opt(&smbios_type1.product, opts, "product");
1421 save_opt(&smbios_type1.version, opts, "version");
1422 save_opt(&smbios_type1.serial, opts, "serial");
1423 save_opt(&smbios_type1.sku, opts, "sku");
1424 save_opt(&smbios_type1.family, opts, "family");
1425
1426 val = qemu_opt_get(opts, "uuid");
1427 if (val) {
1428 if (qemu_uuid_parse(val, &qemu_uuid) != 0) {
1429 error_setg(errp, "Invalid UUID");
1430 return;
1431 }
1432 qemu_uuid_set = true;
1433 }
1434 return;
1435 case 2:
1436 if (!qemu_opts_validate(opts, qemu_smbios_type2_opts, errp)) {
1437 return;
1438 }
1439 save_opt(&type2.manufacturer, opts, "manufacturer");
1440 save_opt(&type2.product, opts, "product");
1441 save_opt(&type2.version, opts, "version");
1442 save_opt(&type2.serial, opts, "serial");
1443 save_opt(&type2.asset, opts, "asset");
1444 save_opt(&type2.location, opts, "location");
1445 return;
1446 case 3:
1447 if (!qemu_opts_validate(opts, qemu_smbios_type3_opts, errp)) {
1448 return;
1449 }
1450 save_opt(&type3.manufacturer, opts, "manufacturer");
1451 save_opt(&type3.version, opts, "version");
1452 save_opt(&type3.serial, opts, "serial");
1453 save_opt(&type3.asset, opts, "asset");
1454 save_opt(&type3.sku, opts, "sku");
1455 return;
1456 case 4:
1457 if (!qemu_opts_validate(opts, qemu_smbios_type4_opts, errp)) {
1458 return;
1459 }
1460 save_opt(&type4.sock_pfx, opts, "sock_pfx");
1461 type4.processor_family = qemu_opt_get_number(opts,
1462 "processor-family",
1463 0x01 /* Other */);
1464 save_opt(&type4.manufacturer, opts, "manufacturer");
1465 save_opt(&type4.version, opts, "version");
1466 save_opt(&type4.serial, opts, "serial");
1467 save_opt(&type4.asset, opts, "asset");
1468 save_opt(&type4.part, opts, "part");
1469 /* If the value is 0, it will take the value from the CPU model. */
1470 type4.processor_id = qemu_opt_get_number(opts, "processor-id", 0);
1471 type4.max_speed = qemu_opt_get_number(opts, "max-speed",
1472 DEFAULT_CPU_SPEED);
1473 type4.current_speed = qemu_opt_get_number(opts, "current-speed",
1474 DEFAULT_CPU_SPEED);
1475 if (type4.max_speed > UINT16_MAX ||
1476 type4.current_speed > UINT16_MAX) {
1477 error_setg(errp, "SMBIOS CPU speed is too large (> %d)",
1478 UINT16_MAX);
1479 }
1480 return;
1481 case 8:
1482 if (!qemu_opts_validate(opts, qemu_smbios_type8_opts, errp)) {
1483 return;
1484 }
1485 struct type8_instance *t8_i;
1486 t8_i = g_new0(struct type8_instance, 1);
1487 save_opt(&t8_i->internal_reference, opts, "internal_reference");
1488 save_opt(&t8_i->external_reference, opts, "external_reference");
1489 t8_i->connector_type = qemu_opt_get_number(opts,
1490 "connector_type", 0);
1491 t8_i->port_type = qemu_opt_get_number(opts, "port_type", 0);
1492 QTAILQ_INSERT_TAIL(&type8, t8_i, next);
1493 return;
1494 case 9: {
1495 if (!qemu_opts_validate(opts, qemu_smbios_type9_opts, errp)) {
1496 return;
1497 }
1498 struct type9_instance *t;
1499 t = g_new0(struct type9_instance, 1);
1500 save_opt(&t->slot_designation, opts, "slot_designation");
1501 t->slot_type = qemu_opt_get_number(opts, "slot_type", 0);
1502 t->slot_data_bus_width =
1503 qemu_opt_get_number(opts, "slot_data_bus_width", 0);
1504 t->current_usage = qemu_opt_get_number(opts, "current_usage", 0);
1505 t->slot_length = qemu_opt_get_number(opts, "slot_length", 0);
1506 t->slot_id = qemu_opt_get_number(opts, "slot_id", 0);
1507 t->slot_characteristics1 =
1508 qemu_opt_get_number(opts, "slot_characteristics1", 0);
1509 t->slot_characteristics2 =
1510 qemu_opt_get_number(opts, "slot_characteristics2", 0);
1511 save_opt(&t->pcidev, opts, "pcidev");
1512 QTAILQ_INSERT_TAIL(&type9, t, next);
1513 return;
1514 }
1515 case 11:
1516 if (!qemu_opts_validate(opts, qemu_smbios_type11_opts, errp)) {
1517 return;
1518 }
1519 if (!save_opt_list(&type11.nvalues, &type11.values, opts, errp)) {
1520 return;
1521 }
1522 return;
1523 case 17:
1524 if (!qemu_opts_validate(opts, qemu_smbios_type17_opts, errp)) {
1525 return;
1526 }
1527 save_opt(&type17.loc_pfx, opts, "loc_pfx");
1528 save_opt(&type17.bank, opts, "bank");
1529 save_opt(&type17.manufacturer, opts, "manufacturer");
1530 save_opt(&type17.serial, opts, "serial");
1531 save_opt(&type17.asset, opts, "asset");
1532 save_opt(&type17.part, opts, "part");
1533 type17.speed = qemu_opt_get_number(opts, "speed", 0);
1534 return;
1535 case 41: {
1536 struct type41_instance *t41_i;
1537 Error *local_err = NULL;
1538
1539 if (!qemu_opts_validate(opts, qemu_smbios_type41_opts, errp)) {
1540 return;
1541 }
1542 t41_i = g_new0(struct type41_instance, 1);
1543 save_opt(&t41_i->designation, opts, "designation");
1544 t41_i->kind = qapi_enum_parse(&type41_kind_lookup,
1545 qemu_opt_get(opts, "kind"),
1546 0, &local_err) + 1;
1547 t41_i->kind |= 0x80; /* enabled */
1548 if (local_err != NULL) {
1549 error_propagate(errp, local_err);
1550 g_free(t41_i);
1551 return;
1552 }
1553 t41_i->instance = qemu_opt_get_number(opts, "instance", 1);
1554 save_opt(&t41_i->pcidev, opts, "pcidev");
1555
1556 QTAILQ_INSERT_TAIL(&type41, t41_i, next);
1557 return;
1558 }
1559 default:
1560 error_setg(errp,
1561 "Don't know how to build fields for SMBIOS type %ld",
1562 type);
1563 return;
1564 }
1565 }
1566
1567 error_setg(errp, "Must specify type= or file=");
1568 }
1569