1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mx6-ddr.h>
15 #include <asm/arch/sys_proto.h>
16 #include <errno.h>
17 #include <asm/gpio.h>
18 #include <malloc.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/spi.h>
23 #include <mmc.h>
24 #include <fsl_esdhc.h>
25 #include <miiphy.h>
26 #include <netdev.h>
27 #include <i2c.h>
28 #include <environment.h>
29
30 #include <dm.h>
31 #include <dm/platform_data/serial_mxc.h>
32 #include <dm/platdata.h>
33
34 #ifndef CONFIG_MXC_SPI
35 #error "CONFIG_SPI must be set for this board"
36 #error "Please check your config file"
37 #endif
38
39 #include "common.h"
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 static bool hw_ids_valid;
44 static bool sw_ids_valid;
45 static u32 cpu_id;
46 static u32 unit_id;
47
48 #define EM_PAD IMX_GPIO_NR(3, 29)
49 #define SW0 IMX_GPIO_NR(2, 4)
50 #define SW1 IMX_GPIO_NR(2, 5)
51 #define SW2 IMX_GPIO_NR(2, 6)
52 #define SW3 IMX_GPIO_NR(2, 7)
53 #define HW0 IMX_GPIO_NR(6, 7)
54 #define HW1 IMX_GPIO_NR(6, 9)
55 #define HW2 IMX_GPIO_NR(6, 10)
56 #define HW3 IMX_GPIO_NR(6, 11)
57 #define HW4 IMX_GPIO_NR(4, 7)
58 #define HW5 IMX_GPIO_NR(4, 11)
59 #define HW6 IMX_GPIO_NR(4, 13)
60 #define HW7 IMX_GPIO_NR(4, 15)
61
62 int gpio_table_sw_ids[] = {
63 SW0, SW1, SW2, SW3
64 };
65
66 const char *gpio_table_sw_ids_names[] = {
67 "sw0", "sw1", "sw2", "sw3"
68 };
69
70 int gpio_table_hw_ids[] = {
71 HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
72 };
73
74 const char *gpio_table_hw_ids_names[] = {
75 "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
76 };
77
get_board_id(int * ids,const char ** c,int size,bool * valid,u32 * id)78 static int get_board_id(int *ids, const char **c, int size,
79 bool *valid, u32 *id)
80 {
81 int i, ret, val;
82
83 *valid = false;
84
85 for (i = 0; i < size; i++) {
86 ret = gpio_request(ids[i], c[i]);
87 if (ret) {
88 printf("Can't request SWx gpios\n");
89 return ret;
90 }
91 }
92
93 for (i = 0; i < size; i++) {
94 ret = gpio_direction_input(ids[i]);
95 if (ret) {
96 printf("Can't set SWx gpios direction\n");
97 return ret;
98 }
99 }
100
101 for (i = 0; i < size; i++) {
102 val = gpio_get_value(ids[i]);
103 if (val < 0) {
104 printf("Can't get SW%d ID\n", i);
105 *id = 0;
106 return val;
107 }
108 *id |= val << i;
109 }
110 *valid = true;
111
112 return 0;
113 }
114
dram_init(void)115 int dram_init(void)
116 {
117 gd->ram_size = imx_ddr_size();
118
119 return 0;
120 }
121
122 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
123 /* I2C1: TFA9879 */
124 struct i2c_pads_info i2c_pad_info0 = {
125 .scl = {
126 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
127 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
128 .gp = IMX_GPIO_NR(3, 21)
129 },
130 .sda = {
131 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
132 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
133 .gp = IMX_GPIO_NR(3, 28)
134 }
135 };
136
137 /* I2C2: TIVO TM4C123 */
138 struct i2c_pads_info i2c_pad_info1 = {
139 .scl = {
140 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
141 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
142 .gp = IMX_GPIO_NR(2, 30)
143 },
144 .sda = {
145 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
146 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
147 .gp = IMX_GPIO_NR(3, 16)
148 }
149 };
150
151 /* I2C3: PMIC PF0100, EEPROM AT24C256C */
152 struct i2c_pads_info i2c_pad_info2 = {
153 .scl = {
154 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
155 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
156 .gp = IMX_GPIO_NR(3, 17)
157 },
158 .sda = {
159 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
160 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
161 .gp = IMX_GPIO_NR(3, 18)
162 }
163 };
164
165 iomux_v3_cfg_t const misc_pads[] = {
166 /* Prod ID GPIO pins */
167 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
168 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
169 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
170 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
171
172 /* HW revision GPIO pins */
173 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
175 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
177 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
178 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
179 MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
180 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
181
182 /* XTALOSC */
183 MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
184
185 /* Emergency recovery pin */
186 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
187 };
188
189 #ifdef CONFIG_FSL_ESDHC
190 struct fsl_esdhc_cfg usdhc_cfg[1] = {
191 { USDHC4_BASE_ADDR, 0, 8, },
192 };
193
board_mmc_getcd(struct mmc * mmc)194 int board_mmc_getcd(struct mmc *mmc)
195 {
196 return 1;
197 }
198
board_mmc_init(bd_t * bis)199 int board_mmc_init(bd_t *bis)
200 {
201 displ5_set_iomux_usdhc();
202
203 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
204
205 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
206 }
207 #endif /* CONFIG_FSL_ESDHC */
208
displ5_setup_ecspi(void)209 static void displ5_setup_ecspi(void)
210 {
211 int ret;
212
213 displ5_set_iomux_ecspi();
214
215 ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
216 if (!ret)
217 gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
218
219 ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
220 if (!ret)
221 gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
222 }
223
224 #ifdef CONFIG_FEC_MXC
225 iomux_v3_cfg_t const enet_pads[] = {
226 MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
230 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
231
232 /* for old evalboard with R159 present and R160 not populated */
233 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
234
235 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
237 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
239 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
240 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
241
242 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
243 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
244 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
245 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
246 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
247 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
248 /*INT#_GBE*/
249 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
250 };
251
setup_iomux_enet(void)252 static void setup_iomux_enet(void)
253 {
254 SETUP_IOMUX_PADS(enet_pads);
255 gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
256 }
257
setup_mac_from_fuse(void)258 static int setup_mac_from_fuse(void)
259 {
260 unsigned char enetaddr[6];
261 int ret;
262
263 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
264 if (ret) /* ethaddr is already set */
265 return 0;
266
267 imx_get_mac_from_fuse(0, enetaddr);
268
269 if (is_valid_ethaddr(enetaddr)) {
270 eth_env_set_enetaddr("ethaddr", enetaddr);
271 return 0;
272 }
273
274 return 0;
275 }
276
board_eth_init(bd_t * bd)277 int board_eth_init(bd_t *bd)
278 {
279 struct phy_device *phydev;
280 struct mii_dev *bus;
281 int ret;
282
283 setup_iomux_enet();
284
285 iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
286
287 ret = enable_fec_anatop_clock(0, ENET_125MHZ);
288 if (ret)
289 return ret;
290
291 setup_mac_from_fuse();
292
293 bus = fec_get_miibus(IMX_FEC_BASE, -1);
294 if (!bus)
295 return -ENODEV;
296
297 /*
298 * We use here the "rgmii-id" mode of operation and allow M88E1512
299 * PHY to use its internally callibrated RX/TX delays
300 */
301 phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
302 PHY_INTERFACE_MODE_RGMII_ID);
303 if (!phydev) {
304 ret = -ENODEV;
305 goto err_phy;
306 }
307
308 /* display5 due to PCB routing can only work with 100 Mbps */
309 phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
310 ADVERTISED_1000baseX_Full |
311 SUPPORTED_1000baseT_Half |
312 SUPPORTED_1000baseT_Full);
313
314 ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
315 if (ret)
316 goto err_sw;
317
318 return 0;
319
320 err_sw:
321 free(phydev);
322 err_phy:
323 mdio_unregister(bus);
324 free(bus);
325 return ret;
326 }
327 #endif /* CONFIG_FEC_MXC */
328
329 /*
330 * Do not overwrite the console
331 * Always use serial for U-Boot console
332 */
overwrite_console(void)333 int overwrite_console(void)
334 {
335 return 1;
336 }
337
338 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)339 int ft_board_setup(void *blob, bd_t *bd)
340 {
341 fdt_fixup_ethernet(blob);
342 return 0;
343 }
344 #endif
345
board_init(void)346 int board_init(void)
347 {
348 debug("board init\n");
349 /* address of boot parameters */
350 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
351
352 /* Setup iomux for non console UARTS */
353 displ5_set_iomux_uart();
354
355 displ5_setup_ecspi();
356
357 SETUP_IOMUX_PADS(misc_pads);
358
359 get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
360 ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
361 debug("SWx unit_id 0x%x\n", unit_id);
362
363 get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
364 ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
365 debug("HWx cpu_id 0x%x\n", cpu_id);
366
367 if (hw_ids_valid && sw_ids_valid)
368 printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
369
370 udelay(25);
371
372 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
373 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
374 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
375
376 return 0;
377 }
378
379 #ifdef CONFIG_CMD_BMODE
380 static const struct boot_mode board_boot_modes[] = {
381 /* eMMC, USDHC-4, 8-bit bus width */
382 /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
383 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
384 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
385 {NULL, 0},
386 };
387
setup_boot_modes(void)388 static void setup_boot_modes(void)
389 {
390 add_board_boot_modes(board_boot_modes);
391 }
392 #else
setup_boot_modes(void)393 static inline void setup_boot_modes(void) {}
394 #endif
395
misc_init_r(void)396 int misc_init_r(void)
397 {
398 int ret;
399
400 setup_boot_modes();
401
402 ret = gpio_request(EM_PAD, "Emergency_PAD");
403 if (ret) {
404 printf("Can't request emergency PAD gpio\n");
405 return ret;
406 }
407
408 ret = gpio_direction_input(EM_PAD);
409 if (ret) {
410 printf("Can't set emergency PAD direction\n");
411 return ret;
412 }
413
414 return 0;
415 }
416
417 static struct mxc_serial_platdata mxc_serial_plat = {
418 .reg = (struct mxc_uart *)UART5_BASE,
419 };
420
421 U_BOOT_DEVICE(mxc_serial) = {
422 .name = "serial_mxc",
423 .platdata = &mxc_serial_plat,
424 };
425