xref: /openbmc/linux/drivers/tty/serial/sunzilog.c (revision 29e5c442)
1 // SPDX-License-Identifier: GPL-2.0
2 /* sunzilog.c: Zilog serial driver for Sparc systems.
3  *
4  * Driver for Zilog serial chips found on Sun workstations and
5  * servers.  This driver could actually be made more generic.
6  *
7  * This is based on the old drivers/sbus/char/zs.c code.  A lot
8  * of code has been simply moved over directly from there but
9  * much has been rewritten.  Credits therefore go out to Eddie
10  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
11  * work there.
12  *
13  * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
14  */
15 
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/delay.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/major.h>
23 #include <linux/string.h>
24 #include <linux/ptrace.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/circ_buf.h>
28 #include <linux/serial.h>
29 #include <linux/sysrq.h>
30 #include <linux/console.h>
31 #include <linux/spinlock.h>
32 #ifdef CONFIG_SERIO
33 #include <linux/serio.h>
34 #endif
35 #include <linux/init.h>
36 #include <linux/of.h>
37 #include <linux/platform_device.h>
38 
39 #include <linux/io.h>
40 #include <asm/irq.h>
41 #include <asm/setup.h>
42 
43 #include <linux/serial_core.h>
44 #include <linux/sunserialcore.h>
45 
46 #include "sunzilog.h"
47 
48 /* On 32-bit sparcs we need to delay after register accesses
49  * to accommodate sun4 systems, but we do not need to flush writes.
50  * On 64-bit sparc we only need to flush single writes to ensure
51  * completion.
52  */
53 #ifndef CONFIG_SPARC64
54 #define ZSDELAY()		udelay(5)
55 #define ZSDELAY_LONG()		udelay(20)
56 #define ZS_WSYNC(channel)	do { } while (0)
57 #else
58 #define ZSDELAY()
59 #define ZSDELAY_LONG()
60 #define ZS_WSYNC(__channel) \
61 	readb(&((__channel)->control))
62 #endif
63 
64 #define ZS_CLOCK		4915200 /* Zilog input clock rate. */
65 #define ZS_CLOCK_DIVISOR	16      /* Divisor this driver uses. */
66 
67 /*
68  * We wrap our port structure around the generic uart_port.
69  */
70 struct uart_sunzilog_port {
71 	struct uart_port		port;
72 
73 	/* IRQ servicing chain.  */
74 	struct uart_sunzilog_port	*next;
75 
76 	/* Current values of Zilog write registers.  */
77 	unsigned char			curregs[NUM_ZSREGS];
78 
79 	unsigned int			flags;
80 #define SUNZILOG_FLAG_CONS_KEYB		0x00000001
81 #define SUNZILOG_FLAG_CONS_MOUSE	0x00000002
82 #define SUNZILOG_FLAG_IS_CONS		0x00000004
83 #define SUNZILOG_FLAG_IS_KGDB		0x00000008
84 #define SUNZILOG_FLAG_MODEM_STATUS	0x00000010
85 #define SUNZILOG_FLAG_IS_CHANNEL_A	0x00000020
86 #define SUNZILOG_FLAG_REGS_HELD		0x00000040
87 #define SUNZILOG_FLAG_TX_STOPPED	0x00000080
88 #define SUNZILOG_FLAG_TX_ACTIVE		0x00000100
89 #define SUNZILOG_FLAG_ESCC		0x00000200
90 #define SUNZILOG_FLAG_ISR_HANDLER	0x00000400
91 
92 	unsigned int cflag;
93 
94 	unsigned char			parity_mask;
95 	unsigned char			prev_status;
96 
97 #ifdef CONFIG_SERIO
98 	struct serio			serio;
99 	int				serio_open;
100 #endif
101 };
102 
103 static void sunzilog_putchar(struct uart_port *port, unsigned char ch);
104 
105 #define ZILOG_CHANNEL_FROM_PORT(PORT)	((struct zilog_channel __iomem *)((PORT)->membase))
106 #define UART_ZILOG(PORT)		((struct uart_sunzilog_port *)(PORT))
107 
108 #define ZS_IS_KEYB(UP)	((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
109 #define ZS_IS_MOUSE(UP)	((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
110 #define ZS_IS_CONS(UP)	((UP)->flags & SUNZILOG_FLAG_IS_CONS)
111 #define ZS_IS_KGDB(UP)	((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
112 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
113 #define ZS_IS_CHANNEL_A(UP)	((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
114 #define ZS_REGS_HELD(UP)	((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
115 #define ZS_TX_STOPPED(UP)	((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
116 #define ZS_TX_ACTIVE(UP)	((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
117 
118 /* Reading and writing Zilog8530 registers.  The delays are to make this
119  * driver work on the Sun4 which needs a settling delay after each chip
120  * register access, other machines handle this in hardware via auxiliary
121  * flip-flops which implement the settle time we do in software.
122  *
123  * The port lock must be held and local IRQs must be disabled
124  * when {read,write}_zsreg is invoked.
125  */
read_zsreg(struct zilog_channel __iomem * channel,unsigned char reg)126 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
127 				unsigned char reg)
128 {
129 	unsigned char retval;
130 
131 	writeb(reg, &channel->control);
132 	ZSDELAY();
133 	retval = readb(&channel->control);
134 	ZSDELAY();
135 
136 	return retval;
137 }
138 
write_zsreg(struct zilog_channel __iomem * channel,unsigned char reg,unsigned char value)139 static void write_zsreg(struct zilog_channel __iomem *channel,
140 			unsigned char reg, unsigned char value)
141 {
142 	writeb(reg, &channel->control);
143 	ZSDELAY();
144 	writeb(value, &channel->control);
145 	ZSDELAY();
146 }
147 
sunzilog_clear_fifo(struct zilog_channel __iomem * channel)148 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
149 {
150 	int i;
151 
152 	for (i = 0; i < 32; i++) {
153 		unsigned char regval;
154 
155 		regval = readb(&channel->control);
156 		ZSDELAY();
157 		if (regval & Rx_CH_AV)
158 			break;
159 
160 		regval = read_zsreg(channel, R1);
161 		readb(&channel->data);
162 		ZSDELAY();
163 
164 		if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
165 			writeb(ERR_RES, &channel->control);
166 			ZSDELAY();
167 			ZS_WSYNC(channel);
168 		}
169 	}
170 }
171 
172 /* This function must only be called when the TX is not busy.  The UART
173  * port lock must be held and local interrupts disabled.
174  */
__load_zsregs(struct zilog_channel __iomem * channel,unsigned char * regs)175 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
176 {
177 	int i;
178 	int escc;
179 	unsigned char r15;
180 
181 	/* Let pending transmits finish.  */
182 	for (i = 0; i < 1000; i++) {
183 		unsigned char stat = read_zsreg(channel, R1);
184 		if (stat & ALL_SNT)
185 			break;
186 		udelay(100);
187 	}
188 
189 	writeb(ERR_RES, &channel->control);
190 	ZSDELAY();
191 	ZS_WSYNC(channel);
192 
193 	sunzilog_clear_fifo(channel);
194 
195 	/* Disable all interrupts.  */
196 	write_zsreg(channel, R1,
197 		    regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
198 
199 	/* Set parity, sync config, stop bits, and clock divisor.  */
200 	write_zsreg(channel, R4, regs[R4]);
201 
202 	/* Set misc. TX/RX control bits.  */
203 	write_zsreg(channel, R10, regs[R10]);
204 
205 	/* Set TX/RX controls sans the enable bits.  */
206 	write_zsreg(channel, R3, regs[R3] & ~RxENAB);
207 	write_zsreg(channel, R5, regs[R5] & ~TxENAB);
208 
209 	/* Synchronous mode config.  */
210 	write_zsreg(channel, R6, regs[R6]);
211 	write_zsreg(channel, R7, regs[R7]);
212 
213 	/* Don't mess with the interrupt vector (R2, unused by us) and
214 	 * master interrupt control (R9).  We make sure this is setup
215 	 * properly at probe time then never touch it again.
216 	 */
217 
218 	/* Disable baud generator.  */
219 	write_zsreg(channel, R14, regs[R14] & ~BRENAB);
220 
221 	/* Clock mode control.  */
222 	write_zsreg(channel, R11, regs[R11]);
223 
224 	/* Lower and upper byte of baud rate generator divisor.  */
225 	write_zsreg(channel, R12, regs[R12]);
226 	write_zsreg(channel, R13, regs[R13]);
227 
228 	/* Now rewrite R14, with BRENAB (if set).  */
229 	write_zsreg(channel, R14, regs[R14]);
230 
231 	/* External status interrupt control.  */
232 	write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
233 
234 	/* ESCC Extension Register */
235 	r15 = read_zsreg(channel, R15);
236 	if (r15 & 0x01)	{
237 		write_zsreg(channel, R7,  regs[R7p]);
238 
239 		/* External status interrupt and FIFO control.  */
240 		write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
241 		escc = 1;
242 	} else {
243 		 /* Clear FIFO bit case it is an issue */
244 		regs[R15] &= ~FIFOEN;
245 		escc = 0;
246 	}
247 
248 	/* Reset external status interrupts.  */
249 	write_zsreg(channel, R0, RES_EXT_INT); /* First Latch  */
250 	write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
251 
252 	/* Rewrite R3/R5, this time without enables masked.  */
253 	write_zsreg(channel, R3, regs[R3]);
254 	write_zsreg(channel, R5, regs[R5]);
255 
256 	/* Rewrite R1, this time without IRQ enabled masked.  */
257 	write_zsreg(channel, R1, regs[R1]);
258 
259 	return escc;
260 }
261 
262 /* Reprogram the Zilog channel HW registers with the copies found in the
263  * software state struct.  If the transmitter is busy, we defer this update
264  * until the next TX complete interrupt.  Else, we do it right now.
265  *
266  * The UART port lock must be held and local interrupts disabled.
267  */
sunzilog_maybe_update_regs(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)268 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
269 				       struct zilog_channel __iomem *channel)
270 {
271 	if (!ZS_REGS_HELD(up)) {
272 		if (ZS_TX_ACTIVE(up)) {
273 			up->flags |= SUNZILOG_FLAG_REGS_HELD;
274 		} else {
275 			__load_zsregs(channel, up->curregs);
276 		}
277 	}
278 }
279 
sunzilog_change_mouse_baud(struct uart_sunzilog_port * up)280 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
281 {
282 	unsigned int cur_cflag = up->cflag;
283 	int brg, new_baud;
284 
285 	up->cflag &= ~CBAUD;
286 	up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
287 
288 	brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
289 	up->curregs[R12] = (brg & 0xff);
290 	up->curregs[R13] = (brg >> 8) & 0xff;
291 	sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
292 }
293 
sunzilog_kbdms_receive_chars(struct uart_sunzilog_port * up,unsigned char ch,int is_break)294 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
295 					 unsigned char ch, int is_break)
296 {
297 	if (ZS_IS_KEYB(up)) {
298 		/* Stop-A is handled by drivers/char/keyboard.c now. */
299 #ifdef CONFIG_SERIO
300 		if (up->serio_open)
301 			serio_interrupt(&up->serio, ch, 0);
302 #endif
303 	} else if (ZS_IS_MOUSE(up)) {
304 		int ret = suncore_mouse_baud_detection(ch, is_break);
305 
306 		switch (ret) {
307 		case 2:
308 			sunzilog_change_mouse_baud(up);
309 			fallthrough;
310 		case 1:
311 			break;
312 
313 		case 0:
314 #ifdef CONFIG_SERIO
315 			if (up->serio_open)
316 				serio_interrupt(&up->serio, ch, 0);
317 #endif
318 			break;
319 		}
320 	}
321 }
322 
323 static struct tty_port *
sunzilog_receive_chars(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)324 sunzilog_receive_chars(struct uart_sunzilog_port *up,
325 		       struct zilog_channel __iomem *channel)
326 {
327 	struct tty_port *port = NULL;
328 	unsigned char ch, r1, flag;
329 
330 	if (up->port.state != NULL)		/* Unopened serial console */
331 		port = &up->port.state->port;
332 
333 	for (;;) {
334 
335 		r1 = read_zsreg(channel, R1);
336 		if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
337 			writeb(ERR_RES, &channel->control);
338 			ZSDELAY();
339 			ZS_WSYNC(channel);
340 		}
341 
342 		ch = readb(&channel->control);
343 		ZSDELAY();
344 
345 		/* This funny hack depends upon BRK_ABRT not interfering
346 		 * with the other bits we care about in R1.
347 		 */
348 		if (ch & BRK_ABRT)
349 			r1 |= BRK_ABRT;
350 
351 		if (!(ch & Rx_CH_AV))
352 			break;
353 
354 		ch = readb(&channel->data);
355 		ZSDELAY();
356 
357 		ch &= up->parity_mask;
358 
359 		if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
360 			sunzilog_kbdms_receive_chars(up, ch, 0);
361 			continue;
362 		}
363 
364 		/* A real serial line, record the character and status.  */
365 		flag = TTY_NORMAL;
366 		up->port.icount.rx++;
367 		if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
368 			if (r1 & BRK_ABRT) {
369 				r1 &= ~(PAR_ERR | CRC_ERR);
370 				up->port.icount.brk++;
371 				if (uart_handle_break(&up->port))
372 					continue;
373 			}
374 			else if (r1 & PAR_ERR)
375 				up->port.icount.parity++;
376 			else if (r1 & CRC_ERR)
377 				up->port.icount.frame++;
378 			if (r1 & Rx_OVR)
379 				up->port.icount.overrun++;
380 			r1 &= up->port.read_status_mask;
381 			if (r1 & BRK_ABRT)
382 				flag = TTY_BREAK;
383 			else if (r1 & PAR_ERR)
384 				flag = TTY_PARITY;
385 			else if (r1 & CRC_ERR)
386 				flag = TTY_FRAME;
387 		}
388 		if (uart_handle_sysrq_char(&up->port, ch) || !port)
389 			continue;
390 
391 		if (up->port.ignore_status_mask == 0xff ||
392 		    (r1 & up->port.ignore_status_mask) == 0) {
393 		    	tty_insert_flip_char(port, ch, flag);
394 		}
395 		if (r1 & Rx_OVR)
396 			tty_insert_flip_char(port, 0, TTY_OVERRUN);
397 	}
398 
399 	return port;
400 }
401 
sunzilog_status_handle(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)402 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
403 				   struct zilog_channel __iomem *channel)
404 {
405 	unsigned char status;
406 
407 	status = readb(&channel->control);
408 	ZSDELAY();
409 
410 	writeb(RES_EXT_INT, &channel->control);
411 	ZSDELAY();
412 	ZS_WSYNC(channel);
413 
414 	if (status & BRK_ABRT) {
415 		if (ZS_IS_MOUSE(up))
416 			sunzilog_kbdms_receive_chars(up, 0, 1);
417 		if (ZS_IS_CONS(up)) {
418 			/* Wait for BREAK to deassert to avoid potentially
419 			 * confusing the PROM.
420 			 */
421 			while (1) {
422 				status = readb(&channel->control);
423 				ZSDELAY();
424 				if (!(status & BRK_ABRT))
425 					break;
426 			}
427 			sun_do_break();
428 			return;
429 		}
430 	}
431 
432 	if (ZS_WANTS_MODEM_STATUS(up)) {
433 		if (status & SYNC)
434 			up->port.icount.dsr++;
435 
436 		/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
437 		 * But it does not tell us which bit has changed, we have to keep
438 		 * track of this ourselves.
439 		 */
440 		if ((status ^ up->prev_status) ^ DCD)
441 			uart_handle_dcd_change(&up->port,
442 					       (status & DCD));
443 		if ((status ^ up->prev_status) ^ CTS)
444 			uart_handle_cts_change(&up->port,
445 					       (status & CTS));
446 
447 		wake_up_interruptible(&up->port.state->port.delta_msr_wait);
448 	}
449 
450 	up->prev_status = status;
451 }
452 
sunzilog_transmit_chars(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)453 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
454 				    struct zilog_channel __iomem *channel)
455 {
456 	struct circ_buf *xmit;
457 
458 	if (ZS_IS_CONS(up)) {
459 		unsigned char status = readb(&channel->control);
460 		ZSDELAY();
461 
462 		/* TX still busy?  Just wait for the next TX done interrupt.
463 		 *
464 		 * It can occur because of how we do serial console writes.  It would
465 		 * be nice to transmit console writes just like we normally would for
466 		 * a TTY line. (ie. buffered and TX interrupt driven).  That is not
467 		 * easy because console writes cannot sleep.  One solution might be
468 		 * to poll on enough port->xmit space becoming free.  -DaveM
469 		 */
470 		if (!(status & Tx_BUF_EMP))
471 			return;
472 	}
473 
474 	up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
475 
476 	if (ZS_REGS_HELD(up)) {
477 		__load_zsregs(channel, up->curregs);
478 		up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
479 	}
480 
481 	if (ZS_TX_STOPPED(up)) {
482 		up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
483 		goto ack_tx_int;
484 	}
485 
486 	if (up->port.x_char) {
487 		up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
488 		writeb(up->port.x_char, &channel->data);
489 		ZSDELAY();
490 		ZS_WSYNC(channel);
491 
492 		up->port.icount.tx++;
493 		up->port.x_char = 0;
494 		return;
495 	}
496 
497 	if (up->port.state == NULL)
498 		goto ack_tx_int;
499 	xmit = &up->port.state->xmit;
500 	if (uart_circ_empty(xmit))
501 		goto ack_tx_int;
502 
503 	if (uart_tx_stopped(&up->port))
504 		goto ack_tx_int;
505 
506 	up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
507 	writeb(xmit->buf[xmit->tail], &channel->data);
508 	ZSDELAY();
509 	ZS_WSYNC(channel);
510 
511 	uart_xmit_advance(&up->port, 1);
512 
513 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
514 		uart_write_wakeup(&up->port);
515 
516 	return;
517 
518 ack_tx_int:
519 	writeb(RES_Tx_P, &channel->control);
520 	ZSDELAY();
521 	ZS_WSYNC(channel);
522 }
523 
sunzilog_interrupt(int irq,void * dev_id)524 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
525 {
526 	struct uart_sunzilog_port *up = dev_id;
527 
528 	while (up) {
529 		struct zilog_channel __iomem *channel
530 			= ZILOG_CHANNEL_FROM_PORT(&up->port);
531 		struct tty_port *port;
532 		unsigned char r3;
533 
534 		spin_lock(&up->port.lock);
535 		r3 = read_zsreg(channel, R3);
536 
537 		/* Channel A */
538 		port = NULL;
539 		if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
540 			writeb(RES_H_IUS, &channel->control);
541 			ZSDELAY();
542 			ZS_WSYNC(channel);
543 
544 			if (r3 & CHARxIP)
545 				port = sunzilog_receive_chars(up, channel);
546 			if (r3 & CHAEXT)
547 				sunzilog_status_handle(up, channel);
548 			if (r3 & CHATxIP)
549 				sunzilog_transmit_chars(up, channel);
550 		}
551 		spin_unlock(&up->port.lock);
552 
553 		if (port)
554 			tty_flip_buffer_push(port);
555 
556 		/* Channel B */
557 		up = up->next;
558 		channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
559 
560 		spin_lock(&up->port.lock);
561 		port = NULL;
562 		if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
563 			writeb(RES_H_IUS, &channel->control);
564 			ZSDELAY();
565 			ZS_WSYNC(channel);
566 
567 			if (r3 & CHBRxIP)
568 				port = sunzilog_receive_chars(up, channel);
569 			if (r3 & CHBEXT)
570 				sunzilog_status_handle(up, channel);
571 			if (r3 & CHBTxIP)
572 				sunzilog_transmit_chars(up, channel);
573 		}
574 		spin_unlock(&up->port.lock);
575 
576 		if (port)
577 			tty_flip_buffer_push(port);
578 
579 		up = up->next;
580 	}
581 
582 	return IRQ_HANDLED;
583 }
584 
585 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
586  * port lock, it is acquired here.
587  */
sunzilog_read_channel_status(struct uart_port * port)588 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
589 {
590 	struct zilog_channel __iomem *channel;
591 	unsigned char status;
592 
593 	channel = ZILOG_CHANNEL_FROM_PORT(port);
594 	status = readb(&channel->control);
595 	ZSDELAY();
596 
597 	return status;
598 }
599 
600 /* The port lock is not held.  */
sunzilog_tx_empty(struct uart_port * port)601 static unsigned int sunzilog_tx_empty(struct uart_port *port)
602 {
603 	unsigned long flags;
604 	unsigned char status;
605 	unsigned int ret;
606 
607 	spin_lock_irqsave(&port->lock, flags);
608 
609 	status = sunzilog_read_channel_status(port);
610 
611 	spin_unlock_irqrestore(&port->lock, flags);
612 
613 	if (status & Tx_BUF_EMP)
614 		ret = TIOCSER_TEMT;
615 	else
616 		ret = 0;
617 
618 	return ret;
619 }
620 
621 /* The port lock is held and interrupts are disabled.  */
sunzilog_get_mctrl(struct uart_port * port)622 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
623 {
624 	unsigned char status;
625 	unsigned int ret;
626 
627 	status = sunzilog_read_channel_status(port);
628 
629 	ret = 0;
630 	if (status & DCD)
631 		ret |= TIOCM_CAR;
632 	if (status & SYNC)
633 		ret |= TIOCM_DSR;
634 	if (status & CTS)
635 		ret |= TIOCM_CTS;
636 
637 	return ret;
638 }
639 
640 /* The port lock is held and interrupts are disabled.  */
sunzilog_set_mctrl(struct uart_port * port,unsigned int mctrl)641 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
642 {
643 	struct uart_sunzilog_port *up =
644 		container_of(port, struct uart_sunzilog_port, port);
645 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
646 	unsigned char set_bits, clear_bits;
647 
648 	set_bits = clear_bits = 0;
649 
650 	if (mctrl & TIOCM_RTS)
651 		set_bits |= RTS;
652 	else
653 		clear_bits |= RTS;
654 	if (mctrl & TIOCM_DTR)
655 		set_bits |= DTR;
656 	else
657 		clear_bits |= DTR;
658 
659 	/* NOTE: Not subject to 'transmitter active' rule.  */
660 	up->curregs[R5] |= set_bits;
661 	up->curregs[R5] &= ~clear_bits;
662 	write_zsreg(channel, R5, up->curregs[R5]);
663 }
664 
665 /* The port lock is held and interrupts are disabled.  */
sunzilog_stop_tx(struct uart_port * port)666 static void sunzilog_stop_tx(struct uart_port *port)
667 {
668 	struct uart_sunzilog_port *up =
669 		container_of(port, struct uart_sunzilog_port, port);
670 
671 	up->flags |= SUNZILOG_FLAG_TX_STOPPED;
672 }
673 
674 /* The port lock is held and interrupts are disabled.  */
sunzilog_start_tx(struct uart_port * port)675 static void sunzilog_start_tx(struct uart_port *port)
676 {
677 	struct uart_sunzilog_port *up =
678 		container_of(port, struct uart_sunzilog_port, port);
679 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
680 	unsigned char status;
681 
682 	up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
683 	up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
684 
685 	status = readb(&channel->control);
686 	ZSDELAY();
687 
688 	/* TX busy?  Just wait for the TX done interrupt.  */
689 	if (!(status & Tx_BUF_EMP))
690 		return;
691 
692 	/* Send the first character to jump-start the TX done
693 	 * IRQ sending engine.
694 	 */
695 	if (port->x_char) {
696 		writeb(port->x_char, &channel->data);
697 		ZSDELAY();
698 		ZS_WSYNC(channel);
699 
700 		port->icount.tx++;
701 		port->x_char = 0;
702 	} else {
703 		struct circ_buf *xmit = &port->state->xmit;
704 
705 		if (uart_circ_empty(xmit))
706 			return;
707 		writeb(xmit->buf[xmit->tail], &channel->data);
708 		ZSDELAY();
709 		ZS_WSYNC(channel);
710 
711 		uart_xmit_advance(port, 1);
712 
713 		if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
714 			uart_write_wakeup(&up->port);
715 	}
716 }
717 
718 /* The port lock is held.  */
sunzilog_stop_rx(struct uart_port * port)719 static void sunzilog_stop_rx(struct uart_port *port)
720 {
721 	struct uart_sunzilog_port *up = UART_ZILOG(port);
722 	struct zilog_channel __iomem *channel;
723 
724 	if (ZS_IS_CONS(up))
725 		return;
726 
727 	channel = ZILOG_CHANNEL_FROM_PORT(port);
728 
729 	/* Disable all RX interrupts.  */
730 	up->curregs[R1] &= ~RxINT_MASK;
731 	sunzilog_maybe_update_regs(up, channel);
732 }
733 
734 /* The port lock is held.  */
sunzilog_enable_ms(struct uart_port * port)735 static void sunzilog_enable_ms(struct uart_port *port)
736 {
737 	struct uart_sunzilog_port *up =
738 		container_of(port, struct uart_sunzilog_port, port);
739 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
740 	unsigned char new_reg;
741 
742 	new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
743 	if (new_reg != up->curregs[R15]) {
744 		up->curregs[R15] = new_reg;
745 
746 		/* NOTE: Not subject to 'transmitter active' rule.  */
747 		write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
748 	}
749 }
750 
751 /* The port lock is not held.  */
sunzilog_break_ctl(struct uart_port * port,int break_state)752 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
753 {
754 	struct uart_sunzilog_port *up =
755 		container_of(port, struct uart_sunzilog_port, port);
756 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
757 	unsigned char set_bits, clear_bits, new_reg;
758 	unsigned long flags;
759 
760 	set_bits = clear_bits = 0;
761 
762 	if (break_state)
763 		set_bits |= SND_BRK;
764 	else
765 		clear_bits |= SND_BRK;
766 
767 	spin_lock_irqsave(&port->lock, flags);
768 
769 	new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
770 	if (new_reg != up->curregs[R5]) {
771 		up->curregs[R5] = new_reg;
772 
773 		/* NOTE: Not subject to 'transmitter active' rule.  */
774 		write_zsreg(channel, R5, up->curregs[R5]);
775 	}
776 
777 	spin_unlock_irqrestore(&port->lock, flags);
778 }
779 
__sunzilog_startup(struct uart_sunzilog_port * up)780 static void __sunzilog_startup(struct uart_sunzilog_port *up)
781 {
782 	struct zilog_channel __iomem *channel;
783 
784 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
785 	up->prev_status = readb(&channel->control);
786 
787 	/* Enable receiver and transmitter.  */
788 	up->curregs[R3] |= RxENAB;
789 	up->curregs[R5] |= TxENAB;
790 
791 	up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
792 	sunzilog_maybe_update_regs(up, channel);
793 }
794 
sunzilog_startup(struct uart_port * port)795 static int sunzilog_startup(struct uart_port *port)
796 {
797 	struct uart_sunzilog_port *up = UART_ZILOG(port);
798 	unsigned long flags;
799 
800 	if (ZS_IS_CONS(up))
801 		return 0;
802 
803 	spin_lock_irqsave(&port->lock, flags);
804 	__sunzilog_startup(up);
805 	spin_unlock_irqrestore(&port->lock, flags);
806 	return 0;
807 }
808 
809 /*
810  * The test for ZS_IS_CONS is explained by the following e-mail:
811  *****
812  * From: Russell King <rmk@arm.linux.org.uk>
813  * Date: Sun, 8 Dec 2002 10:18:38 +0000
814  *
815  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
816  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
817  * > and I noticed that something is not right with reference
818  * > counting in this case. It seems that when the console
819  * > is open by kernel initially, this is not accounted
820  * > as an open, and uart_startup is not called.
821  *
822  * That is correct.  We are unable to call uart_startup when the serial
823  * console is initialised because it may need to allocate memory (as
824  * request_irq does) and the memory allocators may not have been
825  * initialised.
826  *
827  * 1. initialise the port into a state where it can send characters in the
828  *    console write method.
829  *
830  * 2. don't do the actual hardware shutdown in your shutdown() method (but
831  *    do the normal software shutdown - ie, free irqs etc)
832  *****
833  */
sunzilog_shutdown(struct uart_port * port)834 static void sunzilog_shutdown(struct uart_port *port)
835 {
836 	struct uart_sunzilog_port *up = UART_ZILOG(port);
837 	struct zilog_channel __iomem *channel;
838 	unsigned long flags;
839 
840 	if (ZS_IS_CONS(up))
841 		return;
842 
843 	spin_lock_irqsave(&port->lock, flags);
844 
845 	channel = ZILOG_CHANNEL_FROM_PORT(port);
846 
847 	/* Disable receiver and transmitter.  */
848 	up->curregs[R3] &= ~RxENAB;
849 	up->curregs[R5] &= ~TxENAB;
850 
851 	/* Disable all interrupts and BRK assertion.  */
852 	up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
853 	up->curregs[R5] &= ~SND_BRK;
854 	sunzilog_maybe_update_regs(up, channel);
855 
856 	spin_unlock_irqrestore(&port->lock, flags);
857 }
858 
859 /* Shared by TTY driver and serial console setup.  The port lock is held
860  * and local interrupts are disabled.
861  */
862 static void
sunzilog_convert_to_zs(struct uart_sunzilog_port * up,unsigned int cflag,unsigned int iflag,int brg)863 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
864 		       unsigned int iflag, int brg)
865 {
866 
867 	up->curregs[R10] = NRZ;
868 	up->curregs[R11] = TCBR | RCBR;
869 
870 	/* Program BAUD and clock source. */
871 	up->curregs[R4] &= ~XCLK_MASK;
872 	up->curregs[R4] |= X16CLK;
873 	up->curregs[R12] = brg & 0xff;
874 	up->curregs[R13] = (brg >> 8) & 0xff;
875 	up->curregs[R14] = BRSRC | BRENAB;
876 
877 	/* Character size, stop bits, and parity. */
878 	up->curregs[R3] &= ~RxN_MASK;
879 	up->curregs[R5] &= ~TxN_MASK;
880 	switch (cflag & CSIZE) {
881 	case CS5:
882 		up->curregs[R3] |= Rx5;
883 		up->curregs[R5] |= Tx5;
884 		up->parity_mask = 0x1f;
885 		break;
886 	case CS6:
887 		up->curregs[R3] |= Rx6;
888 		up->curregs[R5] |= Tx6;
889 		up->parity_mask = 0x3f;
890 		break;
891 	case CS7:
892 		up->curregs[R3] |= Rx7;
893 		up->curregs[R5] |= Tx7;
894 		up->parity_mask = 0x7f;
895 		break;
896 	case CS8:
897 	default:
898 		up->curregs[R3] |= Rx8;
899 		up->curregs[R5] |= Tx8;
900 		up->parity_mask = 0xff;
901 		break;
902 	}
903 	up->curregs[R4] &= ~0x0c;
904 	if (cflag & CSTOPB)
905 		up->curregs[R4] |= SB2;
906 	else
907 		up->curregs[R4] |= SB1;
908 	if (cflag & PARENB)
909 		up->curregs[R4] |= PAR_ENAB;
910 	else
911 		up->curregs[R4] &= ~PAR_ENAB;
912 	if (!(cflag & PARODD))
913 		up->curregs[R4] |= PAR_EVEN;
914 	else
915 		up->curregs[R4] &= ~PAR_EVEN;
916 
917 	up->port.read_status_mask = Rx_OVR;
918 	if (iflag & INPCK)
919 		up->port.read_status_mask |= CRC_ERR | PAR_ERR;
920 	if (iflag & (IGNBRK | BRKINT | PARMRK))
921 		up->port.read_status_mask |= BRK_ABRT;
922 
923 	up->port.ignore_status_mask = 0;
924 	if (iflag & IGNPAR)
925 		up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
926 	if (iflag & IGNBRK) {
927 		up->port.ignore_status_mask |= BRK_ABRT;
928 		if (iflag & IGNPAR)
929 			up->port.ignore_status_mask |= Rx_OVR;
930 	}
931 
932 	if ((cflag & CREAD) == 0)
933 		up->port.ignore_status_mask = 0xff;
934 }
935 
936 /* The port lock is not held.  */
937 static void
sunzilog_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)938 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
939 		     const struct ktermios *old)
940 {
941 	struct uart_sunzilog_port *up =
942 		container_of(port, struct uart_sunzilog_port, port);
943 	unsigned long flags;
944 	int baud, brg;
945 
946 	baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
947 
948 	spin_lock_irqsave(&up->port.lock, flags);
949 
950 	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
951 
952 	sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
953 
954 	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
955 		up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
956 	else
957 		up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
958 
959 	up->cflag = termios->c_cflag;
960 
961 	sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
962 
963 	uart_update_timeout(port, termios->c_cflag, baud);
964 
965 	spin_unlock_irqrestore(&up->port.lock, flags);
966 }
967 
sunzilog_type(struct uart_port * port)968 static const char *sunzilog_type(struct uart_port *port)
969 {
970 	struct uart_sunzilog_port *up = UART_ZILOG(port);
971 
972 	return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
973 }
974 
975 /* We do not request/release mappings of the registers here, this
976  * happens at early serial probe time.
977  */
sunzilog_release_port(struct uart_port * port)978 static void sunzilog_release_port(struct uart_port *port)
979 {
980 }
981 
sunzilog_request_port(struct uart_port * port)982 static int sunzilog_request_port(struct uart_port *port)
983 {
984 	return 0;
985 }
986 
987 /* These do not need to do anything interesting either.  */
sunzilog_config_port(struct uart_port * port,int flags)988 static void sunzilog_config_port(struct uart_port *port, int flags)
989 {
990 }
991 
992 /* We do not support letting the user mess with the divisor, IRQ, etc. */
sunzilog_verify_port(struct uart_port * port,struct serial_struct * ser)993 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
994 {
995 	return -EINVAL;
996 }
997 
998 #ifdef CONFIG_CONSOLE_POLL
sunzilog_get_poll_char(struct uart_port * port)999 static int sunzilog_get_poll_char(struct uart_port *port)
1000 {
1001 	unsigned char ch, r1;
1002 	struct uart_sunzilog_port *up =
1003 		container_of(port, struct uart_sunzilog_port, port);
1004 	struct zilog_channel __iomem *channel
1005 		= ZILOG_CHANNEL_FROM_PORT(&up->port);
1006 
1007 
1008 	r1 = read_zsreg(channel, R1);
1009 	if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1010 		writeb(ERR_RES, &channel->control);
1011 		ZSDELAY();
1012 		ZS_WSYNC(channel);
1013 	}
1014 
1015 	ch = readb(&channel->control);
1016 	ZSDELAY();
1017 
1018 	/* This funny hack depends upon BRK_ABRT not interfering
1019 	 * with the other bits we care about in R1.
1020 	 */
1021 	if (ch & BRK_ABRT)
1022 		r1 |= BRK_ABRT;
1023 
1024 	if (!(ch & Rx_CH_AV))
1025 		return NO_POLL_CHAR;
1026 
1027 	ch = readb(&channel->data);
1028 	ZSDELAY();
1029 
1030 	ch &= up->parity_mask;
1031 	return ch;
1032 }
1033 
sunzilog_put_poll_char(struct uart_port * port,unsigned char ch)1034 static void sunzilog_put_poll_char(struct uart_port *port,
1035 			unsigned char ch)
1036 {
1037 	struct uart_sunzilog_port *up =
1038 		container_of(port, struct uart_sunzilog_port, port);
1039 
1040 	sunzilog_putchar(&up->port, ch);
1041 }
1042 #endif /* CONFIG_CONSOLE_POLL */
1043 
1044 static const struct uart_ops sunzilog_pops = {
1045 	.tx_empty	=	sunzilog_tx_empty,
1046 	.set_mctrl	=	sunzilog_set_mctrl,
1047 	.get_mctrl	=	sunzilog_get_mctrl,
1048 	.stop_tx	=	sunzilog_stop_tx,
1049 	.start_tx	=	sunzilog_start_tx,
1050 	.stop_rx	=	sunzilog_stop_rx,
1051 	.enable_ms	=	sunzilog_enable_ms,
1052 	.break_ctl	=	sunzilog_break_ctl,
1053 	.startup	=	sunzilog_startup,
1054 	.shutdown	=	sunzilog_shutdown,
1055 	.set_termios	=	sunzilog_set_termios,
1056 	.type		=	sunzilog_type,
1057 	.release_port	=	sunzilog_release_port,
1058 	.request_port	=	sunzilog_request_port,
1059 	.config_port	=	sunzilog_config_port,
1060 	.verify_port	=	sunzilog_verify_port,
1061 #ifdef CONFIG_CONSOLE_POLL
1062 	.poll_get_char	=	sunzilog_get_poll_char,
1063 	.poll_put_char	=	sunzilog_put_poll_char,
1064 #endif
1065 };
1066 
1067 static int uart_chip_count;
1068 static struct uart_sunzilog_port *sunzilog_port_table;
1069 static struct zilog_layout __iomem **sunzilog_chip_regs;
1070 
1071 static struct uart_sunzilog_port *sunzilog_irq_chain;
1072 
1073 static struct uart_driver sunzilog_reg = {
1074 	.owner		=	THIS_MODULE,
1075 	.driver_name	=	"sunzilog",
1076 	.dev_name	=	"ttyS",
1077 	.major		=	TTY_MAJOR,
1078 };
1079 
sunzilog_alloc_tables(int num_sunzilog)1080 static int __init sunzilog_alloc_tables(int num_sunzilog)
1081 {
1082 	struct uart_sunzilog_port *up;
1083 	unsigned long size;
1084 	int num_channels = num_sunzilog * 2;
1085 	int i;
1086 
1087 	size = num_channels * sizeof(struct uart_sunzilog_port);
1088 	sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1089 	if (!sunzilog_port_table)
1090 		return -ENOMEM;
1091 
1092 	for (i = 0; i < num_channels; i++) {
1093 		up = &sunzilog_port_table[i];
1094 
1095 		spin_lock_init(&up->port.lock);
1096 
1097 		if (i == 0)
1098 			sunzilog_irq_chain = up;
1099 
1100 		if (i < num_channels - 1)
1101 			up->next = up + 1;
1102 		else
1103 			up->next = NULL;
1104 	}
1105 
1106 	size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1107 	sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1108 	if (!sunzilog_chip_regs) {
1109 		kfree(sunzilog_port_table);
1110 		sunzilog_irq_chain = NULL;
1111 		return -ENOMEM;
1112 	}
1113 
1114 	return 0;
1115 }
1116 
sunzilog_free_tables(void)1117 static void sunzilog_free_tables(void)
1118 {
1119 	kfree(sunzilog_port_table);
1120 	sunzilog_irq_chain = NULL;
1121 	kfree(sunzilog_chip_regs);
1122 }
1123 
1124 #define ZS_PUT_CHAR_MAX_DELAY	2000	/* 10 ms */
1125 
sunzilog_putchar(struct uart_port * port,unsigned char ch)1126 static void __maybe_unused sunzilog_putchar(struct uart_port *port, unsigned char ch)
1127 {
1128 	struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1129 	int loops = ZS_PUT_CHAR_MAX_DELAY;
1130 
1131 	/* This is a timed polling loop so do not switch the explicit
1132 	 * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1133 	 */
1134 	do {
1135 		unsigned char val = readb(&channel->control);
1136 		if (val & Tx_BUF_EMP) {
1137 			ZSDELAY();
1138 			break;
1139 		}
1140 		udelay(5);
1141 	} while (--loops);
1142 
1143 	writeb(ch, &channel->data);
1144 	ZSDELAY();
1145 	ZS_WSYNC(channel);
1146 }
1147 
1148 #ifdef CONFIG_SERIO
1149 
1150 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1151 
sunzilog_serio_write(struct serio * serio,unsigned char ch)1152 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1153 {
1154 	struct uart_sunzilog_port *up = serio->port_data;
1155 	unsigned long flags;
1156 
1157 	spin_lock_irqsave(&sunzilog_serio_lock, flags);
1158 
1159 	sunzilog_putchar(&up->port, ch);
1160 
1161 	spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1162 
1163 	return 0;
1164 }
1165 
sunzilog_serio_open(struct serio * serio)1166 static int sunzilog_serio_open(struct serio *serio)
1167 {
1168 	struct uart_sunzilog_port *up = serio->port_data;
1169 	unsigned long flags;
1170 	int ret;
1171 
1172 	spin_lock_irqsave(&sunzilog_serio_lock, flags);
1173 	if (!up->serio_open) {
1174 		up->serio_open = 1;
1175 		ret = 0;
1176 	} else
1177 		ret = -EBUSY;
1178 	spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1179 
1180 	return ret;
1181 }
1182 
sunzilog_serio_close(struct serio * serio)1183 static void sunzilog_serio_close(struct serio *serio)
1184 {
1185 	struct uart_sunzilog_port *up = serio->port_data;
1186 	unsigned long flags;
1187 
1188 	spin_lock_irqsave(&sunzilog_serio_lock, flags);
1189 	up->serio_open = 0;
1190 	spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1191 }
1192 
1193 #endif /* CONFIG_SERIO */
1194 
1195 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1196 static void
sunzilog_console_write(struct console * con,const char * s,unsigned int count)1197 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1198 {
1199 	struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1200 	unsigned long flags;
1201 	int locked = 1;
1202 
1203 	if (up->port.sysrq || oops_in_progress)
1204 		locked = spin_trylock_irqsave(&up->port.lock, flags);
1205 	else
1206 		spin_lock_irqsave(&up->port.lock, flags);
1207 
1208 	uart_console_write(&up->port, s, count, sunzilog_putchar);
1209 	udelay(2);
1210 
1211 	if (locked)
1212 		spin_unlock_irqrestore(&up->port.lock, flags);
1213 }
1214 
sunzilog_console_setup(struct console * con,char * options)1215 static int __init sunzilog_console_setup(struct console *con, char *options)
1216 {
1217 	struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1218 	unsigned long flags;
1219 	int baud, brg;
1220 
1221 	if (up->port.type != PORT_SUNZILOG)
1222 		return -EINVAL;
1223 
1224 	printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1225 	       (sunzilog_reg.minor - 64) + con->index, con->index);
1226 
1227 	/* Get firmware console settings.  */
1228 	sunserial_console_termios(con, up->port.dev->of_node);
1229 
1230 	/* Firmware console speed is limited to 150-->38400 baud so
1231 	 * this hackish cflag thing is OK.
1232 	 */
1233 	switch (con->cflag & CBAUD) {
1234 	case B150: baud = 150; break;
1235 	case B300: baud = 300; break;
1236 	case B600: baud = 600; break;
1237 	case B1200: baud = 1200; break;
1238 	case B2400: baud = 2400; break;
1239 	case B4800: baud = 4800; break;
1240 	default: case B9600: baud = 9600; break;
1241 	case B19200: baud = 19200; break;
1242 	case B38400: baud = 38400; break;
1243 	}
1244 
1245 	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1246 
1247 	spin_lock_irqsave(&up->port.lock, flags);
1248 
1249 	up->curregs[R15] |= BRKIE;
1250 	sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1251 
1252 	sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1253 	__sunzilog_startup(up);
1254 
1255 	spin_unlock_irqrestore(&up->port.lock, flags);
1256 
1257 	return 0;
1258 }
1259 
1260 static struct console sunzilog_console_ops = {
1261 	.name	=	"ttyS",
1262 	.write	=	sunzilog_console_write,
1263 	.device	=	uart_console_device,
1264 	.setup	=	sunzilog_console_setup,
1265 	.flags	=	CON_PRINTBUFFER,
1266 	.index	=	-1,
1267 	.data   =	&sunzilog_reg,
1268 };
1269 
SUNZILOG_CONSOLE(void)1270 static inline struct console *SUNZILOG_CONSOLE(void)
1271 {
1272 	return &sunzilog_console_ops;
1273 }
1274 
1275 #else
1276 #define SUNZILOG_CONSOLE()	(NULL)
1277 #endif
1278 
sunzilog_init_kbdms(struct uart_sunzilog_port * up)1279 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1280 {
1281 	int baud, brg;
1282 
1283 	if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1284 		up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1285 		baud = 1200;
1286 	} else {
1287 		up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1288 		baud = 4800;
1289 	}
1290 
1291 	up->curregs[R15] |= BRKIE;
1292 	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1293 	sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1294 	sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1295 	__sunzilog_startup(up);
1296 }
1297 
1298 #ifdef CONFIG_SERIO
sunzilog_register_serio(struct uart_sunzilog_port * up)1299 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1300 {
1301 	struct serio *serio = &up->serio;
1302 
1303 	serio->port_data = up;
1304 
1305 	serio->id.type = SERIO_RS232;
1306 	if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1307 		serio->id.proto = SERIO_SUNKBD;
1308 		strscpy(serio->name, "zskbd", sizeof(serio->name));
1309 	} else {
1310 		serio->id.proto = SERIO_SUN;
1311 		serio->id.extra = 1;
1312 		strscpy(serio->name, "zsms", sizeof(serio->name));
1313 	}
1314 	strscpy(serio->phys,
1315 		((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1316 		 "zs/serio0" : "zs/serio1"),
1317 		sizeof(serio->phys));
1318 
1319 	serio->write = sunzilog_serio_write;
1320 	serio->open = sunzilog_serio_open;
1321 	serio->close = sunzilog_serio_close;
1322 	serio->dev.parent = up->port.dev;
1323 
1324 	serio_register_port(serio);
1325 }
1326 #endif
1327 
sunzilog_init_hw(struct uart_sunzilog_port * up)1328 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1329 {
1330 	struct zilog_channel __iomem *channel;
1331 	unsigned long flags;
1332 	int baud, brg;
1333 
1334 	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1335 
1336 	spin_lock_irqsave(&up->port.lock, flags);
1337 	if (ZS_IS_CHANNEL_A(up)) {
1338 		write_zsreg(channel, R9, FHWRES);
1339 		ZSDELAY_LONG();
1340 		(void) read_zsreg(channel, R0);
1341 	}
1342 
1343 	if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1344 			 SUNZILOG_FLAG_CONS_MOUSE)) {
1345 		up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1346 		up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1347 		up->curregs[R3] = RxENAB | Rx8;
1348 		up->curregs[R5] = TxENAB | Tx8;
1349 		up->curregs[R6] = 0x00; /* SDLC Address */
1350 		up->curregs[R7] = 0x7E; /* SDLC Flag    */
1351 		up->curregs[R9] = NV;
1352 		up->curregs[R7p] = 0x00;
1353 		sunzilog_init_kbdms(up);
1354 		/* Only enable interrupts if an ISR handler available */
1355 		if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1356 			up->curregs[R9] |= MIE;
1357 		write_zsreg(channel, R9, up->curregs[R9]);
1358 	} else {
1359 		/* Normal serial TTY. */
1360 		up->parity_mask = 0xff;
1361 		up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1362 		up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1363 		up->curregs[R3] = RxENAB | Rx8;
1364 		up->curregs[R5] = TxENAB | Tx8;
1365 		up->curregs[R6] = 0x00; /* SDLC Address */
1366 		up->curregs[R7] = 0x7E; /* SDLC Flag    */
1367 		up->curregs[R9] = NV;
1368 		up->curregs[R10] = NRZ;
1369 		up->curregs[R11] = TCBR | RCBR;
1370 		baud = 9600;
1371 		brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1372 		up->curregs[R12] = (brg & 0xff);
1373 		up->curregs[R13] = (brg >> 8) & 0xff;
1374 		up->curregs[R14] = BRSRC | BRENAB;
1375 		up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1376 		up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1377 		if (__load_zsregs(channel, up->curregs)) {
1378 			up->flags |= SUNZILOG_FLAG_ESCC;
1379 		}
1380 		/* Only enable interrupts if an ISR handler available */
1381 		if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1382 			up->curregs[R9] |= MIE;
1383 		write_zsreg(channel, R9, up->curregs[R9]);
1384 	}
1385 
1386 	spin_unlock_irqrestore(&up->port.lock, flags);
1387 
1388 #ifdef CONFIG_SERIO
1389 	if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1390 			 SUNZILOG_FLAG_CONS_MOUSE))
1391 		sunzilog_register_serio(up);
1392 #endif
1393 }
1394 
1395 static int zilog_irq;
1396 
zs_probe(struct platform_device * op)1397 static int zs_probe(struct platform_device *op)
1398 {
1399 	static int kbm_inst, uart_inst;
1400 	int inst;
1401 	struct uart_sunzilog_port *up;
1402 	struct zilog_layout __iomem *rp;
1403 	int keyboard_mouse = 0;
1404 	int err;
1405 
1406 	if (of_property_present(op->dev.of_node, "keyboard"))
1407 		keyboard_mouse = 1;
1408 
1409 	/* uarts must come before keyboards/mice */
1410 	if (keyboard_mouse)
1411 		inst = uart_chip_count + kbm_inst;
1412 	else
1413 		inst = uart_inst;
1414 
1415 	sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1416 					      sizeof(struct zilog_layout),
1417 					      "zs");
1418 	if (!sunzilog_chip_regs[inst])
1419 		return -ENOMEM;
1420 
1421 	rp = sunzilog_chip_regs[inst];
1422 
1423 	if (!zilog_irq)
1424 		zilog_irq = op->archdata.irqs[0];
1425 
1426 	up = &sunzilog_port_table[inst * 2];
1427 
1428 	/* Channel A */
1429 	up[0].port.mapbase = op->resource[0].start + 0x00;
1430 	up[0].port.membase = (void __iomem *) &rp->channelA;
1431 	up[0].port.iotype = UPIO_MEM;
1432 	up[0].port.irq = op->archdata.irqs[0];
1433 	up[0].port.uartclk = ZS_CLOCK;
1434 	up[0].port.fifosize = 1;
1435 	up[0].port.ops = &sunzilog_pops;
1436 	up[0].port.type = PORT_SUNZILOG;
1437 	up[0].port.flags = 0;
1438 	up[0].port.line = (inst * 2) + 0;
1439 	up[0].port.dev = &op->dev;
1440 	up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1441 	up[0].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1442 	if (keyboard_mouse)
1443 		up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1444 	sunzilog_init_hw(&up[0]);
1445 
1446 	/* Channel B */
1447 	up[1].port.mapbase = op->resource[0].start + 0x04;
1448 	up[1].port.membase = (void __iomem *) &rp->channelB;
1449 	up[1].port.iotype = UPIO_MEM;
1450 	up[1].port.irq = op->archdata.irqs[0];
1451 	up[1].port.uartclk = ZS_CLOCK;
1452 	up[1].port.fifosize = 1;
1453 	up[1].port.ops = &sunzilog_pops;
1454 	up[1].port.type = PORT_SUNZILOG;
1455 	up[1].port.flags = 0;
1456 	up[1].port.line = (inst * 2) + 1;
1457 	up[1].port.dev = &op->dev;
1458 	up[1].flags |= 0;
1459 	up[1].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1460 	if (keyboard_mouse)
1461 		up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1462 	sunzilog_init_hw(&up[1]);
1463 
1464 	if (!keyboard_mouse) {
1465 		if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1466 					    &sunzilog_reg, up[0].port.line,
1467 					    false))
1468 			up->flags |= SUNZILOG_FLAG_IS_CONS;
1469 		err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1470 		if (err) {
1471 			of_iounmap(&op->resource[0],
1472 				   rp, sizeof(struct zilog_layout));
1473 			return err;
1474 		}
1475 		if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1476 					    &sunzilog_reg, up[1].port.line,
1477 					    false))
1478 			up->flags |= SUNZILOG_FLAG_IS_CONS;
1479 		err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1480 		if (err) {
1481 			uart_remove_one_port(&sunzilog_reg, &up[0].port);
1482 			of_iounmap(&op->resource[0],
1483 				   rp, sizeof(struct zilog_layout));
1484 			return err;
1485 		}
1486 		uart_inst++;
1487 	} else {
1488 		printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1489 		       "is a %s\n",
1490 		       dev_name(&op->dev),
1491 		       (unsigned long long) up[0].port.mapbase,
1492 		       op->archdata.irqs[0], sunzilog_type(&up[0].port));
1493 		printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1494 		       "is a %s\n",
1495 		       dev_name(&op->dev),
1496 		       (unsigned long long) up[1].port.mapbase,
1497 		       op->archdata.irqs[0], sunzilog_type(&up[1].port));
1498 		kbm_inst++;
1499 	}
1500 
1501 	platform_set_drvdata(op, &up[0]);
1502 
1503 	return 0;
1504 }
1505 
zs_remove_one(struct uart_sunzilog_port * up)1506 static void zs_remove_one(struct uart_sunzilog_port *up)
1507 {
1508 	if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1509 #ifdef CONFIG_SERIO
1510 		serio_unregister_port(&up->serio);
1511 #endif
1512 	} else
1513 		uart_remove_one_port(&sunzilog_reg, &up->port);
1514 }
1515 
zs_remove(struct platform_device * op)1516 static int zs_remove(struct platform_device *op)
1517 {
1518 	struct uart_sunzilog_port *up = platform_get_drvdata(op);
1519 	struct zilog_layout __iomem *regs;
1520 
1521 	zs_remove_one(&up[0]);
1522 	zs_remove_one(&up[1]);
1523 
1524 	regs = sunzilog_chip_regs[up[0].port.line / 2];
1525 	of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1526 
1527 	return 0;
1528 }
1529 
1530 static const struct of_device_id zs_match[] = {
1531 	{
1532 		.name = "zs",
1533 	},
1534 	{},
1535 };
1536 MODULE_DEVICE_TABLE(of, zs_match);
1537 
1538 static struct platform_driver zs_driver = {
1539 	.driver = {
1540 		.name = "zs",
1541 		.of_match_table = zs_match,
1542 	},
1543 	.probe		= zs_probe,
1544 	.remove		= zs_remove,
1545 };
1546 
sunzilog_init(void)1547 static int __init sunzilog_init(void)
1548 {
1549 	struct device_node *dp;
1550 	int err;
1551 	int num_keybms = 0;
1552 	int num_sunzilog = 0;
1553 
1554 	for_each_node_by_name(dp, "zs") {
1555 		num_sunzilog++;
1556 		if (of_property_present(dp, "keyboard"))
1557 			num_keybms++;
1558 	}
1559 
1560 	if (num_sunzilog) {
1561 		err = sunzilog_alloc_tables(num_sunzilog);
1562 		if (err)
1563 			goto out;
1564 
1565 		uart_chip_count = num_sunzilog - num_keybms;
1566 
1567 		err = sunserial_register_minors(&sunzilog_reg,
1568 						uart_chip_count * 2);
1569 		if (err)
1570 			goto out_free_tables;
1571 	}
1572 
1573 	err = platform_driver_register(&zs_driver);
1574 	if (err)
1575 		goto out_unregister_uart;
1576 
1577 	if (zilog_irq) {
1578 		struct uart_sunzilog_port *up = sunzilog_irq_chain;
1579 		err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1580 				  "zs", sunzilog_irq_chain);
1581 		if (err)
1582 			goto out_unregister_driver;
1583 
1584 		/* Enable Interrupts */
1585 		while (up) {
1586 			struct zilog_channel __iomem *channel;
1587 
1588 			/* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1589 			channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1590 			up->flags       |= SUNZILOG_FLAG_ISR_HANDLER;
1591 			up->curregs[R9] |= MIE;
1592 			write_zsreg(channel, R9, up->curregs[R9]);
1593 			up = up->next;
1594 		}
1595 	}
1596 
1597 out:
1598 	return err;
1599 
1600 out_unregister_driver:
1601 	platform_driver_unregister(&zs_driver);
1602 
1603 out_unregister_uart:
1604 	if (num_sunzilog) {
1605 		sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1606 		sunzilog_reg.cons = NULL;
1607 	}
1608 
1609 out_free_tables:
1610 	sunzilog_free_tables();
1611 	goto out;
1612 }
1613 
sunzilog_exit(void)1614 static void __exit sunzilog_exit(void)
1615 {
1616 	platform_driver_unregister(&zs_driver);
1617 
1618 	if (zilog_irq) {
1619 		struct uart_sunzilog_port *up = sunzilog_irq_chain;
1620 
1621 		/* Disable Interrupts */
1622 		while (up) {
1623 			struct zilog_channel __iomem *channel;
1624 
1625 			/* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1626 			channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1627 			up->flags       &= ~SUNZILOG_FLAG_ISR_HANDLER;
1628 			up->curregs[R9] &= ~MIE;
1629 			write_zsreg(channel, R9, up->curregs[R9]);
1630 			up = up->next;
1631 		}
1632 
1633 		free_irq(zilog_irq, sunzilog_irq_chain);
1634 		zilog_irq = 0;
1635 	}
1636 
1637 	if (sunzilog_reg.nr) {
1638 		sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1639 		sunzilog_free_tables();
1640 	}
1641 }
1642 
1643 module_init(sunzilog_init);
1644 module_exit(sunzilog_exit);
1645 
1646 MODULE_AUTHOR("David S. Miller");
1647 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1648 MODULE_VERSION("2.0");
1649 MODULE_LICENSE("GPL");
1650