1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
11 */
12
13 #include <common.h>
14 #include <dm.h>
15 #include <mmc.h>
16 #include <axp_pmic.h>
17 #include <generic-phy.h>
18 #include <phy-sun4i-usb.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/display.h>
22 #include <asm/arch/dram.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc.h>
25 #include <asm/arch/spl.h>
26 #ifndef CONFIG_ARM64
27 #include <asm/armv7.h>
28 #endif
29 #include <asm/gpio.h>
30 #include <asm/io.h>
31 #include <u-boot/crc.h>
32 #include <environment.h>
33 #include <linux/libfdt.h>
34 #include <nand.h>
35 #include <net.h>
36 #include <spl.h>
37 #include <sy8106a.h>
38 #include <asm/setup.h>
39
40 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
41 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
42 int soft_i2c_gpio_sda;
43 int soft_i2c_gpio_scl;
44
soft_i2c_board_init(void)45 static int soft_i2c_board_init(void)
46 {
47 int ret;
48
49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
50 if (soft_i2c_gpio_sda < 0) {
51 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
53 return soft_i2c_gpio_sda;
54 }
55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
56 if (ret) {
57 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
59 return ret;
60 }
61
62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
63 if (soft_i2c_gpio_scl < 0) {
64 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
66 return soft_i2c_gpio_scl;
67 }
68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
69 if (ret) {
70 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
72 return ret;
73 }
74
75 return 0;
76 }
77 #else
soft_i2c_board_init(void)78 static int soft_i2c_board_init(void) { return 0; }
79 #endif
80
81 DECLARE_GLOBAL_DATA_PTR;
82
i2c_init_board(void)83 void i2c_init_board(void)
84 {
85 #ifdef CONFIG_I2C0_ENABLE
86 #if defined(CONFIG_MACH_SUN4I) || \
87 defined(CONFIG_MACH_SUN5I) || \
88 defined(CONFIG_MACH_SUN7I) || \
89 defined(CONFIG_MACH_SUN8I_R40)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
92 clock_twi_onoff(0, 1);
93 #elif defined(CONFIG_MACH_SUN6I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
96 clock_twi_onoff(0, 1);
97 #elif defined(CONFIG_MACH_SUN8I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
100 clock_twi_onoff(0, 1);
101 #elif defined(CONFIG_MACH_SUN50I)
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
104 clock_twi_onoff(0, 1);
105 #endif
106 #endif
107
108 #ifdef CONFIG_I2C1_ENABLE
109 #if defined(CONFIG_MACH_SUN4I) || \
110 defined(CONFIG_MACH_SUN7I) || \
111 defined(CONFIG_MACH_SUN8I_R40)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
114 clock_twi_onoff(1, 1);
115 #elif defined(CONFIG_MACH_SUN5I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
118 clock_twi_onoff(1, 1);
119 #elif defined(CONFIG_MACH_SUN6I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
122 clock_twi_onoff(1, 1);
123 #elif defined(CONFIG_MACH_SUN8I)
124 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
125 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
126 clock_twi_onoff(1, 1);
127 #elif defined(CONFIG_MACH_SUN50I)
128 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
129 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
130 clock_twi_onoff(1, 1);
131 #endif
132 #endif
133
134 #ifdef CONFIG_I2C2_ENABLE
135 #if defined(CONFIG_MACH_SUN4I) || \
136 defined(CONFIG_MACH_SUN7I) || \
137 defined(CONFIG_MACH_SUN8I_R40)
138 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
139 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
140 clock_twi_onoff(2, 1);
141 #elif defined(CONFIG_MACH_SUN5I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
143 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
144 clock_twi_onoff(2, 1);
145 #elif defined(CONFIG_MACH_SUN6I)
146 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
147 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
148 clock_twi_onoff(2, 1);
149 #elif defined(CONFIG_MACH_SUN8I)
150 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
151 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
152 clock_twi_onoff(2, 1);
153 #elif defined(CONFIG_MACH_SUN50I)
154 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
155 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
156 clock_twi_onoff(2, 1);
157 #endif
158 #endif
159
160 #ifdef CONFIG_I2C3_ENABLE
161 #if defined(CONFIG_MACH_SUN6I)
162 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
163 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
164 clock_twi_onoff(3, 1);
165 #elif defined(CONFIG_MACH_SUN7I) || \
166 defined(CONFIG_MACH_SUN8I_R40)
167 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
168 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
169 clock_twi_onoff(3, 1);
170 #endif
171 #endif
172
173 #ifdef CONFIG_I2C4_ENABLE
174 #if defined(CONFIG_MACH_SUN7I) || \
175 defined(CONFIG_MACH_SUN8I_R40)
176 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
177 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
178 clock_twi_onoff(4, 1);
179 #endif
180 #endif
181
182 #ifdef CONFIG_R_I2C_ENABLE
183 #ifdef CONFIG_MACH_SUN50I
184 clock_twi_onoff(5, 1);
185 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
186 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
187 #else
188 clock_twi_onoff(5, 1);
189 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
190 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
191 #endif
192 #endif
193 }
194
195 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
env_get_location(enum env_operation op,int prio)196 enum env_location env_get_location(enum env_operation op, int prio)
197 {
198 switch (prio) {
199 case 0:
200 return ENVL_FAT;
201
202 case 1:
203 return ENVL_MMC;
204
205 default:
206 return ENVL_UNKNOWN;
207 }
208 }
209 #endif
210
211 #ifdef CONFIG_DM_MMC
212 static void mmc_pinmux_setup(int sdc);
213 #endif
214
215 /* add board specific code here */
board_init(void)216 int board_init(void)
217 {
218 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
219
220 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
221
222 #ifndef CONFIG_ARM64
223 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
224 debug("id_pfr1: 0x%08x\n", id_pfr1);
225 /* Generic Timer Extension available? */
226 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
227 uint32_t freq;
228
229 debug("Setting CNTFRQ\n");
230
231 /*
232 * CNTFRQ is a secure register, so we will crash if we try to
233 * write this from the non-secure world (read is OK, though).
234 * In case some bootcode has already set the correct value,
235 * we avoid the risk of writing to it.
236 */
237 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
238 if (freq != COUNTER_FREQUENCY) {
239 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
240 freq, COUNTER_FREQUENCY);
241 #ifdef CONFIG_NON_SECURE
242 printf("arch timer frequency is wrong, but cannot adjust it\n");
243 #else
244 asm volatile("mcr p15, 0, %0, c14, c0, 0"
245 : : "r"(COUNTER_FREQUENCY));
246 #endif
247 }
248 }
249 #endif /* !CONFIG_ARM64 */
250
251 ret = axp_gpio_init();
252 if (ret)
253 return ret;
254
255 #ifdef CONFIG_SATAPWR
256 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
257 gpio_request(satapwr_pin, "satapwr");
258 gpio_direction_output(satapwr_pin, 1);
259 /* Give attached sata device time to power-up to avoid link timeouts */
260 mdelay(500);
261 #endif
262 #ifdef CONFIG_MACPWR
263 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
264 gpio_request(macpwr_pin, "macpwr");
265 gpio_direction_output(macpwr_pin, 1);
266 #endif
267
268 #ifdef CONFIG_DM_I2C
269 /*
270 * Temporary workaround for enabling I2C clocks until proper sunxi DM
271 * clk, reset and pinctrl drivers land.
272 */
273 i2c_init_board();
274 #endif
275
276 #ifdef CONFIG_DM_MMC
277 /*
278 * Temporary workaround for enabling MMC clocks until a sunxi DM
279 * pinctrl driver lands.
280 */
281 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
282 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
283 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
284 #endif
285 #endif /* CONFIG_DM_MMC */
286
287 /* Uses dm gpio code so do this here and not in i2c_init_board() */
288 return soft_i2c_board_init();
289 }
290
291 /*
292 * On older SoCs the SPL is actually at address zero, so using NULL as
293 * an error value does not work.
294 */
295 #define INVALID_SPL_HEADER ((void *)~0UL)
296
get_spl_header(uint8_t req_version)297 static struct boot_file_head * get_spl_header(uint8_t req_version)
298 {
299 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
300 uint8_t spl_header_version = spl->spl_signature[3];
301
302 /* Is there really the SPL header (still) there? */
303 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
304 return INVALID_SPL_HEADER;
305
306 if (spl_header_version < req_version) {
307 printf("sunxi SPL version mismatch: expected %u, got %u\n",
308 req_version, spl_header_version);
309 return INVALID_SPL_HEADER;
310 }
311
312 return spl;
313 }
314
dram_init(void)315 int dram_init(void)
316 {
317 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
318
319 if (spl == INVALID_SPL_HEADER)
320 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
321 PHYS_SDRAM_0_SIZE);
322 else
323 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
324
325 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
326 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
327
328 return 0;
329 }
330
331 #if defined(CONFIG_NAND_SUNXI)
nand_pinmux_setup(void)332 static void nand_pinmux_setup(void)
333 {
334 unsigned int pin;
335
336 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
337 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
338
339 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
340 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
341 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
342 #endif
343 /* sun4i / sun7i do have a PC23, but it is not used for nand,
344 * only sun7i has a PC24 */
345 #ifdef CONFIG_MACH_SUN7I
346 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
347 #endif
348 }
349
nand_clock_setup(void)350 static void nand_clock_setup(void)
351 {
352 struct sunxi_ccm_reg *const ccm =
353 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
354
355 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
356 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
357 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
358 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
359 #endif
360 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
361 }
362
board_nand_init(void)363 void board_nand_init(void)
364 {
365 nand_pinmux_setup();
366 nand_clock_setup();
367 #ifndef CONFIG_SPL_BUILD
368 sunxi_nand_init();
369 #endif
370 }
371 #endif
372
373 #ifdef CONFIG_MMC
mmc_pinmux_setup(int sdc)374 static void mmc_pinmux_setup(int sdc)
375 {
376 unsigned int pin;
377 __maybe_unused int pins;
378
379 switch (sdc) {
380 case 0:
381 /* SDC0: PF0-PF5 */
382 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
383 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
384 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
385 sunxi_gpio_set_drv(pin, 2);
386 }
387 break;
388
389 case 1:
390 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
391
392 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
393 defined(CONFIG_MACH_SUN8I_R40)
394 if (pins == SUNXI_GPIO_H) {
395 /* SDC1: PH22-PH-27 */
396 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
397 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
398 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
399 sunxi_gpio_set_drv(pin, 2);
400 }
401 } else {
402 /* SDC1: PG0-PG5 */
403 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
404 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
405 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
406 sunxi_gpio_set_drv(pin, 2);
407 }
408 }
409 #elif defined(CONFIG_MACH_SUN5I)
410 /* SDC1: PG3-PG8 */
411 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
412 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
413 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
414 sunxi_gpio_set_drv(pin, 2);
415 }
416 #elif defined(CONFIG_MACH_SUN6I)
417 /* SDC1: PG0-PG5 */
418 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
419 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
420 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
421 sunxi_gpio_set_drv(pin, 2);
422 }
423 #elif defined(CONFIG_MACH_SUN8I)
424 if (pins == SUNXI_GPIO_D) {
425 /* SDC1: PD2-PD7 */
426 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
427 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
428 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
429 sunxi_gpio_set_drv(pin, 2);
430 }
431 } else {
432 /* SDC1: PG0-PG5 */
433 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
434 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
435 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
436 sunxi_gpio_set_drv(pin, 2);
437 }
438 }
439 #endif
440 break;
441
442 case 2:
443 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
444
445 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
446 /* SDC2: PC6-PC11 */
447 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
448 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
449 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
450 sunxi_gpio_set_drv(pin, 2);
451 }
452 #elif defined(CONFIG_MACH_SUN5I)
453 if (pins == SUNXI_GPIO_E) {
454 /* SDC2: PE4-PE9 */
455 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
456 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
457 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
458 sunxi_gpio_set_drv(pin, 2);
459 }
460 } else {
461 /* SDC2: PC6-PC15 */
462 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
463 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
464 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(pin, 2);
466 }
467 }
468 #elif defined(CONFIG_MACH_SUN6I)
469 if (pins == SUNXI_GPIO_A) {
470 /* SDC2: PA9-PA14 */
471 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
472 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
473 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
474 sunxi_gpio_set_drv(pin, 2);
475 }
476 } else {
477 /* SDC2: PC6-PC15, PC24 */
478 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
479 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
480 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
481 sunxi_gpio_set_drv(pin, 2);
482 }
483
484 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
485 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
486 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
487 }
488 #elif defined(CONFIG_MACH_SUN8I_R40)
489 /* SDC2: PC6-PC15, PC24 */
490 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
491 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
492 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
493 sunxi_gpio_set_drv(pin, 2);
494 }
495
496 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
497 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
498 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
499 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
500 /* SDC2: PC5-PC6, PC8-PC16 */
501 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
502 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
503 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
504 sunxi_gpio_set_drv(pin, 2);
505 }
506
507 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
508 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
509 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
510 sunxi_gpio_set_drv(pin, 2);
511 }
512 #elif defined(CONFIG_MACH_SUN50I_H6)
513 /* SDC2: PC4-PC14 */
514 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
515 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
516 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
517 sunxi_gpio_set_drv(pin, 2);
518 }
519 #elif defined(CONFIG_MACH_SUN9I)
520 /* SDC2: PC6-PC16 */
521 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
522 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
523 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
524 sunxi_gpio_set_drv(pin, 2);
525 }
526 #endif
527 break;
528
529 case 3:
530 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
531
532 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
533 defined(CONFIG_MACH_SUN8I_R40)
534 /* SDC3: PI4-PI9 */
535 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
536 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
537 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
538 sunxi_gpio_set_drv(pin, 2);
539 }
540 #elif defined(CONFIG_MACH_SUN6I)
541 if (pins == SUNXI_GPIO_A) {
542 /* SDC3: PA9-PA14 */
543 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
544 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
545 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
546 sunxi_gpio_set_drv(pin, 2);
547 }
548 } else {
549 /* SDC3: PC6-PC15, PC24 */
550 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
551 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
552 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
553 sunxi_gpio_set_drv(pin, 2);
554 }
555
556 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
557 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
558 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
559 }
560 #endif
561 break;
562
563 default:
564 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
565 break;
566 }
567 }
568
board_mmc_init(bd_t * bis)569 int board_mmc_init(bd_t *bis)
570 {
571 __maybe_unused struct mmc *mmc0, *mmc1;
572
573 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
574 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
575 if (!mmc0)
576 return -1;
577
578 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
579 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
580 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
581 if (!mmc1)
582 return -1;
583 #endif
584
585 return 0;
586 }
587 #endif
588
589 #ifdef CONFIG_SPL_BUILD
590
sunxi_spl_store_dram_size(phys_addr_t dram_size)591 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
592 {
593 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
594
595 if (spl == INVALID_SPL_HEADER)
596 return;
597
598 /* Promote the header version for U-Boot proper, if needed. */
599 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
600 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
601
602 spl->dram_size = dram_size >> 20;
603 }
604
sunxi_board_init(void)605 void sunxi_board_init(void)
606 {
607 int power_failed = 0;
608
609 #ifdef CONFIG_SY8106A_POWER
610 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
611 #endif
612
613 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
614 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
615 defined CONFIG_AXP818_POWER
616 power_failed = axp_init();
617
618 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
619 defined CONFIG_AXP818_POWER
620 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
621 #endif
622 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
623 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
624 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
625 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
626 #endif
627 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
628 defined CONFIG_AXP818_POWER
629 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
630 #endif
631
632 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
633 defined CONFIG_AXP818_POWER
634 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
635 #endif
636 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
637 #if !defined(CONFIG_AXP152_POWER)
638 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
639 #endif
640 #ifdef CONFIG_AXP209_POWER
641 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
642 #endif
643
644 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
645 defined(CONFIG_AXP818_POWER)
646 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
647 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
648 #if !defined CONFIG_AXP809_POWER
649 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
650 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
651 #endif
652 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
653 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
654 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
655 #endif
656
657 #ifdef CONFIG_AXP818_POWER
658 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
659 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
660 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
661 #endif
662
663 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
664 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
665 #endif
666 #endif
667 printf("DRAM:");
668 gd->ram_size = sunxi_dram_init();
669 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
670 if (!gd->ram_size)
671 hang();
672
673 sunxi_spl_store_dram_size(gd->ram_size);
674
675 /*
676 * Only clock up the CPU to full speed if we are reasonably
677 * assured it's being powered with suitable core voltage
678 */
679 if (!power_failed)
680 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
681 else
682 printf("Failed to set core voltage! Can't set CPU frequency\n");
683 }
684 #endif
685
686 #ifdef CONFIG_USB_GADGET
g_dnl_board_usb_cable_connected(void)687 int g_dnl_board_usb_cable_connected(void)
688 {
689 struct udevice *dev;
690 struct phy phy;
691 int ret;
692
693 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
694 if (ret) {
695 pr_err("%s: Cannot find USB device\n", __func__);
696 return ret;
697 }
698
699 ret = generic_phy_get_by_name(dev, "usb", &phy);
700 if (ret) {
701 pr_err("failed to get %s USB PHY\n", dev->name);
702 return ret;
703 }
704
705 ret = generic_phy_init(&phy);
706 if (ret) {
707 pr_err("failed to init %s USB PHY\n", dev->name);
708 return ret;
709 }
710
711 ret = sun4i_usb_phy_vbus_detect(&phy);
712 if (ret == 1) {
713 pr_err("A charger is plugged into the OTG\n");
714 return -ENODEV;
715 }
716
717 return ret;
718 }
719 #endif
720
721 #ifdef CONFIG_SERIAL_TAG
get_board_serial(struct tag_serialnr * serialnr)722 void get_board_serial(struct tag_serialnr *serialnr)
723 {
724 char *serial_string;
725 unsigned long long serial;
726
727 serial_string = env_get("serial#");
728
729 if (serial_string) {
730 serial = simple_strtoull(serial_string, NULL, 16);
731
732 serialnr->high = (unsigned int) (serial >> 32);
733 serialnr->low = (unsigned int) (serial & 0xffffffff);
734 } else {
735 serialnr->high = 0;
736 serialnr->low = 0;
737 }
738 }
739 #endif
740
741 /*
742 * Check the SPL header for the "sunxi" variant. If found: parse values
743 * that might have been passed by the loader ("fel" utility), and update
744 * the environment accordingly.
745 */
parse_spl_header(const uint32_t spl_addr)746 static void parse_spl_header(const uint32_t spl_addr)
747 {
748 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
749
750 if (spl == INVALID_SPL_HEADER)
751 return;
752
753 if (!spl->fel_script_address)
754 return;
755
756 if (spl->fel_uEnv_length != 0) {
757 /*
758 * data is expected in uEnv.txt compatible format, so "env
759 * import -t" the string(s) at fel_script_address right away.
760 */
761 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
762 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
763 return;
764 }
765 /* otherwise assume .scr format (mkimage-type script) */
766 env_set_hex("fel_scriptaddr", spl->fel_script_address);
767 }
768
769 /*
770 * Note this function gets called multiple times.
771 * It must not make any changes to env variables which already exist.
772 */
setup_environment(const void * fdt)773 static void setup_environment(const void *fdt)
774 {
775 char serial_string[17] = { 0 };
776 unsigned int sid[4];
777 uint8_t mac_addr[6];
778 char ethaddr[16];
779 int i, ret;
780
781 ret = sunxi_get_sid(sid);
782 if (ret == 0 && sid[0] != 0) {
783 /*
784 * The single words 1 - 3 of the SID have quite a few bits
785 * which are the same on many models, so we take a crc32
786 * of all 3 words, to get a more unique value.
787 *
788 * Note we only do this on newer SoCs as we cannot change
789 * the algorithm on older SoCs since those have been using
790 * fixed mac-addresses based on only using word 3 for a
791 * long time and changing a fixed mac-address with an
792 * u-boot update is not good.
793 */
794 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
795 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
796 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
797 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
798 #endif
799
800 /* Ensure the NIC specific bytes of the mac are not all 0 */
801 if ((sid[3] & 0xffffff) == 0)
802 sid[3] |= 0x800000;
803
804 for (i = 0; i < 4; i++) {
805 sprintf(ethaddr, "ethernet%d", i);
806 if (!fdt_get_alias(fdt, ethaddr))
807 continue;
808
809 if (i == 0)
810 strcpy(ethaddr, "ethaddr");
811 else
812 sprintf(ethaddr, "eth%daddr", i);
813
814 if (env_get(ethaddr))
815 continue;
816
817 /* Non OUI / registered MAC address */
818 mac_addr[0] = (i << 4) | 0x02;
819 mac_addr[1] = (sid[0] >> 0) & 0xff;
820 mac_addr[2] = (sid[3] >> 24) & 0xff;
821 mac_addr[3] = (sid[3] >> 16) & 0xff;
822 mac_addr[4] = (sid[3] >> 8) & 0xff;
823 mac_addr[5] = (sid[3] >> 0) & 0xff;
824
825 eth_env_set_enetaddr(ethaddr, mac_addr);
826 }
827
828 if (!env_get("serial#")) {
829 snprintf(serial_string, sizeof(serial_string),
830 "%08x%08x", sid[0], sid[3]);
831
832 env_set("serial#", serial_string);
833 }
834 }
835 }
836
misc_init_r(void)837 int misc_init_r(void)
838 {
839 uint boot;
840
841 env_set("fel_booted", NULL);
842 env_set("fel_scriptaddr", NULL);
843 env_set("mmc_bootdev", NULL);
844
845 boot = sunxi_get_boot_device();
846 /* determine if we are running in FEL mode */
847 if (boot == BOOT_DEVICE_BOARD) {
848 env_set("fel_booted", "1");
849 parse_spl_header(SPL_ADDR);
850 /* or if we booted from MMC, and which one */
851 } else if (boot == BOOT_DEVICE_MMC1) {
852 env_set("mmc_bootdev", "0");
853 } else if (boot == BOOT_DEVICE_MMC2) {
854 env_set("mmc_bootdev", "1");
855 }
856
857 setup_environment(gd->fdt_blob);
858
859 #ifdef CONFIG_USB_ETHER
860 usb_ether_init();
861 #endif
862
863 return 0;
864 }
865
ft_board_setup(void * blob,bd_t * bd)866 int ft_board_setup(void *blob, bd_t *bd)
867 {
868 int __maybe_unused r;
869
870 /*
871 * Call setup_environment again in case the boot fdt has
872 * ethernet aliases the u-boot copy does not have.
873 */
874 setup_environment(blob);
875
876 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
877 r = sunxi_simplefb_setup(blob);
878 if (r)
879 return r;
880 #endif
881 return 0;
882 }
883
884 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)885 int board_fit_config_name_match(const char *name)
886 {
887 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
888 const char *cmp_str = (const char *)spl;
889
890 /* Check if there is a DT name stored in the SPL header and use that. */
891 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
892 cmp_str += spl->dt_name_offset;
893 } else {
894 #ifdef CONFIG_DEFAULT_DEVICE_TREE
895 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
896 #else
897 return 0;
898 #endif
899 };
900
901 #ifdef CONFIG_PINE64_DT_SELECTION
902 /* Differentiate the two Pine64 board DTs by their DRAM size. */
903 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
904 if ((gd->ram_size > 512 * 1024 * 1024))
905 return !strstr(name, "plus");
906 else
907 return !!strstr(name, "plus");
908 } else {
909 return strcmp(name, cmp_str);
910 }
911 #endif
912 return strcmp(name, cmp_str);
913 }
914 #endif
915