1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.io>
4  *
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 
12 #include "ccu_common.h"
13 #include "ccu_reset.h"
14 
15 #include "ccu_div.h"
16 #include "ccu_gate.h"
17 #include "ccu_mp.h"
18 #include "ccu_mult.h"
19 #include "ccu_nk.h"
20 #include "ccu_nkm.h"
21 #include "ccu_nkmp.h"
22 #include "ccu_nm.h"
23 #include "ccu_phase.h"
24 
25 #include "ccu-suniv-f1c100s.h"
26 
27 static struct ccu_nkmp pll_cpu_clk = {
28 	.enable = BIT(31),
29 	.lock	= BIT(28),
30 
31 	.n	= _SUNXI_CCU_MULT(8, 5),
32 	.k	= _SUNXI_CCU_MULT(4, 2),
33 	.m	= _SUNXI_CCU_DIV(0, 2),
34 	/* MAX is guessed by the BSP table */
35 	.p	= _SUNXI_CCU_DIV_MAX(16, 2, 4),
36 
37 	.common	= {
38 		.reg		= 0x000,
39 		.hw.init	= CLK_HW_INIT("pll-cpu", "osc24M",
40 					      &ccu_nkmp_ops,
41 					      CLK_SET_RATE_UNGATE),
42 	},
43 };
44 
45 /*
46  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
47  * the base (2x, 4x and 8x), and one variable divider (the one true
48  * pll audio).
49  *
50  * We don't have any need for the variable divider for now, so we just
51  * hardcode it to match with the clock names
52  */
53 #define SUNIV_PLL_AUDIO_REG	0x008
54 
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
56 				   "osc24M", 0x008,
57 				   8, 7,		/* N */
58 				   0, 5,		/* M */
59 				   BIT(31),		/* gate */
60 				   BIT(28),		/* lock */
61 				   CLK_SET_RATE_UNGATE);
62 
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
64 					"osc24M", 0x010,
65 					8, 7,		/* N */
66 					0, 4,		/* M */
67 					BIT(24),	/* frac enable */
68 					BIT(25),	/* frac select */
69 					270000000,	/* frac rate 0 */
70 					297000000,	/* frac rate 1 */
71 					BIT(31),	/* gate */
72 					BIT(28),	/* lock */
73 					CLK_SET_RATE_UNGATE);
74 
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
76 					"osc24M", 0x018,
77 					8, 7,		/* N */
78 					0, 4,		/* M */
79 					BIT(24),	/* frac enable */
80 					BIT(25),	/* frac select */
81 					270000000,	/* frac rate 0 */
82 					297000000,	/* frac rate 1 */
83 					BIT(31),	/* gate */
84 					BIT(28),	/* lock */
85 					CLK_SET_RATE_UNGATE);
86 
87 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
88 				    "osc24M", 0x020,
89 				    8, 5,		/* N */
90 				    4, 2,		/* K */
91 				    0, 2,		/* M */
92 				    BIT(31),		/* gate */
93 				    BIT(28),		/* lock */
94 				    CLK_IS_CRITICAL);
95 
96 static struct ccu_nk pll_periph_clk = {
97 	.enable		= BIT(31),
98 	.lock		= BIT(28),
99 	.k		= _SUNXI_CCU_MULT(4, 2),
100 	.n		= _SUNXI_CCU_MULT(8, 5),
101 	.common		= {
102 		.reg		= 0x028,
103 		.hw.init	= CLK_HW_INIT("pll-periph", "osc24M",
104 					      &ccu_nk_ops, 0),
105 	},
106 };
107 
108 static const char * const cpu_parents[] = { "osc32k", "osc24M",
109 					     "pll-cpu", "pll-cpu" };
110 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
111 		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
112 
113 static const char * const ahb_parents[] = { "osc32k", "osc24M",
114 					    "cpu", "pll-periph" };
115 static const struct ccu_mux_var_prediv ahb_predivs[] = {
116 	{ .index = 3, .shift = 6, .width = 2 },
117 };
118 static struct ccu_div ahb_clk = {
119 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
120 
121 	.mux		= {
122 		.shift	= 12,
123 		.width	= 2,
124 
125 		.var_predivs	= ahb_predivs,
126 		.n_var_predivs	= ARRAY_SIZE(ahb_predivs),
127 	},
128 
129 	.common		= {
130 		.reg		= 0x054,
131 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
132 		.hw.init	= CLK_HW_INIT_PARENTS("ahb",
133 						      ahb_parents,
134 						      &ccu_div_ops,
135 						      0),
136 	},
137 };
138 
139 static struct clk_div_table apb_div_table[] = {
140 	{ .val = 0, .div = 2 },
141 	{ .val = 1, .div = 2 },
142 	{ .val = 2, .div = 4 },
143 	{ .val = 3, .div = 8 },
144 	{ /* Sentinel */ },
145 };
146 static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
147 			   0x054, 8, 2, apb_div_table, 0);
148 
149 static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb",
150 		      0x060, BIT(6), 0);
151 static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb",
152 		      0x060, BIT(8), 0);
153 static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb",
154 		      0x060, BIT(9), 0);
155 static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb",
156 		      0x060, BIT(14), 0);
157 static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb",
158 		      0x060, BIT(20), 0);
159 static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb",
160 		      0x060, BIT(21), 0);
161 static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb",
162 		      0x060, BIT(24), 0);
163 
164 static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb",
165 		      0x064, BIT(0), 0);
166 static SUNXI_CCU_GATE(bus_lcd_clk,	"bus-lcd",	"ahb",
167 		      0x064, BIT(4), 0);
168 static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb",
169 		      0x064, BIT(5), 0);
170 static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb",
171 		      0x064, BIT(8), 0);
172 static SUNXI_CCU_GATE(bus_tvd_clk,	"bus-tvd",	"ahb",
173 		      0x064, BIT(9), 0);
174 static SUNXI_CCU_GATE(bus_tve_clk,	"bus-tve",	"ahb",
175 		      0x064, BIT(10), 0);
176 static SUNXI_CCU_GATE(bus_de_be_clk,	"bus-de-be",	"ahb",
177 		      0x064, BIT(12), 0);
178 static SUNXI_CCU_GATE(bus_de_fe_clk,	"bus-de-fe",	"ahb",
179 		      0x064, BIT(14), 0);
180 
181 static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb",
182 		      0x068, BIT(0), 0);
183 static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb",
184 		      0x068, BIT(1), 0);
185 static SUNXI_CCU_GATE(bus_ir_clk,	"bus-ir",	"apb",
186 		      0x068, BIT(2), 0);
187 static SUNXI_CCU_GATE(bus_rsb_clk,	"bus-rsb",	"apb",
188 		      0x068, BIT(3), 0);
189 static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb",
190 		      0x068, BIT(12), 0);
191 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb",
192 		      0x068, BIT(16), 0);
193 static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb",
194 		      0x068, BIT(17), 0);
195 static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb",
196 		      0x068, BIT(18), 0);
197 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb",
198 		      0x068, BIT(19), 0);
199 static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb",
200 		      0x068, BIT(20), 0);
201 static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb",
202 		      0x068, BIT(21), 0);
203 static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb",
204 		      0x068, BIT(22), 0);
205 
206 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
207 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
208 				  0, 4,		/* M */
209 				  16, 2,	/* P */
210 				  24, 2,	/* mux */
211 				  BIT(31),	/* gate */
212 				  0);
213 
214 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
215 		       0x088, 20, 3, 0);
216 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
217 		       0x088, 8, 3, 0);
218 
219 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
220 				  0, 4,		/* M */
221 				  16, 2,	/* P */
222 				  24, 2,	/* mux */
223 				  BIT(31),	/* gate */
224 				  0);
225 
226 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
227 		       0x08c, 20, 3, 0);
228 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
229 		       0x08c, 8, 3, 0);
230 
231 static const char * const i2s_spdif_parents[] = { "pll-audio-8x",
232 						  "pll-audio-4x",
233 						  "pll-audio-2x",
234 						  "pll-audio" };
235 
236 static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
237 			       0x0b0, 16, 2, BIT(31), 0);
238 
239 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
240 			       0x0b4, 16, 2, BIT(31), 0);
241 
242 static const char * const ir_parents[] = { "osc32k", "osc24M" };
243 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
244 				  ir_parents, 0x0b8,
245 				  0, 4,		/* M */
246 				  16, 2,	/* P */
247 				  24, 2,        /* mux */
248 				  BIT(31),      /* gate */
249 				  0);
250 
251 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
252 		      0x0cc, BIT(1), 0);
253 
254 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"pll-ddr",
255 		      0x100, BIT(0), 0);
256 static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"pll-ddr",
257 		      0x100, BIT(1), 0);
258 static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",
259 		      "pll-ddr", 0x100, BIT(2), 0);
260 static SUNXI_CCU_GATE(dram_tvd_clk,	"dram-tvd",	"pll-ddr",
261 		      0x100, BIT(3), 0);
262 static SUNXI_CCU_GATE(dram_de_fe_clk,	"dram-de-fe",	"pll-ddr",
263 		      0x100, BIT(24), 0);
264 static SUNXI_CCU_GATE(dram_de_be_clk,	"dram-de-be",	"pll-ddr",
265 		      0x100, BIT(26), 0);
266 
267 static const char * const de_parents[] = { "pll-video", "pll-periph" };
268 static const u8 de_table[] = { 0, 2, };
269 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
270 				       de_parents, de_table,
271 				       0x104, 0, 4, 24, 3, BIT(31), 0);
272 
273 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
274 				       de_parents, de_table,
275 				       0x10c, 0, 4, 24, 3, BIT(31), 0);
276 
277 static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" };
278 static const u8 tcon_table[] = { 0, 2, };
279 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon",
280 				     tcon_parents, tcon_table,
281 				     0x118, 24, 3, BIT(31),
282 				     CLK_SET_RATE_PARENT);
283 
284 static const char * const deinterlace_parents[] = { "pll-video",
285 						    "pll-video-2x" };
286 static const u8 deinterlace_table[] = { 0, 2, };
287 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace",
288 				       deinterlace_parents, deinterlace_table,
289 				       0x11c, 0, 4, 24, 3, BIT(31), 0);
290 
291 static const char * const tve_clk2_parents[] = { "pll-video",
292 						 "pll-video-2x" };
293 static const u8 tve_clk2_table[] = { 0, 2, };
294 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
295 				       tve_clk2_parents, tve_clk2_table,
296 				       0x120, 0, 4, 24, 3, BIT(31), 0);
297 static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
298 			     0x120, 8, 1, BIT(15), 0);
299 
300 static const char * const tvd_parents[] = { "pll-video", "osc24M",
301 					    "pll-video-2x" };
302 static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents,
303 				 0x124, 0, 4, 24, 3, BIT(31), 0);
304 
305 static const char * const csi_parents[] = { "pll-video", "osc24M" };
306 static const u8 csi_table[] = { 0, 5, };
307 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table,
308 				       0x120, 0, 4, 8, 3, BIT(15), 0);
309 
310 /*
311  * TODO: BSP says the parent is pll-audio, however common sense and experience
312  * told us it should be pll-ve. pll-ve is totally not used in BSP code.
313  */
314 static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
315 
316 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
317 
318 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
319 
320 static struct ccu_common *suniv_ccu_clks[] = {
321 	&pll_cpu_clk.common,
322 	&pll_audio_base_clk.common,
323 	&pll_video_clk.common,
324 	&pll_ve_clk.common,
325 	&pll_ddr0_clk.common,
326 	&pll_periph_clk.common,
327 	&cpu_clk.common,
328 	&ahb_clk.common,
329 	&apb_clk.common,
330 	&bus_dma_clk.common,
331 	&bus_mmc0_clk.common,
332 	&bus_mmc1_clk.common,
333 	&bus_dram_clk.common,
334 	&bus_spi0_clk.common,
335 	&bus_spi1_clk.common,
336 	&bus_otg_clk.common,
337 	&bus_ve_clk.common,
338 	&bus_lcd_clk.common,
339 	&bus_deinterlace_clk.common,
340 	&bus_csi_clk.common,
341 	&bus_tve_clk.common,
342 	&bus_tvd_clk.common,
343 	&bus_de_be_clk.common,
344 	&bus_de_fe_clk.common,
345 	&bus_codec_clk.common,
346 	&bus_spdif_clk.common,
347 	&bus_ir_clk.common,
348 	&bus_rsb_clk.common,
349 	&bus_i2s0_clk.common,
350 	&bus_i2c0_clk.common,
351 	&bus_i2c1_clk.common,
352 	&bus_i2c2_clk.common,
353 	&bus_pio_clk.common,
354 	&bus_uart0_clk.common,
355 	&bus_uart1_clk.common,
356 	&bus_uart2_clk.common,
357 	&mmc0_clk.common,
358 	&mmc0_sample_clk.common,
359 	&mmc0_output_clk.common,
360 	&mmc1_clk.common,
361 	&mmc1_sample_clk.common,
362 	&mmc1_output_clk.common,
363 	&i2s_clk.common,
364 	&spdif_clk.common,
365 	&ir_clk.common,
366 	&usb_phy0_clk.common,
367 	&dram_ve_clk.common,
368 	&dram_csi_clk.common,
369 	&dram_deinterlace_clk.common,
370 	&dram_tvd_clk.common,
371 	&dram_de_fe_clk.common,
372 	&dram_de_be_clk.common,
373 	&de_be_clk.common,
374 	&de_fe_clk.common,
375 	&tcon_clk.common,
376 	&deinterlace_clk.common,
377 	&tve_clk2_clk.common,
378 	&tve_clk1_clk.common,
379 	&tvd_clk.common,
380 	&csi_clk.common,
381 	&ve_clk.common,
382 	&codec_clk.common,
383 	&avs_clk.common,
384 };
385 
386 static const struct clk_hw *clk_parent_pll_audio[] = {
387 	&pll_audio_base_clk.common.hw
388 };
389 
390 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
391 			    clk_parent_pll_audio,
392 			    4, 1, CLK_SET_RATE_PARENT);
393 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
394 			    clk_parent_pll_audio,
395 			    2, 1, CLK_SET_RATE_PARENT);
396 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
397 			    clk_parent_pll_audio,
398 			    1, 1, CLK_SET_RATE_PARENT);
399 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
400 			    clk_parent_pll_audio,
401 			    1, 2, CLK_SET_RATE_PARENT);
402 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
403 			    &pll_video_clk.common.hw,
404 			    1, 2, 0);
405 
406 static struct clk_hw_onecell_data suniv_hw_clks = {
407 	.hws	= {
408 		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
409 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
410 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
411 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
412 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
413 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
414 		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
415 		[CLK_PLL_VIDEO_2X]	= &pll_video_2x_clk.hw,
416 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
417 		[CLK_PLL_DDR0]		= &pll_ddr0_clk.common.hw,
418 		[CLK_PLL_PERIPH]	= &pll_periph_clk.common.hw,
419 		[CLK_CPU]		= &cpu_clk.common.hw,
420 		[CLK_AHB]		= &ahb_clk.common.hw,
421 		[CLK_APB]		= &apb_clk.common.hw,
422 		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
423 		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
424 		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
425 		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
426 		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
427 		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
428 		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
429 		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
430 		[CLK_BUS_LCD]		= &bus_lcd_clk.common.hw,
431 		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
432 		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
433 		[CLK_BUS_TVD]		= &bus_tvd_clk.common.hw,
434 		[CLK_BUS_TVE]		= &bus_tve_clk.common.hw,
435 		[CLK_BUS_DE_BE]		= &bus_de_be_clk.common.hw,
436 		[CLK_BUS_DE_FE]		= &bus_de_fe_clk.common.hw,
437 		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
438 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
439 		[CLK_BUS_IR]		= &bus_ir_clk.common.hw,
440 		[CLK_BUS_RSB]		= &bus_rsb_clk.common.hw,
441 		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
442 		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
443 		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
444 		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
445 		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
446 		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
447 		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
448 		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
449 		[CLK_MMC0]		= &mmc0_clk.common.hw,
450 		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
451 		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
452 		[CLK_MMC1]		= &mmc1_clk.common.hw,
453 		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
454 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
455 		[CLK_I2S]		= &i2s_clk.common.hw,
456 		[CLK_SPDIF]		= &spdif_clk.common.hw,
457 		[CLK_IR]		= &ir_clk.common.hw,
458 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
459 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
460 		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
461 		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
462 		[CLK_DRAM_TVD]		= &dram_tvd_clk.common.hw,
463 		[CLK_DRAM_DE_FE]	= &dram_de_fe_clk.common.hw,
464 		[CLK_DRAM_DE_BE]	= &dram_de_be_clk.common.hw,
465 		[CLK_DE_BE]		= &de_be_clk.common.hw,
466 		[CLK_DE_FE]		= &de_fe_clk.common.hw,
467 		[CLK_TCON]		= &tcon_clk.common.hw,
468 		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
469 		[CLK_TVE2_CLK]		= &tve_clk2_clk.common.hw,
470 		[CLK_TVE1_CLK]		= &tve_clk1_clk.common.hw,
471 		[CLK_TVD]		= &tvd_clk.common.hw,
472 		[CLK_CSI]		= &csi_clk.common.hw,
473 		[CLK_VE]		= &ve_clk.common.hw,
474 		[CLK_CODEC]		= &codec_clk.common.hw,
475 		[CLK_AVS]		= &avs_clk.common.hw,
476 	},
477 	.num	= CLK_NUMBER,
478 };
479 
480 static struct ccu_reset_map suniv_ccu_resets[] = {
481 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
482 
483 	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
484 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
485 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
486 	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
487 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
488 	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
489 	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
490 	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
491 	[RST_BUS_LCD]		=  { 0x2c4, BIT(4) },
492 	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
493 	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
494 	[RST_BUS_TVD]		=  { 0x2c4, BIT(9) },
495 	[RST_BUS_TVE]		=  { 0x2c4, BIT(10) },
496 	[RST_BUS_DE_BE]		=  { 0x2c4, BIT(12) },
497 	[RST_BUS_DE_FE]		=  { 0x2c4, BIT(14) },
498 	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
499 	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
500 	[RST_BUS_IR]		=  { 0x2d0, BIT(2) },
501 	[RST_BUS_RSB]		=  { 0x2d0, BIT(3) },
502 	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
503 	[RST_BUS_I2C0]		=  { 0x2d0, BIT(16) },
504 	[RST_BUS_I2C1]		=  { 0x2d0, BIT(17) },
505 	[RST_BUS_I2C2]		=  { 0x2d0, BIT(18) },
506 	[RST_BUS_UART0]		=  { 0x2d0, BIT(20) },
507 	[RST_BUS_UART1]		=  { 0x2d0, BIT(21) },
508 	[RST_BUS_UART2]		=  { 0x2d0, BIT(22) },
509 };
510 
511 static const struct sunxi_ccu_desc suniv_ccu_desc = {
512 	.ccu_clks	= suniv_ccu_clks,
513 	.num_ccu_clks	= ARRAY_SIZE(suniv_ccu_clks),
514 
515 	.hw_clks	= &suniv_hw_clks,
516 
517 	.resets		= suniv_ccu_resets,
518 	.num_resets	= ARRAY_SIZE(suniv_ccu_resets),
519 };
520 
521 static struct ccu_pll_nb suniv_pll_cpu_nb = {
522 	.common	= &pll_cpu_clk.common,
523 	/* copy from pll_cpu_clk */
524 	.enable	= BIT(31),
525 	.lock	= BIT(28),
526 };
527 
528 static struct ccu_mux_nb suniv_cpu_nb = {
529 	.common		= &cpu_clk.common,
530 	.cm		= &cpu_clk.mux,
531 	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
532 	.bypass_index	= 1, /* index of 24 MHz oscillator */
533 };
534 
suniv_f1c100s_ccu_probe(struct platform_device * pdev)535 static int suniv_f1c100s_ccu_probe(struct platform_device *pdev)
536 {
537 	void __iomem *reg;
538 	int ret;
539 	u32 val;
540 
541 	reg = devm_platform_ioremap_resource(pdev, 0);
542 	if (IS_ERR(reg))
543 		return PTR_ERR(reg);
544 
545 	/* Force the PLL-Audio-1x divider to 4 */
546 	val = readl(reg + SUNIV_PLL_AUDIO_REG);
547 	val &= ~GENMASK(19, 16);
548 	writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
549 
550 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &suniv_ccu_desc);
551 	if (ret)
552 		return ret;
553 
554 	/* Gate then ungate PLL CPU after any rate changes */
555 	ccu_pll_notifier_register(&suniv_pll_cpu_nb);
556 
557 	/* Reparent CPU during PLL CPU rate changes */
558 	ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
559 				  &suniv_cpu_nb);
560 
561 	return 0;
562 }
563 
564 static const struct of_device_id suniv_f1c100s_ccu_ids[] = {
565 	{ .compatible = "allwinner,suniv-f1c100s-ccu" },
566 	{ }
567 };
568 
569 static struct platform_driver suniv_f1c100s_ccu_driver = {
570 	.probe	= suniv_f1c100s_ccu_probe,
571 	.driver	= {
572 		.name			= "suniv-f1c100s-ccu",
573 		.suppress_bind_attrs	= true,
574 		.of_match_table		= suniv_f1c100s_ccu_ids,
575 	},
576 };
577 module_platform_driver(suniv_f1c100s_ccu_driver);
578 
579 MODULE_IMPORT_NS(SUNXI_CCU);
580 MODULE_LICENSE("GPL");
581