1 /*
2 * Allwinner a33 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/pinctrl/pinctrl.h>
19
20 #include "pinctrl-sunxi.h"
21
22 static const struct sunxi_desc_pin sun8i_a33_pins[] = {
23 /* Hole */
24 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
25 SUNXI_FUNCTION(0x0, "gpio_in"),
26 SUNXI_FUNCTION(0x1, "gpio_out"),
27 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
28 SUNXI_FUNCTION(0x3, "uart0"), /* TX */
29 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
30 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
31 SUNXI_FUNCTION(0x0, "gpio_in"),
32 SUNXI_FUNCTION(0x1, "gpio_out"),
33 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
34 SUNXI_FUNCTION(0x3, "uart0"), /* RX */
35 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
40 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
42 SUNXI_FUNCTION(0x0, "gpio_in"),
43 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
45 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
50 SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
51 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
56 SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
57 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
62 SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
63 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
68 SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
70 /* Hole */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
75 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
80 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
85 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
90 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
99 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out"),
103 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
104 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
105 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
106 SUNXI_FUNCTION(0x0, "gpio_in"),
107 SUNXI_FUNCTION(0x1, "gpio_out"),
108 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
109 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
110 SUNXI_FUNCTION(0x0, "gpio_in"),
111 SUNXI_FUNCTION(0x1, "gpio_out"),
112 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
113 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
114 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
115 SUNXI_FUNCTION(0x0, "gpio_in"),
116 SUNXI_FUNCTION(0x1, "gpio_out"),
117 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
118 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
119 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
120 SUNXI_FUNCTION(0x0, "gpio_in"),
121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
123 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
128 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
133 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
134 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
135 SUNXI_FUNCTION(0x0, "gpio_in"),
136 SUNXI_FUNCTION(0x1, "gpio_out"),
137 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
138 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
139 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
140 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out"),
142 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
143 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
144 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
145 SUNXI_FUNCTION(0x0, "gpio_in"),
146 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
148 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
153 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
154 /* Hole */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
159 SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
164 SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
165 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
166 SUNXI_FUNCTION(0x0, "gpio_in"),
167 SUNXI_FUNCTION(0x1, "gpio_out"),
168 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
169 SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
174 SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
179 SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
184 SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
189 SUNXI_FUNCTION(0x3, "uart1")), /* TX */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
194 SUNXI_FUNCTION(0x3, "uart1")), /* RX */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
199 SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
201 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
204 SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
217 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
218 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
219 SUNXI_FUNCTION(0x0, "gpio_in"),
220 SUNXI_FUNCTION(0x1, "gpio_out"),
221 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
222 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
223 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
224 SUNXI_FUNCTION(0x0, "gpio_in"),
225 SUNXI_FUNCTION(0x1, "gpio_out"),
226 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
227 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
232 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
237 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
242 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
247 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
249 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out"),
251 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
252 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
254 SUNXI_FUNCTION(0x0, "gpio_in"),
255 SUNXI_FUNCTION(0x1, "gpio_out"),
256 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
257 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
258 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
259 SUNXI_FUNCTION(0x0, "gpio_in"),
260 SUNXI_FUNCTION(0x1, "gpio_out"),
261 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
262 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
263 /* Hole */
264 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
276 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
284 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
285 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out"),
287 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
296 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
297 SUNXI_FUNCTION(0x0, "gpio_in"),
298 SUNXI_FUNCTION(0x1, "gpio_out"),
299 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out"),
311 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
316 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
321 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out")),
325 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
326 SUNXI_FUNCTION(0x0, "gpio_in"),
327 SUNXI_FUNCTION(0x1, "gpio_out")),
328 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out")),
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out")),
334 /* Hole */
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
336 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
339 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
340 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
341 SUNXI_FUNCTION(0x0, "gpio_in"),
342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
344 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
349 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
350 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
351 SUNXI_FUNCTION(0x0, "gpio_in"),
352 SUNXI_FUNCTION(0x1, "gpio_out"),
353 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
354 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
359 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
364 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
365 /* Hole */
366 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
370 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
375 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
376 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
377 SUNXI_FUNCTION(0x0, "gpio_in"),
378 SUNXI_FUNCTION(0x1, "gpio_out"),
379 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
380 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
381 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
382 SUNXI_FUNCTION(0x0, "gpio_in"),
383 SUNXI_FUNCTION(0x1, "gpio_out"),
384 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
385 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
386 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
387 SUNXI_FUNCTION(0x0, "gpio_in"),
388 SUNXI_FUNCTION(0x1, "gpio_out"),
389 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
390 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
395 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
400 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
401 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
402 SUNXI_FUNCTION(0x0, "gpio_in"),
403 SUNXI_FUNCTION(0x1, "gpio_out"),
404 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
405 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
406 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
407 SUNXI_FUNCTION(0x0, "gpio_in"),
408 SUNXI_FUNCTION(0x1, "gpio_out"),
409 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
410 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
411 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
412 SUNXI_FUNCTION(0x0, "gpio_in"),
413 SUNXI_FUNCTION(0x1, "gpio_out"),
414 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
415 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
416 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
417 SUNXI_FUNCTION(0x0, "gpio_in"),
418 SUNXI_FUNCTION(0x1, "gpio_out"),
419 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
420 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
425 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
426 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
427 SUNXI_FUNCTION(0x0, "gpio_in"),
428 SUNXI_FUNCTION(0x1, "gpio_out"),
429 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
430 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
431 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
432 SUNXI_FUNCTION(0x0, "gpio_in"),
433 SUNXI_FUNCTION(0x1, "gpio_out"),
434 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
435 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
436 /* Hole */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "pwm0")),
441 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
442 SUNXI_FUNCTION(0x0, "gpio_in"),
443 SUNXI_FUNCTION(0x1, "gpio_out"),
444 SUNXI_FUNCTION(0x2, "pwm1")),
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
449 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
450 SUNXI_FUNCTION(0x0, "gpio_in"),
451 SUNXI_FUNCTION(0x1, "gpio_out"),
452 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
453 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
454 SUNXI_FUNCTION(0x0, "gpio_in"),
455 SUNXI_FUNCTION(0x1, "gpio_out"),
456 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out"),
464 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
465 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
466 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
470 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
471 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
472 SUNXI_FUNCTION(0x0, "gpio_in"),
473 SUNXI_FUNCTION(0x1, "gpio_out"),
474 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
475 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x1, "gpio_out"),
479 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
480 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
481 };
482
483 static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 };
484
485 static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
486 .pins = sun8i_a33_pins,
487 .npins = ARRAY_SIZE(sun8i_a33_pins),
488 .irq_banks = 2,
489 .irq_bank_map = sun8i_a33_pinctrl_irq_bank_map,
490 .disable_strict_mode = true,
491 };
492
sun8i_a33_pinctrl_probe(struct platform_device * pdev)493 static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
494 {
495 return sunxi_pinctrl_init(pdev,
496 &sun8i_a33_pinctrl_data);
497 }
498
499 static const struct of_device_id sun8i_a33_pinctrl_match[] = {
500 { .compatible = "allwinner,sun8i-a33-pinctrl", },
501 {}
502 };
503
504 static struct platform_driver sun8i_a33_pinctrl_driver = {
505 .probe = sun8i_a33_pinctrl_probe,
506 .driver = {
507 .name = "sun8i-a33-pinctrl",
508 .of_match_table = sun8i_a33_pinctrl_match,
509 },
510 };
511 builtin_platform_driver(sun8i_a33_pinctrl_driver);
512