1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
13
14 #include "ccu_div.h"
15 #include "ccu_gate.h"
16 #include "ccu_mp.h"
17 #include "ccu_mult.h"
18 #include "ccu_nk.h"
19 #include "ccu_nkm.h"
20 #include "ccu_nkmp.h"
21 #include "ccu_nm.h"
22 #include "ccu_phase.h"
23
24 #include "ccu-sun50i-a64.h"
25
26 static struct ccu_nkmp pll_cpux_clk = {
27 .enable = BIT(31),
28 .lock = BIT(28),
29 .n = _SUNXI_CCU_MULT(8, 5),
30 .k = _SUNXI_CCU_MULT(4, 2),
31 .m = _SUNXI_CCU_DIV(0, 2),
32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
33 .common = {
34 .reg = 0x000,
35 .hw.init = CLK_HW_INIT("pll-cpux",
36 "osc24M",
37 &ccu_nkmp_ops,
38 CLK_SET_RATE_UNGATE),
39 },
40 };
41
42 /*
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * the base (2x, 4x and 8x), and one variable divider (the one true
45 * pll audio).
46 *
47 * With sigma-delta modulation for fractional-N on the audio PLL,
48 * we have to use specific dividers. This means the variable divider
49 * can no longer be used, as the audio codec requests the exact clock
50 * rates we support through this mechanism. So we now hard code the
51 * variable divider to 1. This means the clock rates will no longer
52 * match the clock names.
53 */
54 #define SUN50I_A64_PLL_AUDIO_REG 0x008
55
56 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
59 };
60
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
62 "osc24M", 0x008,
63 8, 7, /* N */
64 0, 5, /* M */
65 pll_audio_sdm_table, BIT(24),
66 0x284, BIT(31),
67 BIT(31), /* gate */
68 BIT(28), /* lock */
69 CLK_SET_RATE_UNGATE);
70
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",
72 "osc24M", 0x010,
73 192000000, /* Minimum rate */
74 1008000000, /* Maximum rate */
75 8, 7, /* N */
76 0, 4, /* M */
77 BIT(24), /* frac enable */
78 BIT(25), /* frac select */
79 270000000, /* frac rate 0 */
80 297000000, /* frac rate 1 */
81 BIT(31), /* gate */
82 BIT(28), /* lock */
83 CLK_SET_RATE_UNGATE);
84
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
86 "osc24M", 0x018,
87 8, 7, /* N */
88 0, 4, /* M */
89 BIT(24), /* frac enable */
90 BIT(25), /* frac select */
91 270000000, /* frac rate 0 */
92 297000000, /* frac rate 1 */
93 BIT(31), /* gate */
94 BIT(28), /* lock */
95 CLK_SET_RATE_UNGATE);
96
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
98 "osc24M", 0x020,
99 8, 5, /* N */
100 4, 2, /* K */
101 0, 2, /* M */
102 BIT(31), /* gate */
103 BIT(28), /* lock */
104 CLK_SET_RATE_UNGATE);
105
106 static struct ccu_nk pll_periph0_clk = {
107 .enable = BIT(31),
108 .lock = BIT(28),
109 .n = _SUNXI_CCU_MULT(8, 5),
110 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
111 .fixed_post_div = 2,
112 .common = {
113 .reg = 0x028,
114 .features = CCU_FEATURE_FIXED_POSTDIV,
115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
116 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
117 },
118 };
119
120 static struct ccu_nk pll_periph1_clk = {
121 .enable = BIT(31),
122 .lock = BIT(28),
123 .n = _SUNXI_CCU_MULT(8, 5),
124 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
125 .fixed_post_div = 2,
126 .common = {
127 .reg = 0x02c,
128 .features = CCU_FEATURE_FIXED_POSTDIV,
129 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
130 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
131 },
132 };
133
134 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
135 "osc24M", 0x030,
136 192000000, /* Minimum rate */
137 1008000000, /* Maximum rate */
138 8, 7, /* N */
139 0, 4, /* M */
140 BIT(24), /* frac enable */
141 BIT(25), /* frac select */
142 270000000, /* frac rate 0 */
143 297000000, /* frac rate 1 */
144 BIT(31), /* gate */
145 BIT(28), /* lock */
146 CLK_SET_RATE_UNGATE);
147
148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
149 "osc24M", 0x038,
150 8, 7, /* N */
151 0, 4, /* M */
152 BIT(24), /* frac enable */
153 BIT(25), /* frac select */
154 270000000, /* frac rate 0 */
155 297000000, /* frac rate 1 */
156 BIT(31), /* gate */
157 BIT(28), /* lock */
158 CLK_SET_RATE_UNGATE);
159
160 /*
161 * The output function can be changed to something more complex that
162 * we do not handle yet.
163 *
164 * Hardcode the mode so that we don't fall in that case.
165 */
166 #define SUN50I_A64_PLL_MIPI_REG 0x040
167
168 static struct ccu_nkm pll_mipi_clk = {
169 /*
170 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
171 * user manual, and by experiments the PLL doesn't work without
172 * these bits toggled.
173 */
174 .enable = BIT(31) | BIT(23) | BIT(22),
175 .lock = BIT(28),
176 .n = _SUNXI_CCU_MULT(8, 4),
177 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
178 .m = _SUNXI_CCU_DIV(0, 4),
179 .common = {
180 .reg = 0x040,
181 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
182 &ccu_nkm_ops,
183 CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT),
184 .features = CCU_FEATURE_CLOSEST_RATE,
185 .min_rate = 500000000,
186 .max_rate = 1400000000,
187 },
188 };
189
190 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
191 "osc24M", 0x044,
192 8, 7, /* N */
193 0, 4, /* M */
194 BIT(24), /* frac enable */
195 BIT(25), /* frac select */
196 270000000, /* frac rate 0 */
197 297000000, /* frac rate 1 */
198 BIT(31), /* gate */
199 BIT(28), /* lock */
200 CLK_SET_RATE_UNGATE);
201
202 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
203 "osc24M", 0x048,
204 8, 7, /* N */
205 0, 4, /* M */
206 BIT(24), /* frac enable */
207 BIT(25), /* frac select */
208 270000000, /* frac rate 0 */
209 297000000, /* frac rate 1 */
210 BIT(31), /* gate */
211 BIT(28), /* lock */
212 CLK_SET_RATE_UNGATE);
213
214 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
215 "osc24M", 0x04c,
216 8, 7, /* N */
217 0, 2, /* M */
218 BIT(31), /* gate */
219 BIT(28), /* lock */
220 CLK_SET_RATE_UNGATE);
221
222 static const char * const cpux_parents[] = { "osc32k", "osc24M",
223 "pll-cpux", "pll-cpux" };
224 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
225 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
226
227 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
228
229 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
230 "axi", "pll-periph0" };
231 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
232 { .index = 3, .shift = 6, .width = 2 },
233 };
234 static struct ccu_div ahb1_clk = {
235 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
236
237 .mux = {
238 .shift = 12,
239 .width = 2,
240
241 .var_predivs = ahb1_predivs,
242 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
243 },
244
245 .common = {
246 .reg = 0x054,
247 .features = CCU_FEATURE_VARIABLE_PREDIV,
248 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
249 ahb1_parents,
250 &ccu_div_ops,
251 0),
252 },
253 };
254
255 static struct clk_div_table apb1_div_table[] = {
256 { .val = 0, .div = 2 },
257 { .val = 1, .div = 2 },
258 { .val = 2, .div = 4 },
259 { .val = 3, .div = 8 },
260 { /* Sentinel */ },
261 };
262 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
263 0x054, 8, 2, apb1_div_table, 0);
264
265 static const char * const apb2_parents[] = { "osc32k", "osc24M",
266 "pll-periph0-2x",
267 "pll-periph0-2x" };
268 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
269 0, 5, /* M */
270 16, 2, /* P */
271 24, 2, /* mux */
272 0);
273
274 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
275 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
276 { .index = 1, .div = 2 },
277 };
278 static struct ccu_mux ahb2_clk = {
279 .mux = {
280 .shift = 0,
281 .width = 1,
282 .fixed_predivs = ahb2_fixed_predivs,
283 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
284 },
285
286 .common = {
287 .reg = 0x05c,
288 .features = CCU_FEATURE_FIXED_PREDIV,
289 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
290 ahb2_parents,
291 &ccu_mux_ops,
292 0),
293 },
294 };
295
296 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
297 0x060, BIT(1), 0);
298 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
299 0x060, BIT(5), 0);
300 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
301 0x060, BIT(6), 0);
302 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
303 0x060, BIT(8), 0);
304 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
305 0x060, BIT(9), 0);
306 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
307 0x060, BIT(10), 0);
308 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
309 0x060, BIT(13), 0);
310 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
311 0x060, BIT(14), 0);
312 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
313 0x060, BIT(17), 0);
314 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
315 0x060, BIT(18), 0);
316 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
317 0x060, BIT(19), 0);
318 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
319 0x060, BIT(20), 0);
320 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
321 0x060, BIT(21), 0);
322 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
323 0x060, BIT(23), 0);
324 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
325 0x060, BIT(24), 0);
326 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
327 0x060, BIT(25), 0);
328 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
329 0x060, BIT(28), 0);
330 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
331 0x060, BIT(29), 0);
332
333 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
334 0x064, BIT(0), 0);
335 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
336 0x064, BIT(3), 0);
337 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
338 0x064, BIT(4), 0);
339 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
340 0x064, BIT(5), 0);
341 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
342 0x064, BIT(8), 0);
343 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
344 0x064, BIT(11), 0);
345 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
346 0x064, BIT(12), 0);
347 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
348 0x064, BIT(20), 0);
349 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
350 0x064, BIT(21), 0);
351 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
352 0x064, BIT(22), 0);
353
354 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
355 0x068, BIT(0), 0);
356 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
357 0x068, BIT(1), 0);
358 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
359 0x068, BIT(5), 0);
360 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
361 0x068, BIT(8), 0);
362 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
363 0x068, BIT(12), 0);
364 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
365 0x068, BIT(13), 0);
366 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
367 0x068, BIT(14), 0);
368
369 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
370 0x06c, BIT(0), 0);
371 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
372 0x06c, BIT(1), 0);
373 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
374 0x06c, BIT(2), 0);
375 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
376 0x06c, BIT(5), 0);
377 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
378 0x06c, BIT(16), 0);
379 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
380 0x06c, BIT(17), 0);
381 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
382 0x06c, BIT(18), 0);
383 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
384 0x06c, BIT(19), 0);
385 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
386 0x06c, BIT(20), 0);
387
388 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
389 0x070, BIT(7), 0);
390
391 static struct clk_div_table ths_div_table[] = {
392 { .val = 0, .div = 1 },
393 { .val = 1, .div = 2 },
394 { .val = 2, .div = 4 },
395 { .val = 3, .div = 6 },
396 { /* Sentinel */ },
397 };
398 static const char * const ths_parents[] = { "osc24M" };
399 static struct ccu_div ths_clk = {
400 .enable = BIT(31),
401 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
402 .mux = _SUNXI_CCU_MUX(24, 2),
403 .common = {
404 .reg = 0x074,
405 .hw.init = CLK_HW_INIT_PARENTS("ths",
406 ths_parents,
407 &ccu_div_ops,
408 0),
409 },
410 };
411
412 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
413 "pll-periph1" };
414 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
415 0, 4, /* M */
416 16, 2, /* P */
417 24, 2, /* mux */
418 BIT(31), /* gate */
419 0);
420
421 /*
422 * MMC clocks are the new timing mode (see A83T & H3) variety, but without
423 * the mode switch. This means they have a 2x post divider between the clock
424 * and the MMC module. This is not documented in the manual, but is taken
425 * into consideration when setting the mmc module clocks in the BSP kernel.
426 * Without it, MMC performance is degraded.
427 *
428 * We model it here to be consistent with other SoCs supporting this mode.
429 * The alternative would be to add the 2x multiplier when setting the MMC
430 * module clock in the MMC driver, just for the A64.
431 */
432 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
433 "pll-periph1-2x" };
434 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
435 mmc_default_parents, 0x088,
436 0, 4, /* M */
437 16, 2, /* P */
438 24, 2, /* mux */
439 BIT(31), /* gate */
440 2, /* post-div */
441 0);
442
443 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
444 mmc_default_parents, 0x08c,
445 0, 4, /* M */
446 16, 2, /* P */
447 24, 2, /* mux */
448 BIT(31), /* gate */
449 2, /* post-div */
450 0);
451
452 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
453 mmc_default_parents, 0x090,
454 0, 4, /* M */
455 16, 2, /* P */
456 24, 2, /* mux */
457 BIT(31), /* gate */
458 2, /* post-div */
459 0);
460
461 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
462 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
463 0, 4, /* M */
464 16, 2, /* P */
465 24, 4, /* mux */
466 BIT(31), /* gate */
467 0);
468
469 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
470 0, 4, /* M */
471 16, 2, /* P */
472 24, 2, /* mux */
473 BIT(31), /* gate */
474 0);
475
476 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
477 0, 4, /* M */
478 16, 2, /* P */
479 24, 2, /* mux */
480 BIT(31), /* gate */
481 0);
482
483 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
484 0, 4, /* M */
485 16, 2, /* P */
486 24, 2, /* mux */
487 BIT(31), /* gate */
488 0);
489
490 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
491 "pll-audio-2x", "pll-audio" };
492 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
493 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
494
495 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
496 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
497
498 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
499 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
500
501 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
502 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
503
504 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
505 0x0cc, BIT(8), 0);
506 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
507 0x0cc, BIT(9), 0);
508 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
509 0x0cc, BIT(10), 0);
510 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
511 0x0cc, BIT(11), 0);
512 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
513 0x0cc, BIT(16), 0);
514 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
515 0x0cc, BIT(17), 0);
516
517 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
518 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
519 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
520
521 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
522 0x100, BIT(0), 0);
523 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
524 0x100, BIT(1), 0);
525 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
526 0x100, BIT(2), 0);
527 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
528 0x100, BIT(3), 0);
529
530 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
531 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
532 0x104, 0, 4, 24, 3, BIT(31),
533 CLK_SET_RATE_PARENT);
534
535 /*
536 * DSI output seems to work only when PLL_MIPI selected. Set it and prevent
537 * the mux from reparenting.
538 */
539 #define SUN50I_A64_TCON0_CLK_REG 0x118
540
541 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
542 static const u8 tcon0_table[] = { 0, 2, };
543 static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
544 tcon0_table, 0x118, 24, 3, BIT(31),
545 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
546
547 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
548 static const u8 tcon1_table[] = { 0, 2, };
549 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents,
550 tcon1_table, 0x11c,
551 0, 4, /* M */
552 24, 2, /* mux */
553 BIT(31), /* gate */
554 CLK_SET_RATE_PARENT);
555
556 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
557 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
558 0x124, 0, 4, 24, 3, BIT(31), 0);
559
560 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
561 0x130, BIT(31), 0);
562
563 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
564 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
565 0x134, 16, 4, 24, 3, BIT(31), 0);
566
567 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
568 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
569 0x134, 0, 5, 8, 3, BIT(15), 0);
570
571 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
572 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
573
574 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
575 0x140, BIT(31), CLK_SET_RATE_PARENT);
576
577 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
578 0x140, BIT(30), CLK_SET_RATE_PARENT);
579
580 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
581 0x144, BIT(31), 0);
582
583 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
584 static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents,
585 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
586
587 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
588 0x154, BIT(31), 0);
589
590 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
591 "pll-ddr0", "pll-ddr1" };
592 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
593 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
594
595 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
596 static const u8 dsi_dphy_table[] = { 0, 2, };
597 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",
598 dsi_dphy_parents, dsi_dphy_table,
599 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
600
601 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
602 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
603
604 /* Fixed Factor clocks */
605 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
606
607 static const struct clk_hw *clk_parent_pll_audio[] = {
608 &pll_audio_base_clk.common.hw
609 };
610
611 /* We hardcode the divider to 1 for now */
612 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
613 clk_parent_pll_audio,
614 1, 1, CLK_SET_RATE_PARENT);
615 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
616 clk_parent_pll_audio,
617 2, 1, CLK_SET_RATE_PARENT);
618 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
619 clk_parent_pll_audio,
620 1, 1, CLK_SET_RATE_PARENT);
621 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
622 clk_parent_pll_audio,
623 1, 2, CLK_SET_RATE_PARENT);
624 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
625 &pll_periph0_clk.common.hw,
626 1, 2, 0);
627 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
628 &pll_periph1_clk.common.hw,
629 1, 2, 0);
630 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
631 &pll_video0_clk.common.hw,
632 1, 2, CLK_SET_RATE_PARENT);
633
634 static struct ccu_common *sun50i_a64_ccu_clks[] = {
635 &pll_cpux_clk.common,
636 &pll_audio_base_clk.common,
637 &pll_video0_clk.common,
638 &pll_ve_clk.common,
639 &pll_ddr0_clk.common,
640 &pll_periph0_clk.common,
641 &pll_periph1_clk.common,
642 &pll_video1_clk.common,
643 &pll_gpu_clk.common,
644 &pll_mipi_clk.common,
645 &pll_hsic_clk.common,
646 &pll_de_clk.common,
647 &pll_ddr1_clk.common,
648 &cpux_clk.common,
649 &axi_clk.common,
650 &ahb1_clk.common,
651 &apb1_clk.common,
652 &apb2_clk.common,
653 &ahb2_clk.common,
654 &bus_mipi_dsi_clk.common,
655 &bus_ce_clk.common,
656 &bus_dma_clk.common,
657 &bus_mmc0_clk.common,
658 &bus_mmc1_clk.common,
659 &bus_mmc2_clk.common,
660 &bus_nand_clk.common,
661 &bus_dram_clk.common,
662 &bus_emac_clk.common,
663 &bus_ts_clk.common,
664 &bus_hstimer_clk.common,
665 &bus_spi0_clk.common,
666 &bus_spi1_clk.common,
667 &bus_otg_clk.common,
668 &bus_ehci0_clk.common,
669 &bus_ehci1_clk.common,
670 &bus_ohci0_clk.common,
671 &bus_ohci1_clk.common,
672 &bus_ve_clk.common,
673 &bus_tcon0_clk.common,
674 &bus_tcon1_clk.common,
675 &bus_deinterlace_clk.common,
676 &bus_csi_clk.common,
677 &bus_hdmi_clk.common,
678 &bus_de_clk.common,
679 &bus_gpu_clk.common,
680 &bus_msgbox_clk.common,
681 &bus_spinlock_clk.common,
682 &bus_codec_clk.common,
683 &bus_spdif_clk.common,
684 &bus_pio_clk.common,
685 &bus_ths_clk.common,
686 &bus_i2s0_clk.common,
687 &bus_i2s1_clk.common,
688 &bus_i2s2_clk.common,
689 &bus_i2c0_clk.common,
690 &bus_i2c1_clk.common,
691 &bus_i2c2_clk.common,
692 &bus_scr_clk.common,
693 &bus_uart0_clk.common,
694 &bus_uart1_clk.common,
695 &bus_uart2_clk.common,
696 &bus_uart3_clk.common,
697 &bus_uart4_clk.common,
698 &bus_dbg_clk.common,
699 &ths_clk.common,
700 &nand_clk.common,
701 &mmc0_clk.common,
702 &mmc1_clk.common,
703 &mmc2_clk.common,
704 &ts_clk.common,
705 &ce_clk.common,
706 &spi0_clk.common,
707 &spi1_clk.common,
708 &i2s0_clk.common,
709 &i2s1_clk.common,
710 &i2s2_clk.common,
711 &spdif_clk.common,
712 &usb_phy0_clk.common,
713 &usb_phy1_clk.common,
714 &usb_hsic_clk.common,
715 &usb_hsic_12m_clk.common,
716 &usb_ohci0_clk.common,
717 &usb_ohci1_clk.common,
718 &dram_clk.common,
719 &dram_ve_clk.common,
720 &dram_csi_clk.common,
721 &dram_deinterlace_clk.common,
722 &dram_ts_clk.common,
723 &de_clk.common,
724 &tcon0_clk.common,
725 &tcon1_clk.common,
726 &deinterlace_clk.common,
727 &csi_misc_clk.common,
728 &csi_sclk_clk.common,
729 &csi_mclk_clk.common,
730 &ve_clk.common,
731 &ac_dig_clk.common,
732 &ac_dig_4x_clk.common,
733 &avs_clk.common,
734 &hdmi_clk.common,
735 &hdmi_ddc_clk.common,
736 &mbus_clk.common,
737 &dsi_dphy_clk.common,
738 &gpu_clk.common,
739 };
740
741 static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
742 .hws = {
743 [CLK_OSC_12M] = &osc12M_clk.hw,
744 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
745 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
746 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
747 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
748 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
749 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
750 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
751 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
752 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
753 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
754 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
755 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
756 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
757 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
758 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
759 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
760 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
761 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
762 [CLK_PLL_DE] = &pll_de_clk.common.hw,
763 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
764 [CLK_CPUX] = &cpux_clk.common.hw,
765 [CLK_AXI] = &axi_clk.common.hw,
766 [CLK_AHB1] = &ahb1_clk.common.hw,
767 [CLK_APB1] = &apb1_clk.common.hw,
768 [CLK_APB2] = &apb2_clk.common.hw,
769 [CLK_AHB2] = &ahb2_clk.common.hw,
770 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
771 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
772 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
773 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
774 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
775 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
776 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
777 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
778 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
779 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
780 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
781 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
782 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
783 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
784 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
785 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
786 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
787 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
788 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
789 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
790 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
791 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
792 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
793 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
794 [CLK_BUS_DE] = &bus_de_clk.common.hw,
795 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
796 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
797 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
798 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
799 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
800 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
801 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
802 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
803 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
804 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
805 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
806 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
807 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
808 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
809 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
810 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
811 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
812 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
813 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
814 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
815 [CLK_THS] = &ths_clk.common.hw,
816 [CLK_NAND] = &nand_clk.common.hw,
817 [CLK_MMC0] = &mmc0_clk.common.hw,
818 [CLK_MMC1] = &mmc1_clk.common.hw,
819 [CLK_MMC2] = &mmc2_clk.common.hw,
820 [CLK_TS] = &ts_clk.common.hw,
821 [CLK_CE] = &ce_clk.common.hw,
822 [CLK_SPI0] = &spi0_clk.common.hw,
823 [CLK_SPI1] = &spi1_clk.common.hw,
824 [CLK_I2S0] = &i2s0_clk.common.hw,
825 [CLK_I2S1] = &i2s1_clk.common.hw,
826 [CLK_I2S2] = &i2s2_clk.common.hw,
827 [CLK_SPDIF] = &spdif_clk.common.hw,
828 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
829 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
830 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
831 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
832 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
833 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
834 [CLK_DRAM] = &dram_clk.common.hw,
835 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
836 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
837 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
838 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
839 [CLK_DE] = &de_clk.common.hw,
840 [CLK_TCON0] = &tcon0_clk.common.hw,
841 [CLK_TCON1] = &tcon1_clk.common.hw,
842 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
843 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
844 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
845 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
846 [CLK_VE] = &ve_clk.common.hw,
847 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
848 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
849 [CLK_AVS] = &avs_clk.common.hw,
850 [CLK_HDMI] = &hdmi_clk.common.hw,
851 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
852 [CLK_MBUS] = &mbus_clk.common.hw,
853 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
854 [CLK_GPU] = &gpu_clk.common.hw,
855 },
856 .num = CLK_NUMBER,
857 };
858
859 static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
860 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
861 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
862 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
863
864 [RST_DRAM] = { 0x0f4, BIT(31) },
865 [RST_MBUS] = { 0x0fc, BIT(31) },
866
867 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
868 [RST_BUS_CE] = { 0x2c0, BIT(5) },
869 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
870 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
871 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
872 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
873 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
874 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
875 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
876 [RST_BUS_TS] = { 0x2c0, BIT(18) },
877 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
878 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
879 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
880 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
881 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
882 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
883 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
884 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
885
886 [RST_BUS_VE] = { 0x2c4, BIT(0) },
887 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
888 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
889 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
890 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
891 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
892 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
893 [RST_BUS_DE] = { 0x2c4, BIT(12) },
894 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
895 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
896 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
897 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
898
899 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
900
901 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
902 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
903 [RST_BUS_THS] = { 0x2d0, BIT(8) },
904 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
905 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
906 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
907
908 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
909 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
910 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
911 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
912 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
913 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
914 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
915 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
916 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
917 };
918
919 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
920 .ccu_clks = sun50i_a64_ccu_clks,
921 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
922
923 .hw_clks = &sun50i_a64_hw_clks,
924
925 .resets = sun50i_a64_ccu_resets,
926 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
927 };
928
929 static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
930 .common = &pll_cpux_clk.common,
931 /* copy from pll_cpux_clk */
932 .enable = BIT(31),
933 .lock = BIT(28),
934 };
935
936 static struct ccu_mux_nb sun50i_a64_cpu_nb = {
937 .common = &cpux_clk.common,
938 .cm = &cpux_clk.mux,
939 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
940 .bypass_index = 1, /* index of 24 MHz oscillator */
941 };
942
sun50i_a64_ccu_probe(struct platform_device * pdev)943 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
944 {
945 void __iomem *reg;
946 u32 val;
947 int ret;
948
949 reg = devm_platform_ioremap_resource(pdev, 0);
950 if (IS_ERR(reg))
951 return PTR_ERR(reg);
952
953 /* Force the PLL-Audio-1x divider to 1 */
954 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
955 val &= ~GENMASK(19, 16);
956 writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
957
958 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
959
960 /* Set PLL MIPI as parent for TCON0 */
961 val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
962 val &= ~GENMASK(26, 24);
963 writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
964
965 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
966 if (ret)
967 return ret;
968
969 /* Gate then ungate PLL CPU after any rate changes */
970 ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
971
972 /* Reparent CPU during PLL CPU rate changes */
973 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
974 &sun50i_a64_cpu_nb);
975
976 return 0;
977 }
978
979 static const struct of_device_id sun50i_a64_ccu_ids[] = {
980 { .compatible = "allwinner,sun50i-a64-ccu" },
981 { }
982 };
983
984 static struct platform_driver sun50i_a64_ccu_driver = {
985 .probe = sun50i_a64_ccu_probe,
986 .driver = {
987 .name = "sun50i-a64-ccu",
988 .suppress_bind_attrs = true,
989 .of_match_table = sun50i_a64_ccu_ids,
990 },
991 };
992 module_platform_driver(sun50i_a64_ccu_driver);
993
994 MODULE_IMPORT_NS(SUNXI_CCU);
995 MODULE_LICENSE("GPL");
996