xref: /openbmc/linux/drivers/pwm/pwm-sun4i.c (revision 0a41b0c5)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Driver for Allwinner sun4i Pulse Width Modulation Controller
4  *
5  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
6  *
7  * Limitations:
8  * - When outputing the source clock directly, the PWM logic will be bypassed
9  *   and the currently running period is not guaranteed to be completed
10  */
11 
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/jiffies.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/pwm.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/time.h>
26 
27 #define PWM_CTRL_REG		0x0
28 
29 #define PWM_CH_PRD_BASE		0x4
30 #define PWM_CH_PRD_OFFSET	0x4
31 #define PWM_CH_PRD(ch)		(PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
32 
33 #define PWMCH_OFFSET		15
34 #define PWM_PRESCAL_MASK	GENMASK(3, 0)
35 #define PWM_PRESCAL_OFF		0
36 #define PWM_EN			BIT(4)
37 #define PWM_ACT_STATE		BIT(5)
38 #define PWM_CLK_GATING		BIT(6)
39 #define PWM_MODE		BIT(7)
40 #define PWM_PULSE		BIT(8)
41 #define PWM_BYPASS		BIT(9)
42 
43 #define PWM_RDY_BASE		28
44 #define PWM_RDY_OFFSET		1
45 #define PWM_RDY(ch)		BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
46 
47 #define PWM_PRD(prd)		(((prd) - 1) << 16)
48 #define PWM_PRD_MASK		GENMASK(15, 0)
49 
50 #define PWM_DTY_MASK		GENMASK(15, 0)
51 
52 #define PWM_REG_PRD(reg)	((((reg) >> 16) & PWM_PRD_MASK) + 1)
53 #define PWM_REG_DTY(reg)	((reg) & PWM_DTY_MASK)
54 #define PWM_REG_PRESCAL(reg, chan)	(((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
55 
56 #define BIT_CH(bit, chan)	((bit) << ((chan) * PWMCH_OFFSET))
57 
58 static const u32 prescaler_table[] = {
59 	120,
60 	180,
61 	240,
62 	360,
63 	480,
64 	0,
65 	0,
66 	0,
67 	12000,
68 	24000,
69 	36000,
70 	48000,
71 	72000,
72 	0,
73 	0,
74 	0, /* Actually 1 but tested separately */
75 };
76 
77 struct sun4i_pwm_data {
78 	bool has_prescaler_bypass;
79 	bool has_direct_mod_clk_output;
80 	unsigned int npwm;
81 };
82 
83 struct sun4i_pwm_chip {
84 	struct pwm_chip chip;
85 	struct clk *bus_clk;
86 	struct clk *clk;
87 	struct reset_control *rst;
88 	void __iomem *base;
89 	spinlock_t ctrl_lock;
90 	const struct sun4i_pwm_data *data;
91 };
92 
to_sun4i_pwm_chip(struct pwm_chip * chip)93 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
94 {
95 	return container_of(chip, struct sun4i_pwm_chip, chip);
96 }
97 
sun4i_pwm_readl(struct sun4i_pwm_chip * chip,unsigned long offset)98 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
99 				  unsigned long offset)
100 {
101 	return readl(chip->base + offset);
102 }
103 
sun4i_pwm_writel(struct sun4i_pwm_chip * chip,u32 val,unsigned long offset)104 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
105 				    u32 val, unsigned long offset)
106 {
107 	writel(val, chip->base + offset);
108 }
109 
sun4i_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)110 static int sun4i_pwm_get_state(struct pwm_chip *chip,
111 			       struct pwm_device *pwm,
112 			       struct pwm_state *state)
113 {
114 	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
115 	u64 clk_rate, tmp;
116 	u32 val;
117 	unsigned int prescaler;
118 
119 	clk_rate = clk_get_rate(sun4i_pwm->clk);
120 	if (!clk_rate)
121 		return -EINVAL;
122 
123 	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
124 
125 	/*
126 	 * PWM chapter in H6 manual has a diagram which explains that if bypass
127 	 * bit is set, no other setting has any meaning. Even more, experiment
128 	 * proved that also enable bit is ignored in this case.
129 	 */
130 	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
131 	    sun4i_pwm->data->has_direct_mod_clk_output) {
132 		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
133 		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
134 		state->polarity = PWM_POLARITY_NORMAL;
135 		state->enabled = true;
136 		return 0;
137 	}
138 
139 	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
140 	    sun4i_pwm->data->has_prescaler_bypass)
141 		prescaler = 1;
142 	else
143 		prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
144 
145 	if (prescaler == 0)
146 		return -EINVAL;
147 
148 	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
149 		state->polarity = PWM_POLARITY_NORMAL;
150 	else
151 		state->polarity = PWM_POLARITY_INVERSED;
152 
153 	if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
154 	    BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
155 		state->enabled = true;
156 	else
157 		state->enabled = false;
158 
159 	val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
160 
161 	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
162 	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
163 
164 	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
165 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
166 
167 	return 0;
168 }
169 
sun4i_pwm_calculate(struct sun4i_pwm_chip * sun4i_pwm,const struct pwm_state * state,u32 * dty,u32 * prd,unsigned int * prsclr,bool * bypass)170 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
171 			       const struct pwm_state *state,
172 			       u32 *dty, u32 *prd, unsigned int *prsclr,
173 			       bool *bypass)
174 {
175 	u64 clk_rate, div = 0;
176 	unsigned int prescaler = 0;
177 
178 	clk_rate = clk_get_rate(sun4i_pwm->clk);
179 
180 	*bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
181 		  state->enabled &&
182 		  (state->period * clk_rate >= NSEC_PER_SEC) &&
183 		  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
184 		  (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
185 
186 	/* Skip calculation of other parameters if we bypass them */
187 	if (*bypass)
188 		return 0;
189 
190 	if (sun4i_pwm->data->has_prescaler_bypass) {
191 		/* First, test without any prescaler when available */
192 		prescaler = PWM_PRESCAL_MASK;
193 		/*
194 		 * When not using any prescaler, the clock period in nanoseconds
195 		 * is not an integer so round it half up instead of
196 		 * truncating to get less surprising values.
197 		 */
198 		div = clk_rate * state->period + NSEC_PER_SEC / 2;
199 		do_div(div, NSEC_PER_SEC);
200 		if (div - 1 > PWM_PRD_MASK)
201 			prescaler = 0;
202 	}
203 
204 	if (prescaler == 0) {
205 		/* Go up from the first divider */
206 		for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
207 			unsigned int pval = prescaler_table[prescaler];
208 
209 			if (!pval)
210 				continue;
211 
212 			div = clk_rate;
213 			do_div(div, pval);
214 			div = div * state->period;
215 			do_div(div, NSEC_PER_SEC);
216 			if (div - 1 <= PWM_PRD_MASK)
217 				break;
218 		}
219 
220 		if (div - 1 > PWM_PRD_MASK)
221 			return -EINVAL;
222 	}
223 
224 	*prd = div;
225 	div *= state->duty_cycle;
226 	do_div(div, state->period);
227 	*dty = div;
228 	*prsclr = prescaler;
229 
230 	return 0;
231 }
232 
sun4i_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)233 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
234 			   const struct pwm_state *state)
235 {
236 	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
237 	struct pwm_state cstate;
238 	u32 ctrl, duty = 0, period = 0, val;
239 	int ret;
240 	unsigned int delay_us, prescaler = 0;
241 	bool bypass;
242 
243 	pwm_get_state(pwm, &cstate);
244 
245 	if (!cstate.enabled) {
246 		ret = clk_prepare_enable(sun4i_pwm->clk);
247 		if (ret) {
248 			dev_err(chip->dev, "failed to enable PWM clock\n");
249 			return ret;
250 		}
251 	}
252 
253 	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
254 				  &bypass);
255 	if (ret) {
256 		dev_err(chip->dev, "period exceeds the maximum value\n");
257 		if (!cstate.enabled)
258 			clk_disable_unprepare(sun4i_pwm->clk);
259 		return ret;
260 	}
261 
262 	spin_lock(&sun4i_pwm->ctrl_lock);
263 	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
264 
265 	if (sun4i_pwm->data->has_direct_mod_clk_output) {
266 		if (bypass) {
267 			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
268 			/* We can skip other parameter */
269 			sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
270 			spin_unlock(&sun4i_pwm->ctrl_lock);
271 			return 0;
272 		}
273 
274 		ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
275 	}
276 
277 	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
278 		/* Prescaler changed, the clock has to be gated */
279 		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
280 		sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
281 
282 		ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
283 		ctrl |= BIT_CH(prescaler, pwm->hwpwm);
284 	}
285 
286 	val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
287 	sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
288 
289 	if (state->polarity != PWM_POLARITY_NORMAL)
290 		ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
291 	else
292 		ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
293 
294 	ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
295 
296 	if (state->enabled)
297 		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
298 
299 	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
300 
301 	spin_unlock(&sun4i_pwm->ctrl_lock);
302 
303 	if (state->enabled)
304 		return 0;
305 
306 	/* We need a full period to elapse before disabling the channel. */
307 	delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
308 	if ((delay_us / 500) > MAX_UDELAY_MS)
309 		msleep(delay_us / 1000 + 1);
310 	else
311 		usleep_range(delay_us, delay_us * 2);
312 
313 	spin_lock(&sun4i_pwm->ctrl_lock);
314 	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
315 	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
316 	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
317 	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
318 	spin_unlock(&sun4i_pwm->ctrl_lock);
319 
320 	clk_disable_unprepare(sun4i_pwm->clk);
321 
322 	return 0;
323 }
324 
325 static const struct pwm_ops sun4i_pwm_ops = {
326 	.apply = sun4i_pwm_apply,
327 	.get_state = sun4i_pwm_get_state,
328 	.owner = THIS_MODULE,
329 };
330 
331 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
332 	.has_prescaler_bypass = false,
333 	.npwm = 2,
334 };
335 
336 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
337 	.has_prescaler_bypass = true,
338 	.npwm = 2,
339 };
340 
341 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
342 	.has_prescaler_bypass = true,
343 	.npwm = 1,
344 };
345 
346 static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
347 	.has_prescaler_bypass = true,
348 	.has_direct_mod_clk_output = true,
349 	.npwm = 1,
350 };
351 
352 static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
353 	.has_prescaler_bypass = true,
354 	.has_direct_mod_clk_output = true,
355 	.npwm = 2,
356 };
357 
358 static const struct of_device_id sun4i_pwm_dt_ids[] = {
359 	{
360 		.compatible = "allwinner,sun4i-a10-pwm",
361 		.data = &sun4i_pwm_dual_nobypass,
362 	}, {
363 		.compatible = "allwinner,sun5i-a10s-pwm",
364 		.data = &sun4i_pwm_dual_bypass,
365 	}, {
366 		.compatible = "allwinner,sun5i-a13-pwm",
367 		.data = &sun4i_pwm_single_bypass,
368 	}, {
369 		.compatible = "allwinner,sun7i-a20-pwm",
370 		.data = &sun4i_pwm_dual_bypass,
371 	}, {
372 		.compatible = "allwinner,sun8i-h3-pwm",
373 		.data = &sun4i_pwm_single_bypass,
374 	}, {
375 		.compatible = "allwinner,sun50i-a64-pwm",
376 		.data = &sun50i_a64_pwm_data,
377 	}, {
378 		.compatible = "allwinner,sun50i-h6-pwm",
379 		.data = &sun50i_h6_pwm_data,
380 	}, {
381 		/* sentinel */
382 	},
383 };
384 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
385 
sun4i_pwm_probe(struct platform_device * pdev)386 static int sun4i_pwm_probe(struct platform_device *pdev)
387 {
388 	struct sun4i_pwm_chip *sun4ichip;
389 	int ret;
390 
391 	sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL);
392 	if (!sun4ichip)
393 		return -ENOMEM;
394 
395 	sun4ichip->data = of_device_get_match_data(&pdev->dev);
396 	if (!sun4ichip->data)
397 		return -ENODEV;
398 
399 	sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
400 	if (IS_ERR(sun4ichip->base))
401 		return PTR_ERR(sun4ichip->base);
402 
403 	/*
404 	 * All hardware variants need a source clock that is divided and
405 	 * then feeds the counter that defines the output wave form. In the
406 	 * device tree this clock is either unnamed or called "mod".
407 	 * Some variants (e.g. H6) need another clock to access the
408 	 * hardware registers; this is called "bus".
409 	 * So we request "mod" first (and ignore the corner case that a
410 	 * parent provides a "mod" clock while the right one would be the
411 	 * unnamed one of the PWM device) and if this is not found we fall
412 	 * back to the first clock of the PWM.
413 	 */
414 	sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
415 	if (IS_ERR(sun4ichip->clk))
416 		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
417 				     "get mod clock failed\n");
418 
419 	if (!sun4ichip->clk) {
420 		sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
421 		if (IS_ERR(sun4ichip->clk))
422 			return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
423 					     "get unnamed clock failed\n");
424 	}
425 
426 	sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
427 	if (IS_ERR(sun4ichip->bus_clk))
428 		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
429 				     "get bus clock failed\n");
430 
431 	sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
432 	if (IS_ERR(sun4ichip->rst))
433 		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
434 				     "get reset failed\n");
435 
436 	/* Deassert reset */
437 	ret = reset_control_deassert(sun4ichip->rst);
438 	if (ret) {
439 		dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
440 			ERR_PTR(ret));
441 		return ret;
442 	}
443 
444 	/*
445 	 * We're keeping the bus clock on for the sake of simplicity.
446 	 * Actually it only needs to be on for hardware register accesses.
447 	 */
448 	ret = clk_prepare_enable(sun4ichip->bus_clk);
449 	if (ret) {
450 		dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
451 			ERR_PTR(ret));
452 		goto err_bus;
453 	}
454 
455 	sun4ichip->chip.dev = &pdev->dev;
456 	sun4ichip->chip.ops = &sun4i_pwm_ops;
457 	sun4ichip->chip.npwm = sun4ichip->data->npwm;
458 
459 	spin_lock_init(&sun4ichip->ctrl_lock);
460 
461 	ret = pwmchip_add(&sun4ichip->chip);
462 	if (ret < 0) {
463 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
464 		goto err_pwm_add;
465 	}
466 
467 	platform_set_drvdata(pdev, sun4ichip);
468 
469 	return 0;
470 
471 err_pwm_add:
472 	clk_disable_unprepare(sun4ichip->bus_clk);
473 err_bus:
474 	reset_control_assert(sun4ichip->rst);
475 
476 	return ret;
477 }
478 
sun4i_pwm_remove(struct platform_device * pdev)479 static void sun4i_pwm_remove(struct platform_device *pdev)
480 {
481 	struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);
482 
483 	pwmchip_remove(&sun4ichip->chip);
484 
485 	clk_disable_unprepare(sun4ichip->bus_clk);
486 	reset_control_assert(sun4ichip->rst);
487 }
488 
489 static struct platform_driver sun4i_pwm_driver = {
490 	.driver = {
491 		.name = "sun4i-pwm",
492 		.of_match_table = sun4i_pwm_dt_ids,
493 	},
494 	.probe = sun4i_pwm_probe,
495 	.remove_new = sun4i_pwm_remove,
496 };
497 module_platform_driver(sun4i_pwm_driver);
498 
499 MODULE_ALIAS("platform:sun4i-pwm");
500 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
501 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
502 MODULE_LICENSE("GPL v2");
503