1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Free Electrons
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/reset.h>
15
16 #include <drm/drm_device.h>
17 #include <drm/drm_fb_dma_helper.h>
18 #include <drm/drm_fourcc.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_gem_dma_helper.h>
21 #include <drm/drm_plane.h>
22
23 #include "sun4i_drv.h"
24 #include "sun4i_frontend.h"
25
26 static const u32 sun4i_frontend_vert_coef[32] = {
27 0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
28 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
29 0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
30 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
31 0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
32 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
33 0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
34 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
35 };
36
37 static const u32 sun4i_frontend_horz_coef[64] = {
38 0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
39 0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
40 0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
41 0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
42 0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
43 0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
44 0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
45 0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
46 0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
47 0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
48 0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
49 0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
50 0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
51 0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
52 0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
53 0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
54 };
55
56 /*
57 * These coefficients are taken from the A33 BSP from Allwinner.
58 *
59 * The first three values of each row are coded as 13-bit signed fixed-point
60 * numbers, with 10 bits for the fractional part. The fourth value is a
61 * constant coded as a 14-bit signed fixed-point number with 4 bits for the
62 * fractional part.
63 *
64 * The values in table order give the following colorspace translation:
65 * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
66 * R = 1.164 * Y + 1.596 * V - 222
67 * B = 1.164 * Y + 2.018 * U + 276
68 *
69 * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
70 * following the BT601 spec.
71 */
72 const u32 sunxi_bt601_yuv2rgb_coef[12] = {
73 0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
74 0x000004a7, 0x00000000, 0x00000662, 0x00003211,
75 0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
76 };
77 EXPORT_SYMBOL(sunxi_bt601_yuv2rgb_coef);
78
sun4i_frontend_scaler_init(struct sun4i_frontend * frontend)79 static void sun4i_frontend_scaler_init(struct sun4i_frontend *frontend)
80 {
81 int i;
82
83 if (frontend->data->has_coef_access_ctrl)
84 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
85 SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL,
86 SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL);
87
88 for (i = 0; i < 32; i++) {
89 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i),
90 sun4i_frontend_horz_coef[2 * i]);
91 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF0_REG(i),
92 sun4i_frontend_horz_coef[2 * i]);
93 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF1_REG(i),
94 sun4i_frontend_horz_coef[2 * i + 1]);
95 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF1_REG(i),
96 sun4i_frontend_horz_coef[2 * i + 1]);
97 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTCOEF_REG(i),
98 sun4i_frontend_vert_coef[i]);
99 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTCOEF_REG(i),
100 sun4i_frontend_vert_coef[i]);
101 }
102
103 if (frontend->data->has_coef_rdy)
104 regmap_write_bits(frontend->regs,
105 SUN4I_FRONTEND_FRM_CTRL_REG,
106 SUN4I_FRONTEND_FRM_CTRL_COEF_RDY,
107 SUN4I_FRONTEND_FRM_CTRL_COEF_RDY);
108 }
109
sun4i_frontend_init(struct sun4i_frontend * frontend)110 int sun4i_frontend_init(struct sun4i_frontend *frontend)
111 {
112 return pm_runtime_get_sync(frontend->dev);
113 }
114 EXPORT_SYMBOL(sun4i_frontend_init);
115
sun4i_frontend_exit(struct sun4i_frontend * frontend)116 void sun4i_frontend_exit(struct sun4i_frontend *frontend)
117 {
118 pm_runtime_put(frontend->dev);
119 }
120 EXPORT_SYMBOL(sun4i_frontend_exit);
121
sun4i_frontend_format_chroma_requires_swap(uint32_t fmt)122 static bool sun4i_frontend_format_chroma_requires_swap(uint32_t fmt)
123 {
124 switch (fmt) {
125 case DRM_FORMAT_YVU411:
126 case DRM_FORMAT_YVU420:
127 case DRM_FORMAT_YVU422:
128 case DRM_FORMAT_YVU444:
129 return true;
130
131 default:
132 return false;
133 }
134 }
135
sun4i_frontend_format_supports_tiling(uint32_t fmt)136 static bool sun4i_frontend_format_supports_tiling(uint32_t fmt)
137 {
138 switch (fmt) {
139 case DRM_FORMAT_NV12:
140 case DRM_FORMAT_NV16:
141 case DRM_FORMAT_NV21:
142 case DRM_FORMAT_NV61:
143 case DRM_FORMAT_YUV411:
144 case DRM_FORMAT_YUV420:
145 case DRM_FORMAT_YUV422:
146 case DRM_FORMAT_YVU420:
147 case DRM_FORMAT_YVU422:
148 case DRM_FORMAT_YVU411:
149 return true;
150
151 default:
152 return false;
153 }
154 }
155
sun4i_frontend_update_buffer(struct sun4i_frontend * frontend,struct drm_plane * plane)156 void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend,
157 struct drm_plane *plane)
158 {
159 struct drm_plane_state *state = plane->state;
160 struct drm_framebuffer *fb = state->fb;
161 unsigned int strides[3] = {};
162
163 dma_addr_t dma_addr;
164 bool swap;
165
166 if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) {
167 unsigned int width = state->src_w >> 16;
168 unsigned int offset;
169
170 strides[0] = SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[0]);
171
172 /*
173 * The X1 offset is the offset to the bottom-right point in the
174 * end tile, which is the final pixel (at offset width - 1)
175 * within the end tile (with a 32-byte mask).
176 */
177 offset = (width - 1) & (32 - 1);
178
179 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF0_REG,
180 SUN4I_FRONTEND_TB_OFF_X1(offset));
181
182 if (fb->format->num_planes > 1) {
183 strides[1] =
184 SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[1]);
185
186 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF1_REG,
187 SUN4I_FRONTEND_TB_OFF_X1(offset));
188 }
189
190 if (fb->format->num_planes > 2) {
191 strides[2] =
192 SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[2]);
193
194 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF2_REG,
195 SUN4I_FRONTEND_TB_OFF_X1(offset));
196 }
197 } else {
198 strides[0] = fb->pitches[0];
199
200 if (fb->format->num_planes > 1)
201 strides[1] = fb->pitches[1];
202
203 if (fb->format->num_planes > 2)
204 strides[2] = fb->pitches[2];
205 }
206
207 /* Set the line width */
208 DRM_DEBUG_DRIVER("Frontend stride: %d bytes\n", fb->pitches[0]);
209 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD0_REG,
210 strides[0]);
211
212 if (fb->format->num_planes > 1)
213 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD1_REG,
214 strides[1]);
215
216 if (fb->format->num_planes > 2)
217 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD2_REG,
218 strides[2]);
219
220 /* Some planar formats require chroma channel swapping by hand. */
221 swap = sun4i_frontend_format_chroma_requires_swap(fb->format->format);
222
223 /* Set the physical address of the buffer in memory */
224 dma_addr = drm_fb_dma_get_gem_addr(fb, state, 0);
225 DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &dma_addr);
226 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, dma_addr);
227
228 if (fb->format->num_planes > 1) {
229 dma_addr = drm_fb_dma_get_gem_addr(fb, state, swap ? 2 : 1);
230 DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n",
231 &dma_addr);
232 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG,
233 dma_addr);
234 }
235
236 if (fb->format->num_planes > 2) {
237 dma_addr = drm_fb_dma_get_gem_addr(fb, state, swap ? 1 : 2);
238 DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n",
239 &dma_addr);
240 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG,
241 dma_addr);
242 }
243 }
244 EXPORT_SYMBOL(sun4i_frontend_update_buffer);
245
246 static int
sun4i_frontend_drm_format_to_input_fmt(const struct drm_format_info * format,u32 * val)247 sun4i_frontend_drm_format_to_input_fmt(const struct drm_format_info *format,
248 u32 *val)
249 {
250 if (!format->is_yuv)
251 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB;
252 else if (drm_format_info_is_yuv_sampling_411(format))
253 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411;
254 else if (drm_format_info_is_yuv_sampling_420(format))
255 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420;
256 else if (drm_format_info_is_yuv_sampling_422(format))
257 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422;
258 else if (drm_format_info_is_yuv_sampling_444(format))
259 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444;
260 else
261 return -EINVAL;
262
263 return 0;
264 }
265
266 static int
sun4i_frontend_drm_format_to_input_mode(const struct drm_format_info * format,uint64_t modifier,u32 * val)267 sun4i_frontend_drm_format_to_input_mode(const struct drm_format_info *format,
268 uint64_t modifier, u32 *val)
269 {
270 bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED);
271
272 switch (format->num_planes) {
273 case 1:
274 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED;
275 return 0;
276
277 case 2:
278 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR
279 : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_SEMIPLANAR;
280 return 0;
281
282 case 3:
283 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR
284 : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR;
285 return 0;
286
287 default:
288 return -EINVAL;
289 }
290 }
291
292 static int
sun4i_frontend_drm_format_to_input_sequence(const struct drm_format_info * format,u32 * val)293 sun4i_frontend_drm_format_to_input_sequence(const struct drm_format_info *format,
294 u32 *val)
295 {
296 /* Planar formats have an explicit input sequence. */
297 if (drm_format_info_is_yuv_planar(format)) {
298 *val = 0;
299 return 0;
300 }
301
302 switch (format->format) {
303 case DRM_FORMAT_BGRX8888:
304 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX;
305 return 0;
306
307 case DRM_FORMAT_NV12:
308 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
309 return 0;
310
311 case DRM_FORMAT_NV16:
312 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
313 return 0;
314
315 case DRM_FORMAT_NV21:
316 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
317 return 0;
318
319 case DRM_FORMAT_NV61:
320 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
321 return 0;
322
323 case DRM_FORMAT_UYVY:
324 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY;
325 return 0;
326
327 case DRM_FORMAT_VYUY:
328 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY;
329 return 0;
330
331 case DRM_FORMAT_XRGB8888:
332 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB;
333 return 0;
334
335 case DRM_FORMAT_YUYV:
336 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV;
337 return 0;
338
339 case DRM_FORMAT_YVYU:
340 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU;
341 return 0;
342
343 default:
344 return -EINVAL;
345 }
346 }
347
sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt,u32 * val)348 static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val)
349 {
350 switch (fmt) {
351 case DRM_FORMAT_BGRX8888:
352 *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_BGRX8888;
353 return 0;
354
355 case DRM_FORMAT_XRGB8888:
356 *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_XRGB8888;
357 return 0;
358
359 default:
360 return -EINVAL;
361 }
362 }
363
364 static const uint32_t sun4i_frontend_formats[] = {
365 DRM_FORMAT_BGRX8888,
366 DRM_FORMAT_NV12,
367 DRM_FORMAT_NV16,
368 DRM_FORMAT_NV21,
369 DRM_FORMAT_NV61,
370 DRM_FORMAT_UYVY,
371 DRM_FORMAT_VYUY,
372 DRM_FORMAT_XRGB8888,
373 DRM_FORMAT_YUV411,
374 DRM_FORMAT_YUV420,
375 DRM_FORMAT_YUV422,
376 DRM_FORMAT_YUV444,
377 DRM_FORMAT_YUYV,
378 DRM_FORMAT_YVU411,
379 DRM_FORMAT_YVU420,
380 DRM_FORMAT_YVU422,
381 DRM_FORMAT_YVU444,
382 DRM_FORMAT_YVYU,
383 };
384
sun4i_frontend_format_is_supported(uint32_t fmt,uint64_t modifier)385 bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier)
386 {
387 unsigned int i;
388
389 if (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED)
390 return sun4i_frontend_format_supports_tiling(fmt);
391 else if (modifier != DRM_FORMAT_MOD_LINEAR)
392 return false;
393
394 for (i = 0; i < ARRAY_SIZE(sun4i_frontend_formats); i++)
395 if (sun4i_frontend_formats[i] == fmt)
396 return true;
397
398 return false;
399 }
400 EXPORT_SYMBOL(sun4i_frontend_format_is_supported);
401
sun4i_frontend_update_formats(struct sun4i_frontend * frontend,struct drm_plane * plane,uint32_t out_fmt)402 int sun4i_frontend_update_formats(struct sun4i_frontend *frontend,
403 struct drm_plane *plane, uint32_t out_fmt)
404 {
405 struct drm_plane_state *state = plane->state;
406 struct drm_framebuffer *fb = state->fb;
407 const struct drm_format_info *format = fb->format;
408 uint64_t modifier = fb->modifier;
409 unsigned int ch1_phase_idx;
410 u32 out_fmt_val;
411 u32 in_fmt_val, in_mod_val, in_ps_val;
412 unsigned int i;
413 u32 bypass;
414 int ret;
415
416 ret = sun4i_frontend_drm_format_to_input_fmt(format, &in_fmt_val);
417 if (ret) {
418 DRM_DEBUG_DRIVER("Invalid input format\n");
419 return ret;
420 }
421
422 ret = sun4i_frontend_drm_format_to_input_mode(format, modifier,
423 &in_mod_val);
424 if (ret) {
425 DRM_DEBUG_DRIVER("Invalid input mode\n");
426 return ret;
427 }
428
429 ret = sun4i_frontend_drm_format_to_input_sequence(format, &in_ps_val);
430 if (ret) {
431 DRM_DEBUG_DRIVER("Invalid pixel sequence\n");
432 return ret;
433 }
434
435 ret = sun4i_frontend_drm_format_to_output_fmt(out_fmt, &out_fmt_val);
436 if (ret) {
437 DRM_DEBUG_DRIVER("Invalid output format\n");
438 return ret;
439 }
440
441 /*
442 * I have no idea what this does exactly, but it seems to be
443 * related to the scaler FIR filter phase parameters.
444 */
445 ch1_phase_idx = (format->num_planes > 1) ? 1 : 0;
446 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG,
447 frontend->data->ch_phase[0]);
448 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG,
449 frontend->data->ch_phase[ch1_phase_idx]);
450 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG,
451 frontend->data->ch_phase[0]);
452 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG,
453 frontend->data->ch_phase[ch1_phase_idx]);
454 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG,
455 frontend->data->ch_phase[0]);
456 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG,
457 frontend->data->ch_phase[ch1_phase_idx]);
458
459 /*
460 * Checking the input format is sufficient since we currently only
461 * support RGB output formats to the backend. If YUV output formats
462 * ever get supported, an YUV input and output would require bypassing
463 * the CSC engine too.
464 */
465 if (format->is_yuv) {
466 /* Setup the CSC engine for YUV to RGB conversion. */
467 bypass = 0;
468
469 for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
470 regmap_write(frontend->regs,
471 SUN4I_FRONTEND_CSC_COEF_REG(i),
472 sunxi_bt601_yuv2rgb_coef[i]);
473 } else {
474 bypass = SUN4I_FRONTEND_BYPASS_CSC_EN;
475 }
476
477 regmap_update_bits(frontend->regs, SUN4I_FRONTEND_BYPASS_REG,
478 SUN4I_FRONTEND_BYPASS_CSC_EN, bypass);
479
480 regmap_write(frontend->regs, SUN4I_FRONTEND_INPUT_FMT_REG,
481 in_mod_val | in_fmt_val | in_ps_val);
482
483 /*
484 * TODO: It look like the A31 and A80 at least will need the
485 * bit 7 (ALPHA_EN) enabled when using a format with alpha (so
486 * ARGB8888).
487 */
488 regmap_write(frontend->regs, SUN4I_FRONTEND_OUTPUT_FMT_REG,
489 out_fmt_val);
490
491 return 0;
492 }
493 EXPORT_SYMBOL(sun4i_frontend_update_formats);
494
sun4i_frontend_update_coord(struct sun4i_frontend * frontend,struct drm_plane * plane)495 void sun4i_frontend_update_coord(struct sun4i_frontend *frontend,
496 struct drm_plane *plane)
497 {
498 struct drm_plane_state *state = plane->state;
499 struct drm_framebuffer *fb = state->fb;
500 uint32_t luma_width, luma_height;
501 uint32_t chroma_width, chroma_height;
502
503 /* Set height and width */
504 DRM_DEBUG_DRIVER("Frontend size W: %u H: %u\n",
505 state->crtc_w, state->crtc_h);
506
507 luma_width = state->src_w >> 16;
508 luma_height = state->src_h >> 16;
509
510 chroma_width = DIV_ROUND_UP(luma_width, fb->format->hsub);
511 chroma_height = DIV_ROUND_UP(luma_height, fb->format->vsub);
512
513 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_INSIZE_REG,
514 SUN4I_FRONTEND_INSIZE(luma_height, luma_width));
515 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_INSIZE_REG,
516 SUN4I_FRONTEND_INSIZE(chroma_height, chroma_width));
517
518 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_OUTSIZE_REG,
519 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
520 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_OUTSIZE_REG,
521 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
522
523 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZFACT_REG,
524 (luma_width << 16) / state->crtc_w);
525 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZFACT_REG,
526 (chroma_width << 16) / state->crtc_w);
527
528 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTFACT_REG,
529 (luma_height << 16) / state->crtc_h);
530 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTFACT_REG,
531 (chroma_height << 16) / state->crtc_h);
532
533 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
534 SUN4I_FRONTEND_FRM_CTRL_REG_RDY,
535 SUN4I_FRONTEND_FRM_CTRL_REG_RDY);
536 }
537 EXPORT_SYMBOL(sun4i_frontend_update_coord);
538
sun4i_frontend_enable(struct sun4i_frontend * frontend)539 int sun4i_frontend_enable(struct sun4i_frontend *frontend)
540 {
541 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
542 SUN4I_FRONTEND_FRM_CTRL_FRM_START,
543 SUN4I_FRONTEND_FRM_CTRL_FRM_START);
544
545 return 0;
546 }
547 EXPORT_SYMBOL(sun4i_frontend_enable);
548
549 static const struct regmap_config sun4i_frontend_regmap_config = {
550 .reg_bits = 32,
551 .val_bits = 32,
552 .reg_stride = 4,
553 .max_register = 0x0a14,
554 };
555
sun4i_frontend_bind(struct device * dev,struct device * master,void * data)556 static int sun4i_frontend_bind(struct device *dev, struct device *master,
557 void *data)
558 {
559 struct platform_device *pdev = to_platform_device(dev);
560 struct sun4i_frontend *frontend;
561 struct drm_device *drm = data;
562 struct sun4i_drv *drv = drm->dev_private;
563 void __iomem *regs;
564
565 frontend = devm_kzalloc(dev, sizeof(*frontend), GFP_KERNEL);
566 if (!frontend)
567 return -ENOMEM;
568
569 dev_set_drvdata(dev, frontend);
570 frontend->dev = dev;
571 frontend->node = dev->of_node;
572
573 frontend->data = of_device_get_match_data(dev);
574 if (!frontend->data)
575 return -ENODEV;
576
577 regs = devm_platform_ioremap_resource(pdev, 0);
578 if (IS_ERR(regs))
579 return PTR_ERR(regs);
580
581 frontend->regs = devm_regmap_init_mmio(dev, regs,
582 &sun4i_frontend_regmap_config);
583 if (IS_ERR(frontend->regs)) {
584 dev_err(dev, "Couldn't create the frontend regmap\n");
585 return PTR_ERR(frontend->regs);
586 }
587
588 frontend->reset = devm_reset_control_get(dev, NULL);
589 if (IS_ERR(frontend->reset)) {
590 dev_err(dev, "Couldn't get our reset line\n");
591 return PTR_ERR(frontend->reset);
592 }
593
594 frontend->bus_clk = devm_clk_get(dev, "ahb");
595 if (IS_ERR(frontend->bus_clk)) {
596 dev_err(dev, "Couldn't get our bus clock\n");
597 return PTR_ERR(frontend->bus_clk);
598 }
599
600 frontend->mod_clk = devm_clk_get(dev, "mod");
601 if (IS_ERR(frontend->mod_clk)) {
602 dev_err(dev, "Couldn't get our mod clock\n");
603 return PTR_ERR(frontend->mod_clk);
604 }
605
606 frontend->ram_clk = devm_clk_get(dev, "ram");
607 if (IS_ERR(frontend->ram_clk)) {
608 dev_err(dev, "Couldn't get our ram clock\n");
609 return PTR_ERR(frontend->ram_clk);
610 }
611
612 list_add_tail(&frontend->list, &drv->frontend_list);
613 pm_runtime_enable(dev);
614
615 return 0;
616 }
617
sun4i_frontend_unbind(struct device * dev,struct device * master,void * data)618 static void sun4i_frontend_unbind(struct device *dev, struct device *master,
619 void *data)
620 {
621 struct sun4i_frontend *frontend = dev_get_drvdata(dev);
622
623 list_del(&frontend->list);
624 pm_runtime_force_suspend(dev);
625 }
626
627 static const struct component_ops sun4i_frontend_ops = {
628 .bind = sun4i_frontend_bind,
629 .unbind = sun4i_frontend_unbind,
630 };
631
sun4i_frontend_probe(struct platform_device * pdev)632 static int sun4i_frontend_probe(struct platform_device *pdev)
633 {
634 return component_add(&pdev->dev, &sun4i_frontend_ops);
635 }
636
sun4i_frontend_remove(struct platform_device * pdev)637 static void sun4i_frontend_remove(struct platform_device *pdev)
638 {
639 component_del(&pdev->dev, &sun4i_frontend_ops);
640 }
641
sun4i_frontend_runtime_resume(struct device * dev)642 static int sun4i_frontend_runtime_resume(struct device *dev)
643 {
644 struct sun4i_frontend *frontend = dev_get_drvdata(dev);
645 int ret;
646
647 clk_set_rate(frontend->mod_clk, 300000000);
648
649 clk_prepare_enable(frontend->bus_clk);
650 clk_prepare_enable(frontend->mod_clk);
651 clk_prepare_enable(frontend->ram_clk);
652
653 ret = reset_control_reset(frontend->reset);
654 if (ret) {
655 dev_err(dev, "Couldn't reset our device\n");
656 return ret;
657 }
658
659 regmap_update_bits(frontend->regs, SUN4I_FRONTEND_EN_REG,
660 SUN4I_FRONTEND_EN_EN,
661 SUN4I_FRONTEND_EN_EN);
662
663 sun4i_frontend_scaler_init(frontend);
664
665 return 0;
666 }
667
sun4i_frontend_runtime_suspend(struct device * dev)668 static int sun4i_frontend_runtime_suspend(struct device *dev)
669 {
670 struct sun4i_frontend *frontend = dev_get_drvdata(dev);
671
672 clk_disable_unprepare(frontend->ram_clk);
673 clk_disable_unprepare(frontend->mod_clk);
674 clk_disable_unprepare(frontend->bus_clk);
675
676 reset_control_assert(frontend->reset);
677
678 return 0;
679 }
680
681 static const struct dev_pm_ops sun4i_frontend_pm_ops = {
682 .runtime_resume = sun4i_frontend_runtime_resume,
683 .runtime_suspend = sun4i_frontend_runtime_suspend,
684 };
685
686 static const struct sun4i_frontend_data sun4i_a10_frontend = {
687 .ch_phase = { 0x000, 0xfc000 },
688 .has_coef_rdy = true,
689 };
690
691 static const struct sun4i_frontend_data sun8i_a33_frontend = {
692 .ch_phase = { 0x400, 0xfc400 },
693 .has_coef_access_ctrl = true,
694 };
695
696 const struct of_device_id sun4i_frontend_of_table[] = {
697 {
698 .compatible = "allwinner,sun4i-a10-display-frontend",
699 .data = &sun4i_a10_frontend
700 },
701 {
702 .compatible = "allwinner,sun7i-a20-display-frontend",
703 .data = &sun4i_a10_frontend
704 },
705 {
706 .compatible = "allwinner,sun8i-a23-display-frontend",
707 .data = &sun8i_a33_frontend
708 },
709 {
710 .compatible = "allwinner,sun8i-a33-display-frontend",
711 .data = &sun8i_a33_frontend
712 },
713 { }
714 };
715 EXPORT_SYMBOL(sun4i_frontend_of_table);
716 MODULE_DEVICE_TABLE(of, sun4i_frontend_of_table);
717
718 static struct platform_driver sun4i_frontend_driver = {
719 .probe = sun4i_frontend_probe,
720 .remove_new = sun4i_frontend_remove,
721 .driver = {
722 .name = "sun4i-frontend",
723 .of_match_table = sun4i_frontend_of_table,
724 .pm = &sun4i_frontend_pm_ops,
725 },
726 };
727 module_platform_driver(sun4i_frontend_driver);
728
729 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
730 MODULE_DESCRIPTION("Allwinner A10 Display Engine Frontend Driver");
731 MODULE_LICENSE("GPL");
732