1 /*
2  * Allwinner A10 SoCs pinctrl driver.
3  *
4  * Copyright (C) 2014 Maxime Ripard
5  *
6  * Maxime Ripard <maxime.ripard@free-electrons.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12 
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/of.h>
16 #include <linux/pinctrl/pinctrl.h>
17 
18 #include "pinctrl-sunxi.h"
19 
20 static const struct sunxi_desc_pin sun4i_a10_pins[] = {
21 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
22 		  SUNXI_FUNCTION(0x0, "gpio_in"),
23 		  SUNXI_FUNCTION(0x1, "gpio_out"),
24 		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD3 */
25 		  SUNXI_FUNCTION(0x3, "spi1"),		/* CS0 */
26 		  SUNXI_FUNCTION(0x4, "uart2"),		/* RTS */
27 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GRXD3 */
28 					 PINCTRL_SUN7I_A20 |
29 					 PINCTRL_SUN8I_R40)),
30 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
31 		  SUNXI_FUNCTION(0x0, "gpio_in"),
32 		  SUNXI_FUNCTION(0x1, "gpio_out"),
33 		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD2 */
34 		  SUNXI_FUNCTION(0x3, "spi1"),		/* CLK */
35 		  SUNXI_FUNCTION(0x4, "uart2"),		/* CTS */
36 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GRXD2 */
37 					 PINCTRL_SUN7I_A20 |
38 					 PINCTRL_SUN8I_R40)),
39 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
40 		  SUNXI_FUNCTION(0x0, "gpio_in"),
41 		  SUNXI_FUNCTION(0x1, "gpio_out"),
42 		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD1 */
43 		  SUNXI_FUNCTION(0x3, "spi1"),		/* MOSI */
44 		  SUNXI_FUNCTION(0x4, "uart2"),		/* TX */
45 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GRXD1 */
46 					 PINCTRL_SUN7I_A20 |
47 					 PINCTRL_SUN8I_R40)),
48 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
49 		  SUNXI_FUNCTION(0x0, "gpio_in"),
50 		  SUNXI_FUNCTION(0x1, "gpio_out"),
51 		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXD0 */
52 		  SUNXI_FUNCTION(0x3, "spi1"),		/* MISO */
53 		  SUNXI_FUNCTION(0x4, "uart2"),		/* RX */
54 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GRXD0 */
55 					 PINCTRL_SUN7I_A20 |
56 					 PINCTRL_SUN8I_R40)),
57 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
58 		  SUNXI_FUNCTION(0x0, "gpio_in"),
59 		  SUNXI_FUNCTION(0x1, "gpio_out"),
60 		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD3 */
61 		  SUNXI_FUNCTION(0x3, "spi1"),		/* CS1 */
62 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GTXD3 */
63 					 PINCTRL_SUN7I_A20 |
64 					 PINCTRL_SUN8I_R40)),
65 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
66 		  SUNXI_FUNCTION(0x0, "gpio_in"),
67 		  SUNXI_FUNCTION(0x1, "gpio_out"),
68 		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD2 */
69 		  SUNXI_FUNCTION(0x3, "spi3"),		/* CS0 */
70 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GTXD2 */
71 					 PINCTRL_SUN7I_A20 |
72 					 PINCTRL_SUN8I_R40)),
73 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
74 		  SUNXI_FUNCTION(0x0, "gpio_in"),
75 		  SUNXI_FUNCTION(0x1, "gpio_out"),
76 		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD1 */
77 		  SUNXI_FUNCTION(0x3, "spi3"),		/* CLK */
78 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GTXD1 */
79 					 PINCTRL_SUN7I_A20 |
80 					 PINCTRL_SUN8I_R40)),
81 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
82 		  SUNXI_FUNCTION(0x0, "gpio_in"),
83 		  SUNXI_FUNCTION(0x1, "gpio_out"),
84 		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXD0 */
85 		  SUNXI_FUNCTION(0x3, "spi3"),		/* MOSI */
86 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GTXD0 */
87 					 PINCTRL_SUN7I_A20 |
88 					 PINCTRL_SUN8I_R40)),
89 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
90 		  SUNXI_FUNCTION(0x0, "gpio_in"),
91 		  SUNXI_FUNCTION(0x1, "gpio_out"),
92 		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXCK */
93 		  SUNXI_FUNCTION(0x3, "spi3"),		/* MISO */
94 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GRXCK */
95 					 PINCTRL_SUN7I_A20 |
96 					 PINCTRL_SUN8I_R40)),
97 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
98 		  SUNXI_FUNCTION(0x0, "gpio_in"),
99 		  SUNXI_FUNCTION(0x1, "gpio_out"),
100 		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXERR */
101 		  SUNXI_FUNCTION(0x3, "spi3"),		/* CS1 */
102 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GNULL / ERXERR */
103 					 PINCTRL_SUN7I_A20 |
104 					 PINCTRL_SUN8I_R40),
105 		  SUNXI_FUNCTION_VARIANT(0x6, "i2s1",	/* MCLK */
106 					 PINCTRL_SUN7I_A20 |
107 					 PINCTRL_SUN8I_R40)),
108 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
109 		  SUNXI_FUNCTION(0x0, "gpio_in"),
110 		  SUNXI_FUNCTION(0x1, "gpio_out"),
111 		  SUNXI_FUNCTION(0x2, "emac"),		/* ERXDV */
112 		  SUNXI_FUNCTION(0x4, "uart1"),		/* TX */
113 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GRXDV */
114 					 PINCTRL_SUN7I_A20 |
115 					 PINCTRL_SUN8I_R40)),
116 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
117 		  SUNXI_FUNCTION(0x0, "gpio_in"),
118 		  SUNXI_FUNCTION(0x1, "gpio_out"),
119 		  SUNXI_FUNCTION(0x2, "emac"),		/* EMDC */
120 		  SUNXI_FUNCTION(0x4, "uart1"),		/* RX */
121 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* EMDC */
122 					 PINCTRL_SUN7I_A20 |
123 					 PINCTRL_SUN8I_R40)),
124 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
125 		  SUNXI_FUNCTION(0x0, "gpio_in"),
126 		  SUNXI_FUNCTION(0x1, "gpio_out"),
127 		  SUNXI_FUNCTION(0x2, "emac"),		/* EMDIO */
128 		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
129 		  SUNXI_FUNCTION(0x4, "uart1"),		/* RTS */
130 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* EMDIO */
131 					 PINCTRL_SUN7I_A20 |
132 					 PINCTRL_SUN8I_R40)),
133 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
134 		  SUNXI_FUNCTION(0x0, "gpio_in"),
135 		  SUNXI_FUNCTION(0x1, "gpio_out"),
136 		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXEN */
137 		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
138 		  SUNXI_FUNCTION(0x4, "uart1"),		/* CTS */
139 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GTXCTL / ETXEN */
140 					 PINCTRL_SUN7I_A20 |
141 					 PINCTRL_SUN8I_R40)),
142 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
143 		  SUNXI_FUNCTION(0x0, "gpio_in"),
144 		  SUNXI_FUNCTION(0x1, "gpio_out"),
145 		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXCK */
146 		  SUNXI_FUNCTION(0x3, "uart7"),		/* TX */
147 		  SUNXI_FUNCTION(0x4, "uart1"),		/* DTR */
148 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GNULL / ETXCK */
149 					 PINCTRL_SUN7I_A20 |
150 					 PINCTRL_SUN8I_R40),
151 		  SUNXI_FUNCTION_VARIANT(0x6, "i2s1",	/* BCLK */
152 					 PINCTRL_SUN7I_A20 |
153 					 PINCTRL_SUN8I_R40)),
154 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
155 		  SUNXI_FUNCTION(0x0, "gpio_in"),
156 		  SUNXI_FUNCTION(0x1, "gpio_out"),
157 		  SUNXI_FUNCTION(0x2, "emac"),		/* ECRS */
158 		  SUNXI_FUNCTION(0x3, "uart7"),		/* RX */
159 		  SUNXI_FUNCTION(0x4, "uart1"),		/* DSR */
160 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GTXCK / ECRS */
161 					 PINCTRL_SUN7I_A20 |
162 					 PINCTRL_SUN8I_R40),
163 		  SUNXI_FUNCTION_VARIANT(0x6, "i2s1",	/* LRCK */
164 					 PINCTRL_SUN7I_A20 |
165 					 PINCTRL_SUN8I_R40)),
166 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
167 		  SUNXI_FUNCTION(0x0, "gpio_in"),
168 		  SUNXI_FUNCTION(0x1, "gpio_out"),
169 		  SUNXI_FUNCTION(0x2, "emac"),		/* ECOL */
170 		  SUNXI_FUNCTION(0x3, "can"),		/* TX */
171 		  SUNXI_FUNCTION(0x4, "uart1"),		/* DCD */
172 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GCLKIN / ECOL */
173 					 PINCTRL_SUN7I_A20 |
174 					 PINCTRL_SUN8I_R40),
175 		  SUNXI_FUNCTION_VARIANT(0x6, "i2s1",	/* DO */
176 					 PINCTRL_SUN7I_A20 |
177 					 PINCTRL_SUN8I_R40)),
178 	SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
179 		  SUNXI_FUNCTION(0x0, "gpio_in"),
180 		  SUNXI_FUNCTION(0x1, "gpio_out"),
181 		  SUNXI_FUNCTION(0x2, "emac"),		/* ETXERR */
182 		  SUNXI_FUNCTION(0x3, "can"),		/* RX */
183 		  SUNXI_FUNCTION(0x4, "uart1"),		/* RING */
184 		  SUNXI_FUNCTION_VARIANT(0x5, "gmac",	/* GNULL / ETXERR */
185 					 PINCTRL_SUN7I_A20 |
186 					 PINCTRL_SUN8I_R40),
187 		  SUNXI_FUNCTION_VARIANT(0x6, "i2s1",	/* DI */
188 					 PINCTRL_SUN7I_A20 |
189 					 PINCTRL_SUN8I_R40)),
190 	/* Hole */
191 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
192 		  SUNXI_FUNCTION(0x0, "gpio_in"),
193 		  SUNXI_FUNCTION(0x1, "gpio_out"),
194 		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SCK */
195 		  SUNXI_FUNCTION_VARIANT(0x3, "pll_lock_dbg",
196 					 PINCTRL_SUN8I_R40)),
197 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
198 		  SUNXI_FUNCTION(0x0, "gpio_in"),
199 		  SUNXI_FUNCTION(0x1, "gpio_out"),
200 		  SUNXI_FUNCTION(0x2, "i2c0")),		/* SDA */
201 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
202 		  SUNXI_FUNCTION(0x0, "gpio_in"),
203 		  SUNXI_FUNCTION(0x1, "gpio_out"),
204 		  SUNXI_FUNCTION_VARIANT(0x2, "pwm",	/* PWM0 */
205 					 PINCTRL_SUN4I_A10 |
206 					 PINCTRL_SUN7I_A20),
207 		  SUNXI_FUNCTION_VARIANT(0x3, "pwm",	/* PWM0 */
208 					 PINCTRL_SUN8I_R40)),
209 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
210 		  SUNXI_FUNCTION(0x0, "gpio_in"),
211 		  SUNXI_FUNCTION(0x1, "gpio_out"),
212 		  SUNXI_FUNCTION_VARIANT(0x2, "ir0",	/* TX */
213 					 PINCTRL_SUN4I_A10 |
214 					 PINCTRL_SUN7I_A20),
215 		  SUNXI_FUNCTION_VARIANT(0x3, "pwm",	/* PWM1 */
216 					 PINCTRL_SUN8I_R40),
217 		/*
218 		 * The SPDIF block is not referenced at all in the A10 user
219 		 * manual. However it is described in the code leaked and the
220 		 * pin descriptions are declared in the A20 user manual which
221 		 * is pin compatible with this device.
222 		 */
223 		  SUNXI_FUNCTION(0x4, "spdif")),        /* SPDIF MCLK */
224 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
225 		  SUNXI_FUNCTION(0x0, "gpio_in"),
226 		  SUNXI_FUNCTION(0x1, "gpio_out"),
227 		  SUNXI_FUNCTION(0x2, "ir0")),		/* RX */
228 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
229 		  SUNXI_FUNCTION(0x0, "gpio_in"),
230 		  SUNXI_FUNCTION(0x1, "gpio_out"),
231 		  /*
232 		   * On A10 there's only one I2S controller and the pin group
233 		   * is simply named "i2s". On A20 there's two and thus it's
234 		   * renamed to "i2s0". Deal with these name here, in order
235 		   * to satisfy existing device trees.
236 		   */
237 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* MCLK */
238 					 PINCTRL_SUN4I_A10),
239 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* MCLK */
240 					 PINCTRL_SUN7I_A20 |
241 					 PINCTRL_SUN8I_R40),
242 		  SUNXI_FUNCTION(0x3, "ac97")),		/* MCLK */
243 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
244 		  SUNXI_FUNCTION(0x0, "gpio_in"),
245 		  SUNXI_FUNCTION(0x1, "gpio_out"),
246 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* BCLK */
247 					 PINCTRL_SUN4I_A10),
248 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* BCLK */
249 					 PINCTRL_SUN7I_A20 |
250 					 PINCTRL_SUN8I_R40),
251 		  SUNXI_FUNCTION(0x3, "ac97")),		/* BCLK */
252 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
253 		  SUNXI_FUNCTION(0x0, "gpio_in"),
254 		  SUNXI_FUNCTION(0x1, "gpio_out"),
255 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* LRCK */
256 					 PINCTRL_SUN4I_A10),
257 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* LRCK */
258 					 PINCTRL_SUN7I_A20 |
259 					 PINCTRL_SUN8I_R40),
260 		  SUNXI_FUNCTION(0x3, "ac97")),		/* SYNC */
261 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
262 		  SUNXI_FUNCTION(0x0, "gpio_in"),
263 		  SUNXI_FUNCTION(0x1, "gpio_out"),
264 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* DO0 */
265 					 PINCTRL_SUN4I_A10),
266 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* DO0 */
267 					 PINCTRL_SUN7I_A20 |
268 					 PINCTRL_SUN8I_R40),
269 		  SUNXI_FUNCTION(0x3, "ac97")),		/* DO */
270 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
271 		  SUNXI_FUNCTION(0x0, "gpio_in"),
272 		  SUNXI_FUNCTION(0x1, "gpio_out"),
273 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* DO1 */
274 					 PINCTRL_SUN4I_A10),
275 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* DO1 */
276 					 PINCTRL_SUN7I_A20 |
277 					 PINCTRL_SUN8I_R40),
278 		  SUNXI_FUNCTION_VARIANT(0x4, "pwm",	/* PWM6 */
279 					 PINCTRL_SUN8I_R40)),
280 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
281 		  SUNXI_FUNCTION(0x0, "gpio_in"),
282 		  SUNXI_FUNCTION(0x1, "gpio_out"),
283 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* DO2 */
284 					 PINCTRL_SUN4I_A10),
285 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* DO2 */
286 					 PINCTRL_SUN7I_A20 |
287 					 PINCTRL_SUN8I_R40),
288 		  SUNXI_FUNCTION_VARIANT(0x4, "pwm",	/* PWM7 */
289 					 PINCTRL_SUN8I_R40)),
290 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
291 		  SUNXI_FUNCTION(0x0, "gpio_in"),
292 		  SUNXI_FUNCTION(0x1, "gpio_out"),
293 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* DO3 */
294 					 PINCTRL_SUN4I_A10),
295 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* DO3 */
296 					 PINCTRL_SUN7I_A20 |
297 					 PINCTRL_SUN8I_R40)),
298 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
299 		  SUNXI_FUNCTION(0x0, "gpio_in"),
300 		  SUNXI_FUNCTION(0x1, "gpio_out"),
301 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s",	/* DI */
302 					 PINCTRL_SUN4I_A10),
303 		  SUNXI_FUNCTION_VARIANT(0x2, "i2s0",	/* DI */
304 					 PINCTRL_SUN7I_A20 |
305 					 PINCTRL_SUN8I_R40),
306 		  SUNXI_FUNCTION(0x3, "ac97"),		/* DI */
307 		/* Undocumented mux function on A10 - See SPDIF MCLK above */
308 		  SUNXI_FUNCTION_VARIANT(0x4, "spdif",	/* SPDIF IN */
309 					 PINCTRL_SUN4I_A10 |
310 					 PINCTRL_SUN7I_A20)),
311 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
312 		  SUNXI_FUNCTION(0x0, "gpio_in"),
313 		  SUNXI_FUNCTION(0x1, "gpio_out"),
314 		  SUNXI_FUNCTION(0x2, "spi2"),		/* CS1 */
315 		/* Undocumented mux function on A10 - See SPDIF MCLK above */
316 		  SUNXI_FUNCTION(0x4, "spdif")),        /* SPDIF OUT */
317 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
318 		  SUNXI_FUNCTION(0x0, "gpio_in"),
319 		  SUNXI_FUNCTION(0x1, "gpio_out"),
320 		  SUNXI_FUNCTION(0x2, "spi2"),		/* CS0 */
321 		  SUNXI_FUNCTION(0x3, "jtag")),		/* MS0 */
322 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
323 		  SUNXI_FUNCTION(0x0, "gpio_in"),
324 		  SUNXI_FUNCTION(0x1, "gpio_out"),
325 		  SUNXI_FUNCTION(0x2, "spi2"),		/* CLK */
326 		  SUNXI_FUNCTION(0x3, "jtag")),		/* CK0 */
327 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
328 		  SUNXI_FUNCTION(0x0, "gpio_in"),
329 		  SUNXI_FUNCTION(0x1, "gpio_out"),
330 		  SUNXI_FUNCTION(0x2, "spi2"),		/* MOSI */
331 		  SUNXI_FUNCTION(0x3, "jtag")),		/* DO0 */
332 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
333 		  SUNXI_FUNCTION(0x0, "gpio_in"),
334 		  SUNXI_FUNCTION(0x1, "gpio_out"),
335 		  SUNXI_FUNCTION(0x2, "spi2"),		/* MISO */
336 		  SUNXI_FUNCTION(0x3, "jtag")),		/* DI0 */
337 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
338 		  SUNXI_FUNCTION(0x0, "gpio_in"),
339 		  SUNXI_FUNCTION(0x1, "gpio_out"),
340 		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SCK */
341 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
342 		  SUNXI_FUNCTION(0x0, "gpio_in"),
343 		  SUNXI_FUNCTION(0x1, "gpio_out"),
344 		  SUNXI_FUNCTION(0x2, "i2c1")),		/* SDA */
345 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
346 		  SUNXI_FUNCTION(0x0, "gpio_in"),
347 		  SUNXI_FUNCTION(0x1, "gpio_out"),
348 		  SUNXI_FUNCTION(0x2, "i2c2"),		/* SCK */
349 		  SUNXI_FUNCTION_VARIANT(0x4, "pwm",	/* PWM4 */
350 					 PINCTRL_SUN8I_R40)),
351 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
352 		  SUNXI_FUNCTION(0x0, "gpio_in"),
353 		  SUNXI_FUNCTION(0x1, "gpio_out"),
354 		  SUNXI_FUNCTION(0x2, "i2c2"),		/* SDA */
355 		  SUNXI_FUNCTION_VARIANT(0x4, "pwm",	/* PWM5 */
356 					 PINCTRL_SUN8I_R40)),
357 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
358 		  SUNXI_FUNCTION(0x0, "gpio_in"),
359 		  SUNXI_FUNCTION(0x1, "gpio_out"),
360 		  SUNXI_FUNCTION(0x2, "uart0"),		/* TX */
361 		  SUNXI_FUNCTION_VARIANT(0x3, "ir1",	/* TX */
362 					 PINCTRL_SUN4I_A10 |
363 					 PINCTRL_SUN7I_A20)),
364 	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
365 		  SUNXI_FUNCTION(0x0, "gpio_in"),
366 		  SUNXI_FUNCTION(0x1, "gpio_out"),
367 		  SUNXI_FUNCTION(0x2, "uart0"),		/* RX */
368 		  SUNXI_FUNCTION(0x3, "ir1")),		/* RX */
369 	/* Hole */
370 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
371 		  SUNXI_FUNCTION(0x0, "gpio_in"),
372 		  SUNXI_FUNCTION(0x1, "gpio_out"),
373 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NWE */
374 		  SUNXI_FUNCTION(0x3, "spi0")),		/* MOSI */
375 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
376 		  SUNXI_FUNCTION(0x0, "gpio_in"),
377 		  SUNXI_FUNCTION(0x1, "gpio_out"),
378 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NALE */
379 		  SUNXI_FUNCTION(0x3, "spi0")),		/* MISO */
380 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
381 		  SUNXI_FUNCTION(0x0, "gpio_in"),
382 		  SUNXI_FUNCTION(0x1, "gpio_out"),
383 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCLE */
384 		  SUNXI_FUNCTION(0x3, "spi0")),		/* SCK */
385 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
386 		  SUNXI_FUNCTION(0x0, "gpio_in"),
387 		  SUNXI_FUNCTION(0x1, "gpio_out"),
388 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE1 */
389 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
390 		  SUNXI_FUNCTION(0x0, "gpio_in"),
391 		  SUNXI_FUNCTION(0x1, "gpio_out"),
392 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE0 */
393 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
394 		  SUNXI_FUNCTION(0x0, "gpio_in"),
395 		  SUNXI_FUNCTION(0x1, "gpio_out"),
396 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRE# */
397 		  SUNXI_FUNCTION_VARIANT(0x3, "mmc2",	/* DS */
398 					 PINCTRL_SUN8I_R40)),
399 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
400 		  SUNXI_FUNCTION(0x0, "gpio_in"),
401 		  SUNXI_FUNCTION(0x1, "gpio_out"),
402 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB0 */
403 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CMD */
404 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
405 		  SUNXI_FUNCTION(0x0, "gpio_in"),
406 		  SUNXI_FUNCTION(0x1, "gpio_out"),
407 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB1 */
408 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CLK */
409 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
410 		  SUNXI_FUNCTION(0x0, "gpio_in"),
411 		  SUNXI_FUNCTION(0x1, "gpio_out"),
412 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ0 */
413 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D0 */
414 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
415 		  SUNXI_FUNCTION(0x0, "gpio_in"),
416 		  SUNXI_FUNCTION(0x1, "gpio_out"),
417 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ1 */
418 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D1 */
419 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
420 		  SUNXI_FUNCTION(0x0, "gpio_in"),
421 		  SUNXI_FUNCTION(0x1, "gpio_out"),
422 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ2 */
423 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D2 */
424 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
425 		  SUNXI_FUNCTION(0x0, "gpio_in"),
426 		  SUNXI_FUNCTION(0x1, "gpio_out"),
427 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ3 */
428 		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D3 */
429 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
430 		  SUNXI_FUNCTION(0x0, "gpio_in"),
431 		  SUNXI_FUNCTION(0x1, "gpio_out"),
432 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ4 */
433 		  SUNXI_FUNCTION_VARIANT(0x3, "mmc2",	/* D4 */
434 					 PINCTRL_SUN8I_R40)),
435 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
436 		  SUNXI_FUNCTION(0x0, "gpio_in"),
437 		  SUNXI_FUNCTION(0x1, "gpio_out"),
438 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ5 */
439 		  SUNXI_FUNCTION_VARIANT(0x3, "mmc2",	/* D5 */
440 					 PINCTRL_SUN8I_R40)),
441 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
442 		  SUNXI_FUNCTION(0x0, "gpio_in"),
443 		  SUNXI_FUNCTION(0x1, "gpio_out"),
444 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ6 */
445 		  SUNXI_FUNCTION_VARIANT(0x3, "mmc2",	/* D6 */
446 					 PINCTRL_SUN8I_R40)),
447 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
448 		  SUNXI_FUNCTION(0x0, "gpio_in"),
449 		  SUNXI_FUNCTION(0x1, "gpio_out"),
450 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ7 */
451 		  SUNXI_FUNCTION_VARIANT(0x3, "mmc2",	/* D7 */
452 					 PINCTRL_SUN8I_R40)),
453 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
454 		  SUNXI_FUNCTION(0x0, "gpio_in"),
455 		  SUNXI_FUNCTION(0x1, "gpio_out"),
456 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NWP */
457 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
458 		  SUNXI_FUNCTION(0x0, "gpio_in"),
459 		  SUNXI_FUNCTION(0x1, "gpio_out"),
460 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE2 */
461 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
462 		  SUNXI_FUNCTION(0x0, "gpio_in"),
463 		  SUNXI_FUNCTION(0x1, "gpio_out"),
464 		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE3 */
465 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
466 		  SUNXI_FUNCTION(0x0, "gpio_in"),
467 		  SUNXI_FUNCTION(0x1, "gpio_out"),
468 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE4 */
469 		  SUNXI_FUNCTION(0x3, "spi2")),		/* CS0 */
470 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
471 		  SUNXI_FUNCTION(0x0, "gpio_in"),
472 		  SUNXI_FUNCTION(0x1, "gpio_out"),
473 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE5 */
474 		  SUNXI_FUNCTION(0x3, "spi2")),		/* CLK */
475 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
476 		  SUNXI_FUNCTION(0x0, "gpio_in"),
477 		  SUNXI_FUNCTION(0x1, "gpio_out"),
478 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE6 */
479 		  SUNXI_FUNCTION(0x3, "spi2")),		/* MOSI */
480 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
481 		  SUNXI_FUNCTION(0x0, "gpio_in"),
482 		  SUNXI_FUNCTION(0x1, "gpio_out"),
483 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE7 */
484 		  SUNXI_FUNCTION(0x3, "spi2")),		/* MISO */
485 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
486 		  SUNXI_FUNCTION(0x0, "gpio_in"),
487 		  SUNXI_FUNCTION(0x1, "gpio_out"),
488 		  SUNXI_FUNCTION(0x3, "spi0")),		/* CS0 */
489 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
490 		  SUNXI_FUNCTION(0x0, "gpio_in"),
491 		  SUNXI_FUNCTION(0x1, "gpio_out"),
492 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQS */
493 		  SUNXI_FUNCTION_VARIANT(0x3, "mmc2",	/* RST */
494 					 PINCTRL_SUN8I_R40)),
495 	/* Hole */
496 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
497 		  SUNXI_FUNCTION(0x0, "gpio_in"),
498 		  SUNXI_FUNCTION(0x1, "gpio_out"),
499 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D0 */
500 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP0 */
501 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
502 		  SUNXI_FUNCTION(0x0, "gpio_in"),
503 		  SUNXI_FUNCTION(0x1, "gpio_out"),
504 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D1 */
505 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN0 */
506 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
507 		  SUNXI_FUNCTION(0x0, "gpio_in"),
508 		  SUNXI_FUNCTION(0x1, "gpio_out"),
509 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
510 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP1 */
511 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
512 		  SUNXI_FUNCTION(0x0, "gpio_in"),
513 		  SUNXI_FUNCTION(0x1, "gpio_out"),
514 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
515 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN1 */
516 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
517 		  SUNXI_FUNCTION(0x0, "gpio_in"),
518 		  SUNXI_FUNCTION(0x1, "gpio_out"),
519 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
520 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP2 */
521 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
522 		  SUNXI_FUNCTION(0x0, "gpio_in"),
523 		  SUNXI_FUNCTION(0x1, "gpio_out"),
524 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
525 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN2 */
526 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
527 		  SUNXI_FUNCTION(0x0, "gpio_in"),
528 		  SUNXI_FUNCTION(0x1, "gpio_out"),
529 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
530 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VPC */
531 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
532 		  SUNXI_FUNCTION(0x0, "gpio_in"),
533 		  SUNXI_FUNCTION(0x1, "gpio_out"),
534 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
535 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VNC */
536 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
537 		  SUNXI_FUNCTION(0x0, "gpio_in"),
538 		  SUNXI_FUNCTION(0x1, "gpio_out"),
539 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D8 */
540 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP3 */
541 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
542 		  SUNXI_FUNCTION(0x0, "gpio_in"),
543 		  SUNXI_FUNCTION(0x1, "gpio_out"),
544 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D9 */
545 		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VM3 */
546 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
547 		  SUNXI_FUNCTION(0x0, "gpio_in"),
548 		  SUNXI_FUNCTION(0x1, "gpio_out"),
549 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D10 */
550 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP0 */
551 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
552 		  SUNXI_FUNCTION(0x0, "gpio_in"),
553 		  SUNXI_FUNCTION(0x1, "gpio_out"),
554 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D11 */
555 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN0 */
556 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
557 		  SUNXI_FUNCTION(0x0, "gpio_in"),
558 		  SUNXI_FUNCTION(0x1, "gpio_out"),
559 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */
560 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP1 */
561 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
562 		  SUNXI_FUNCTION(0x0, "gpio_in"),
563 		  SUNXI_FUNCTION(0x1, "gpio_out"),
564 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */
565 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN1 */
566 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
567 		  SUNXI_FUNCTION(0x0, "gpio_in"),
568 		  SUNXI_FUNCTION(0x1, "gpio_out"),
569 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */
570 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP2 */
571 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
572 		  SUNXI_FUNCTION(0x0, "gpio_in"),
573 		  SUNXI_FUNCTION(0x1, "gpio_out"),
574 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */
575 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN2 */
576 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
577 		  SUNXI_FUNCTION(0x0, "gpio_in"),
578 		  SUNXI_FUNCTION(0x1, "gpio_out"),
579 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D16 */
580 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VPC */
581 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
582 		  SUNXI_FUNCTION(0x0, "gpio_in"),
583 		  SUNXI_FUNCTION(0x1, "gpio_out"),
584 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D17 */
585 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VNC */
586 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
587 		  SUNXI_FUNCTION(0x0, "gpio_in"),
588 		  SUNXI_FUNCTION(0x1, "gpio_out"),
589 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */
590 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VP3 */
591 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
592 		  SUNXI_FUNCTION(0x0, "gpio_in"),
593 		  SUNXI_FUNCTION(0x1, "gpio_out"),
594 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */
595 		  SUNXI_FUNCTION(0x3, "lvds1")),	/* VN3 */
596 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
597 		  SUNXI_FUNCTION(0x0, "gpio_in"),
598 		  SUNXI_FUNCTION(0x1, "gpio_out"),
599 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */
600 		  SUNXI_FUNCTION(0x3, "csi1")),		/* MCLK */
601 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
602 		  SUNXI_FUNCTION(0x0, "gpio_in"),
603 		  SUNXI_FUNCTION(0x1, "gpio_out"),
604 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */
605 		  SUNXI_FUNCTION(0x3, "sim")),		/* VPPEN */
606 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
607 		  SUNXI_FUNCTION(0x0, "gpio_in"),
608 		  SUNXI_FUNCTION(0x1, "gpio_out"),
609 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */
610 		  SUNXI_FUNCTION(0x3, "sim")),		/* VPPPP */
611 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
612 		  SUNXI_FUNCTION(0x0, "gpio_in"),
613 		  SUNXI_FUNCTION(0x1, "gpio_out"),
614 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */
615 		  SUNXI_FUNCTION(0x3, "sim")),		/* DET */
616 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
617 		  SUNXI_FUNCTION(0x0, "gpio_in"),
618 		  SUNXI_FUNCTION(0x1, "gpio_out"),
619 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */
620 		  SUNXI_FUNCTION(0x3, "sim")),		/* VCCEN */
621 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
622 		  SUNXI_FUNCTION(0x0, "gpio_in"),
623 		  SUNXI_FUNCTION(0x1, "gpio_out"),
624 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */
625 		  SUNXI_FUNCTION(0x3, "sim")),		/* RST */
626 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
627 		  SUNXI_FUNCTION(0x0, "gpio_in"),
628 		  SUNXI_FUNCTION(0x1, "gpio_out"),
629 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* HSYNC */
630 		  SUNXI_FUNCTION(0x3, "sim")),		/* SCK */
631 	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
632 		  SUNXI_FUNCTION(0x0, "gpio_in"),
633 		  SUNXI_FUNCTION(0x1, "gpio_out"),
634 		  SUNXI_FUNCTION(0x2, "lcd0"),		/* VSYNC */
635 		  SUNXI_FUNCTION(0x3, "sim")),		/* SDA */
636 	/* Hole */
637 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
638 		  SUNXI_FUNCTION(0x0, "gpio_in"),
639 		  SUNXI_FUNCTION(0x1, "gpio_out"),
640 		  SUNXI_FUNCTION(0x2, "ts0"),		/* CLK */
641 		  SUNXI_FUNCTION(0x3, "csi0")),		/* PCK */
642 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
643 		  SUNXI_FUNCTION(0x0, "gpio_in"),
644 		  SUNXI_FUNCTION(0x1, "gpio_out"),
645 		  SUNXI_FUNCTION(0x2, "ts0"),		/* ERR */
646 		  SUNXI_FUNCTION(0x3, "csi0")),		/* CK */
647 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
648 		  SUNXI_FUNCTION(0x0, "gpio_in"),
649 		  SUNXI_FUNCTION(0x1, "gpio_out"),
650 		  SUNXI_FUNCTION(0x2, "ts0"),		/* SYNC */
651 		  SUNXI_FUNCTION(0x3, "csi0")),		/* HSYNC */
652 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
653 		  SUNXI_FUNCTION(0x0, "gpio_in"),
654 		  SUNXI_FUNCTION(0x1, "gpio_out"),
655 		  SUNXI_FUNCTION(0x2, "ts0"),		/* DVLD */
656 		  SUNXI_FUNCTION(0x3, "csi0")),		/* VSYNC */
657 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
658 		  SUNXI_FUNCTION(0x0, "gpio_in"),
659 		  SUNXI_FUNCTION(0x1, "gpio_out"),
660 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D0 */
661 		  SUNXI_FUNCTION(0x3, "csi0")),		/* D0 */
662 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
663 		  SUNXI_FUNCTION(0x0, "gpio_in"),
664 		  SUNXI_FUNCTION(0x1, "gpio_out"),
665 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D1 */
666 		  SUNXI_FUNCTION(0x3, "csi0"),		/* D1 */
667 		  SUNXI_FUNCTION(0x4, "sim")),		/* VPPEN */
668 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
669 		  SUNXI_FUNCTION(0x0, "gpio_in"),
670 		  SUNXI_FUNCTION(0x1, "gpio_out"),
671 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D2 */
672 		  SUNXI_FUNCTION(0x3, "csi0")),		/* D2 */
673 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
674 		  SUNXI_FUNCTION(0x0, "gpio_in"),
675 		  SUNXI_FUNCTION(0x1, "gpio_out"),
676 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D3 */
677 		  SUNXI_FUNCTION(0x3, "csi0")),		/* D3 */
678 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
679 		  SUNXI_FUNCTION(0x0, "gpio_in"),
680 		  SUNXI_FUNCTION(0x1, "gpio_out"),
681 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D4 */
682 		  SUNXI_FUNCTION(0x3, "csi0")),		/* D4 */
683 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
684 		  SUNXI_FUNCTION(0x0, "gpio_in"),
685 		  SUNXI_FUNCTION(0x1, "gpio_out"),
686 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D5 */
687 		  SUNXI_FUNCTION(0x3, "csi0")),		/* D5 */
688 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
689 		  SUNXI_FUNCTION(0x0, "gpio_in"),
690 		  SUNXI_FUNCTION(0x1, "gpio_out"),
691 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D6 */
692 		  SUNXI_FUNCTION(0x3, "csi0")),		/* D6 */
693 	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
694 		  SUNXI_FUNCTION(0x0, "gpio_in"),
695 		  SUNXI_FUNCTION(0x1, "gpio_out"),
696 		  SUNXI_FUNCTION(0x2, "ts0"),		/* D7 */
697 		  SUNXI_FUNCTION(0x3, "csi0")),		/* D7 */
698 	/* Hole */
699 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
700 		  SUNXI_FUNCTION(0x0, "gpio_in"),
701 		  SUNXI_FUNCTION(0x1, "gpio_out"),
702 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
703 		  SUNXI_FUNCTION(0x4, "jtag")),		/* MSI */
704 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
705 		  SUNXI_FUNCTION(0x0, "gpio_in"),
706 		  SUNXI_FUNCTION(0x1, "gpio_out"),
707 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
708 		  SUNXI_FUNCTION(0x4, "jtag")),		/* DI1 */
709 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
710 		  SUNXI_FUNCTION(0x0, "gpio_in"),
711 		  SUNXI_FUNCTION(0x1, "gpio_out"),
712 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
713 		  SUNXI_FUNCTION(0x4, "uart0")),	/* TX */
714 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
715 		  SUNXI_FUNCTION(0x0, "gpio_in"),
716 		  SUNXI_FUNCTION(0x1, "gpio_out"),
717 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
718 		  SUNXI_FUNCTION(0x4, "jtag")),		/* DO1 */
719 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
720 		  SUNXI_FUNCTION(0x0, "gpio_in"),
721 		  SUNXI_FUNCTION(0x1, "gpio_out"),
722 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
723 		  SUNXI_FUNCTION(0x4, "uart0")),	/* RX */
724 	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
725 		  SUNXI_FUNCTION(0x0, "gpio_in"),
726 		  SUNXI_FUNCTION(0x1, "gpio_out"),
727 		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
728 		  SUNXI_FUNCTION(0x4, "jtag")),		/* CK1 */
729 	/* Hole */
730 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
731 		  SUNXI_FUNCTION(0x0, "gpio_in"),
732 		  SUNXI_FUNCTION(0x1, "gpio_out"),
733 		  SUNXI_FUNCTION(0x2, "ts1"),		/* CLK */
734 		  SUNXI_FUNCTION(0x3, "csi1"),		/* PCK */
735 		  SUNXI_FUNCTION(0x4, "mmc1")),		/* CMD */
736 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
737 		  SUNXI_FUNCTION(0x0, "gpio_in"),
738 		  SUNXI_FUNCTION(0x1, "gpio_out"),
739 		  SUNXI_FUNCTION(0x2, "ts1"),		/* ERR */
740 		  SUNXI_FUNCTION(0x3, "csi1"),		/* CK */
741 		  SUNXI_FUNCTION(0x4, "mmc1")),		/* CLK */
742 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
743 		  SUNXI_FUNCTION(0x0, "gpio_in"),
744 		  SUNXI_FUNCTION(0x1, "gpio_out"),
745 		  SUNXI_FUNCTION(0x2, "ts1"),		/* SYNC */
746 		  SUNXI_FUNCTION(0x3, "csi1"),		/* HSYNC */
747 		  SUNXI_FUNCTION(0x4, "mmc1")),		/* D0 */
748 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
749 		  SUNXI_FUNCTION(0x0, "gpio_in"),
750 		  SUNXI_FUNCTION(0x1, "gpio_out"),
751 		  SUNXI_FUNCTION(0x2, "ts1"),		/* DVLD */
752 		  SUNXI_FUNCTION(0x3, "csi1"),		/* VSYNC */
753 		  SUNXI_FUNCTION(0x4, "mmc1")),		/* D1 */
754 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
755 		  SUNXI_FUNCTION(0x0, "gpio_in"),
756 		  SUNXI_FUNCTION(0x1, "gpio_out"),
757 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D0 */
758 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D0 */
759 		  SUNXI_FUNCTION(0x4, "mmc1"),		/* D2 */
760 		  SUNXI_FUNCTION(0x5, "csi0")),		/* D8 */
761 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
762 		  SUNXI_FUNCTION(0x0, "gpio_in"),
763 		  SUNXI_FUNCTION(0x1, "gpio_out"),
764 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D1 */
765 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D1 */
766 		  SUNXI_FUNCTION(0x4, "mmc1"),		/* D3 */
767 		  SUNXI_FUNCTION(0x5, "csi0")),		/* D9 */
768 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
769 		  SUNXI_FUNCTION(0x0, "gpio_in"),
770 		  SUNXI_FUNCTION(0x1, "gpio_out"),
771 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D2 */
772 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D2 */
773 		  SUNXI_FUNCTION(0x4, "uart3"),		/* TX */
774 		  SUNXI_FUNCTION(0x5, "csi0")),		/* D10 */
775 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
776 		  SUNXI_FUNCTION(0x0, "gpio_in"),
777 		  SUNXI_FUNCTION(0x1, "gpio_out"),
778 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D3 */
779 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D3 */
780 		  SUNXI_FUNCTION(0x4, "uart3"),		/* RX */
781 		  SUNXI_FUNCTION(0x5, "csi0")),		/* D11 */
782 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
783 		  SUNXI_FUNCTION(0x0, "gpio_in"),
784 		  SUNXI_FUNCTION(0x1, "gpio_out"),
785 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D4 */
786 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D4 */
787 		  SUNXI_FUNCTION(0x4, "uart3"),		/* RTS */
788 		  SUNXI_FUNCTION(0x5, "csi0")),		/* D12 */
789 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
790 		  SUNXI_FUNCTION(0x0, "gpio_in"),
791 		  SUNXI_FUNCTION(0x1, "gpio_out"),
792 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D5 */
793 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D5 */
794 		  SUNXI_FUNCTION(0x4, "uart3"),		/* CTS */
795 		  SUNXI_FUNCTION(0x5, "csi0"),		/* D13 */
796 		  SUNXI_FUNCTION_VARIANT(0x6, "bist",	/* RESULT0 */
797 					 PINCTRL_SUN8I_R40)),
798 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
799 		  SUNXI_FUNCTION(0x0, "gpio_in"),
800 		  SUNXI_FUNCTION(0x1, "gpio_out"),
801 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D6 */
802 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D6 */
803 		  SUNXI_FUNCTION(0x4, "uart4"),		/* TX */
804 		  SUNXI_FUNCTION(0x5, "csi0"),		/* D14 */
805 		  SUNXI_FUNCTION_VARIANT(0x6, "bist",	/* RESULT1 */
806 					 PINCTRL_SUN8I_R40)),
807 	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
808 		  SUNXI_FUNCTION(0x0, "gpio_in"),
809 		  SUNXI_FUNCTION(0x1, "gpio_out"),
810 		  SUNXI_FUNCTION(0x2, "ts1"),		/* D7 */
811 		  SUNXI_FUNCTION(0x3, "csi1"),		/* D7 */
812 		  SUNXI_FUNCTION(0x4, "uart4"),		/* RX */
813 		  SUNXI_FUNCTION(0x5, "csi0")),		/* D15 */
814 	/* Hole */
815 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
816 		  SUNXI_FUNCTION(0x0, "gpio_in"),
817 		  SUNXI_FUNCTION(0x1, "gpio_out"),
818 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D0 */
819 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAA0 */
820 					 PINCTRL_SUN4I_A10),
821 		  SUNXI_FUNCTION(0x4, "uart3"),		/* TX */
822 		  SUNXI_FUNCTION_IRQ(0x6, 0),		/* EINT0 */
823 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D0 */
824 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
825 		  SUNXI_FUNCTION(0x0, "gpio_in"),
826 		  SUNXI_FUNCTION(0x1, "gpio_out"),
827 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D1 */
828 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAA1 */
829 					 PINCTRL_SUN4I_A10),
830 		  SUNXI_FUNCTION(0x4, "uart3"),		/* RX */
831 		  SUNXI_FUNCTION_IRQ(0x6, 1),		/* EINT1 */
832 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D1 */
833 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
834 		  SUNXI_FUNCTION(0x0, "gpio_in"),
835 		  SUNXI_FUNCTION(0x1, "gpio_out"),
836 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D2 */
837 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAA2 */
838 					 PINCTRL_SUN4I_A10),
839 		  SUNXI_FUNCTION(0x4, "uart3"),		/* RTS */
840 		  SUNXI_FUNCTION_IRQ(0x6, 2),		/* EINT2 */
841 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D2 */
842 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
843 		  SUNXI_FUNCTION(0x0, "gpio_in"),
844 		  SUNXI_FUNCTION(0x1, "gpio_out"),
845 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D3 */
846 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAIRQ */
847 					 PINCTRL_SUN4I_A10),
848 		  SUNXI_FUNCTION(0x4, "uart3"),		/* CTS */
849 		  SUNXI_FUNCTION_IRQ(0x6, 3),		/* EINT3 */
850 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D3 */
851 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
852 		  SUNXI_FUNCTION(0x0, "gpio_in"),
853 		  SUNXI_FUNCTION(0x1, "gpio_out"),
854 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D4 */
855 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD0 */
856 					 PINCTRL_SUN4I_A10),
857 		  SUNXI_FUNCTION(0x4, "uart4"),		/* TX */
858 		  SUNXI_FUNCTION_IRQ(0x6, 4),		/* EINT4 */
859 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D4 */
860 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
861 		  SUNXI_FUNCTION(0x0, "gpio_in"),
862 		  SUNXI_FUNCTION(0x1, "gpio_out"),
863 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D5 */
864 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD1 */
865 					 PINCTRL_SUN4I_A10),
866 		  SUNXI_FUNCTION(0x4, "uart4"),		/* RX */
867 		  SUNXI_FUNCTION_IRQ(0x6, 5),		/* EINT5 */
868 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D5 */
869 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
870 		  SUNXI_FUNCTION(0x0, "gpio_in"),
871 		  SUNXI_FUNCTION(0x1, "gpio_out"),
872 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D6 */
873 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD2 */
874 					 PINCTRL_SUN4I_A10),
875 		  SUNXI_FUNCTION(0x4, "uart5"),		/* TX */
876 		  SUNXI_FUNCTION_VARIANT(0x5, "ms",	/* BS */
877 					 PINCTRL_SUN4I_A10 |
878 					 PINCTRL_SUN7I_A20),
879 		  SUNXI_FUNCTION_IRQ(0x6, 6),		/* EINT6 */
880 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D6 */
881 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
882 		  SUNXI_FUNCTION(0x0, "gpio_in"),
883 		  SUNXI_FUNCTION(0x1, "gpio_out"),
884 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D7 */
885 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD3 */
886 					 PINCTRL_SUN4I_A10),
887 		  SUNXI_FUNCTION(0x4, "uart5"),		/* RX */
888 		  SUNXI_FUNCTION_VARIANT(0x5, "ms",	/* CLK */
889 					 PINCTRL_SUN4I_A10 |
890 					 PINCTRL_SUN7I_A20),
891 		  SUNXI_FUNCTION_IRQ(0x6, 7),		/* EINT7 */
892 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D7 */
893 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
894 		  SUNXI_FUNCTION(0x0, "gpio_in"),
895 		  SUNXI_FUNCTION(0x1, "gpio_out"),
896 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D8 */
897 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD4 */
898 					 PINCTRL_SUN4I_A10),
899 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ERXD3 */
900 					 PINCTRL_SUN7I_A20 |
901 					 PINCTRL_SUN8I_R40),
902 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN0 */
903 		  SUNXI_FUNCTION_VARIANT(0x5, "ms",	/* D0 */
904 					 PINCTRL_SUN4I_A10 |
905 					 PINCTRL_SUN7I_A20),
906 		  SUNXI_FUNCTION_IRQ(0x6, 8),		/* EINT8 */
907 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D8 */
908 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
909 		  SUNXI_FUNCTION(0x0, "gpio_in"),
910 		  SUNXI_FUNCTION(0x1, "gpio_out"),
911 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D9 */
912 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD5 */
913 					 PINCTRL_SUN4I_A10),
914 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ERXD2 */
915 					 PINCTRL_SUN7I_A20 |
916 					 PINCTRL_SUN8I_R40),
917 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN1 */
918 		  SUNXI_FUNCTION_VARIANT(0x5, "ms",	/* D1 */
919 					 PINCTRL_SUN4I_A10 |
920 					 PINCTRL_SUN7I_A20),
921 		  SUNXI_FUNCTION_IRQ(0x6, 9),		/* EINT9 */
922 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D9 */
923 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
924 		  SUNXI_FUNCTION(0x0, "gpio_in"),
925 		  SUNXI_FUNCTION(0x1, "gpio_out"),
926 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D10 */
927 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD6 */
928 					 PINCTRL_SUN4I_A10),
929 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ERXD1 */
930 					 PINCTRL_SUN7I_A20 |
931 					 PINCTRL_SUN8I_R40),
932 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN2 */
933 		  SUNXI_FUNCTION_VARIANT(0x5, "ms",	/* D2 */
934 					 PINCTRL_SUN4I_A10 |
935 					 PINCTRL_SUN7I_A20),
936 		  SUNXI_FUNCTION_IRQ(0x6, 10),		/* EINT10 */
937 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D10 */
938 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
939 		  SUNXI_FUNCTION(0x0, "gpio_in"),
940 		  SUNXI_FUNCTION(0x1, "gpio_out"),
941 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D11 */
942 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD7 */
943 					 PINCTRL_SUN4I_A10),
944 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ERXD0 */
945 					 PINCTRL_SUN7I_A20 |
946 					 PINCTRL_SUN8I_R40),
947 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN3 */
948 		  SUNXI_FUNCTION_VARIANT(0x5, "ms",	/* D3 */
949 					 PINCTRL_SUN4I_A10 |
950 					 PINCTRL_SUN7I_A20),
951 		  SUNXI_FUNCTION_IRQ(0x6, 11),		/* EINT11 */
952 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D11 */
953 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
954 		  SUNXI_FUNCTION(0x0, "gpio_in"),
955 		  SUNXI_FUNCTION(0x1, "gpio_out"),
956 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D12 */
957 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD8 */
958 					 PINCTRL_SUN4I_A10),
959 		  SUNXI_FUNCTION(0x4, "ps2"),		/* SCK1 */
960 		  SUNXI_FUNCTION_IRQ(0x6, 12),		/* EINT12 */
961 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D12 */
962 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
963 		  SUNXI_FUNCTION(0x0, "gpio_in"),
964 		  SUNXI_FUNCTION(0x1, "gpio_out"),
965 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D13 */
966 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD9 */
967 					 PINCTRL_SUN4I_A10),
968 		  SUNXI_FUNCTION(0x4, "ps2"),		/* SDA1 */
969 		  SUNXI_FUNCTION(0x5, "sim"),		/* RST */
970 		  SUNXI_FUNCTION_IRQ(0x6, 13),		/* EINT13 */
971 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D13 */
972 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
973 		  SUNXI_FUNCTION(0x0, "gpio_in"),
974 		  SUNXI_FUNCTION(0x1, "gpio_out"),
975 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D14 */
976 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD10 */
977 					 PINCTRL_SUN4I_A10),
978 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ETXD3 */
979 					 PINCTRL_SUN7I_A20 |
980 					 PINCTRL_SUN8I_R40),
981 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN4 */
982 		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPEN */
983 		  SUNXI_FUNCTION_IRQ(0x6, 14),		/* EINT14 */
984 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D14 */
985 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
986 		  SUNXI_FUNCTION(0x0, "gpio_in"),
987 		  SUNXI_FUNCTION(0x1, "gpio_out"),
988 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D15 */
989 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD11 */
990 					 PINCTRL_SUN4I_A10),
991 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ETXD2 */
992 					 PINCTRL_SUN7I_A20 |
993 					 PINCTRL_SUN8I_R40),
994 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN5 */
995 		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPPP */
996 		  SUNXI_FUNCTION_IRQ(0x6, 15),		/* EINT15 */
997 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D15 */
998 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
999 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1000 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1001 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D16 */
1002 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD12 */
1003 					 PINCTRL_SUN4I_A10),
1004 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ETXD1 */
1005 					 PINCTRL_SUN7I_A20 |
1006 					 PINCTRL_SUN8I_R40),
1007 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN6 */
1008 		  SUNXI_FUNCTION(0x5, "sim"),		/* DET */
1009 		  SUNXI_FUNCTION_IRQ(0x6, 16),		/* EINT16 */
1010 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D16 */
1011 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
1012 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1013 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1014 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D17 */
1015 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD13 */
1016 					 PINCTRL_SUN4I_A10),
1017 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ETXD0 */
1018 					 PINCTRL_SUN7I_A20 |
1019 					 PINCTRL_SUN8I_R40),
1020 		  SUNXI_FUNCTION(0x4, "keypad"),	/* IN7 */
1021 		  SUNXI_FUNCTION(0x5, "sim"),		/* VCCEN */
1022 		  SUNXI_FUNCTION_IRQ(0x6, 17),		/* EINT17 */
1023 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D17 */
1024 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
1025 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1026 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1027 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D18 */
1028 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD14 */
1029 					 PINCTRL_SUN4I_A10),
1030 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ERXCK */
1031 					 PINCTRL_SUN7I_A20 |
1032 					 PINCTRL_SUN8I_R40),
1033 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT0 */
1034 		  SUNXI_FUNCTION(0x5, "sim"),		/* SCK */
1035 		  SUNXI_FUNCTION_IRQ(0x6, 18),		/* EINT18 */
1036 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D18 */
1037 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
1038 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1039 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1040 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D19 */
1041 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAD15 */
1042 					 PINCTRL_SUN4I_A10),
1043 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ERXERR */
1044 					 PINCTRL_SUN7I_A20 |
1045 					 PINCTRL_SUN8I_R40),
1046 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT1 */
1047 		  SUNXI_FUNCTION(0x5, "sim"),		/* SDA */
1048 		  SUNXI_FUNCTION_IRQ(0x6, 19),		/* EINT19 */
1049 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D19 */
1050 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
1051 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1052 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1053 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D20 */
1054 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAOE */
1055 					 PINCTRL_SUN4I_A10),
1056 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ERXDV */
1057 					 PINCTRL_SUN7I_A20 |
1058 					 PINCTRL_SUN8I_R40),
1059 		  SUNXI_FUNCTION(0x4, "can"),		/* TX */
1060 		  SUNXI_FUNCTION_IRQ(0x6, 20),		/* EINT20 */
1061 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D20 */
1062 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
1063 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1064 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1065 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D21 */
1066 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATADREQ */
1067 					 PINCTRL_SUN4I_A10),
1068 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* EMDC */
1069 					 PINCTRL_SUN7I_A20 |
1070 					 PINCTRL_SUN8I_R40),
1071 		  SUNXI_FUNCTION(0x4, "can"),		/* RX */
1072 		  SUNXI_FUNCTION_IRQ(0x6, 21),		/* EINT21 */
1073 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D21 */
1074 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
1075 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1076 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1077 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D22 */
1078 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATADACK */
1079 					 PINCTRL_SUN4I_A10),
1080 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* EMDIO */
1081 					 PINCTRL_SUN7I_A20 |
1082 					 PINCTRL_SUN8I_R40),
1083 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT2 */
1084 		  SUNXI_FUNCTION(0x5, "mmc1"),		/* CMD */
1085 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D22 */
1086 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
1087 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1088 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1089 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* D23 */
1090 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATACS0 */
1091 					 PINCTRL_SUN4I_A10),
1092 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ETXEN */
1093 					 PINCTRL_SUN7I_A20 |
1094 					 PINCTRL_SUN8I_R40),
1095 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT3 */
1096 		  SUNXI_FUNCTION(0x5, "mmc1"),		/* CLK */
1097 		  SUNXI_FUNCTION(0x7, "csi1")),		/* D23 */
1098 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
1099 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1100 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1101 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* CLK */
1102 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATACS1 */
1103 					 PINCTRL_SUN4I_A10),
1104 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ETXCK */
1105 					 PINCTRL_SUN7I_A20 |
1106 					 PINCTRL_SUN8I_R40),
1107 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT4 */
1108 		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D0 */
1109 		  SUNXI_FUNCTION(0x7, "csi1")),		/* PCLK */
1110 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
1111 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1112 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1113 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* DE */
1114 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAIORDY */
1115 					 PINCTRL_SUN4I_A10),
1116 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ECRS */
1117 					 PINCTRL_SUN7I_A20 |
1118 					 PINCTRL_SUN8I_R40),
1119 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT5 */
1120 		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D1 */
1121 		  SUNXI_FUNCTION(0x7, "csi1")),		/* FIELD */
1122 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
1123 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1124 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1125 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* HSYNC */
1126 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAIOR */
1127 					 PINCTRL_SUN4I_A10),
1128 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ECOL */
1129 					 PINCTRL_SUN7I_A20 |
1130 					 PINCTRL_SUN8I_R40),
1131 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT6 */
1132 		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D2 */
1133 		  SUNXI_FUNCTION(0x7, "csi1")),		/* HSYNC */
1134 	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
1135 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1136 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1137 		  SUNXI_FUNCTION(0x2, "lcd1"),		/* VSYNC */
1138 		  SUNXI_FUNCTION_VARIANT(0x3, "pata",	/* ATAIOW */
1139 					 PINCTRL_SUN4I_A10),
1140 		  SUNXI_FUNCTION_VARIANT(0x3, "emac",	/* ETXERR */
1141 					 PINCTRL_SUN7I_A20 |
1142 					 PINCTRL_SUN8I_R40),
1143 		  SUNXI_FUNCTION(0x4, "keypad"),	/* OUT7 */
1144 		  SUNXI_FUNCTION(0x5, "mmc1"),		/* D3 */
1145 		  SUNXI_FUNCTION(0x7, "csi1")),		/* VSYNC */
1146 	/* Hole */
1147 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
1148 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1149 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1150 		  SUNXI_FUNCTION_VARIANT(0x3, "i2c3",	/* SCK */
1151 					 PINCTRL_SUN7I_A20 |
1152 					 PINCTRL_SUN8I_R40)),
1153 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
1154 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1155 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1156 		  SUNXI_FUNCTION_VARIANT(0x3, "i2c3",	/* SDA */
1157 					 PINCTRL_SUN7I_A20 |
1158 					 PINCTRL_SUN8I_R40)),
1159 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
1160 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1161 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1162 		  SUNXI_FUNCTION_VARIANT(0x3, "i2c4",	/* SCK */
1163 					 PINCTRL_SUN7I_A20 |
1164 					 PINCTRL_SUN8I_R40)),
1165 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
1166 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1167 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1168 		  SUNXI_FUNCTION(0x2, "pwm"),		/* PWM1 */
1169 		  SUNXI_FUNCTION_VARIANT(0x3, "i2c4",	/* SDA */
1170 					 PINCTRL_SUN7I_A20 |
1171 					 PINCTRL_SUN8I_R40)),
1172 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
1173 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1174 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1175 		  SUNXI_FUNCTION(0x2, "mmc3")),		/* CMD */
1176 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
1177 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1178 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1179 		  SUNXI_FUNCTION(0x2, "mmc3")),		/* CLK */
1180 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
1181 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1182 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1183 		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D0 */
1184 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
1185 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1186 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1187 		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D1 */
1188 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
1189 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1190 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1191 		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D2 */
1192 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
1193 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1194 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1195 		  SUNXI_FUNCTION(0x2, "mmc3")),		/* D3 */
1196 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
1197 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1198 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1199 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CS0 */
1200 		  SUNXI_FUNCTION(0x3, "uart5"),		/* TX */
1201 		  SUNXI_FUNCTION_IRQ(0x6, 22)),		/* EINT22 */
1202 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
1203 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1204 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1205 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CLK */
1206 		  SUNXI_FUNCTION(0x3, "uart5"),		/* RX */
1207 		  SUNXI_FUNCTION_IRQ(0x6, 23)),		/* EINT23 */
1208 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
1209 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1210 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1211 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */
1212 		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
1213 		  SUNXI_FUNCTION_VARIANT(0x4, "clk_out_a",
1214 					 PINCTRL_SUN7I_A20 |
1215 					 PINCTRL_SUN8I_R40),
1216 		  SUNXI_FUNCTION_IRQ(0x6, 24)),		/* EINT24 */
1217 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
1218 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1219 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1220 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */
1221 		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
1222 		  SUNXI_FUNCTION_VARIANT(0x4, "clk_out_b",
1223 					 PINCTRL_SUN7I_A20 |
1224 					 PINCTRL_SUN8I_R40),
1225 		  SUNXI_FUNCTION_IRQ(0x6, 25)),		/* EINT25 */
1226 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
1227 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1228 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1229 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CS1 */
1230 		  SUNXI_FUNCTION(0x3, "ps2"),		/* SCK1 */
1231 		  SUNXI_FUNCTION(0x4, "timer4"),	/* TCLKIN0 */
1232 		  SUNXI_FUNCTION_IRQ(0x6, 26)),		/* EINT26 */
1233 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
1234 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1235 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1236 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS1 */
1237 		  SUNXI_FUNCTION(0x3, "ps2"),		/* SDA1 */
1238 		  SUNXI_FUNCTION(0x4, "timer5"),	/* TCLKIN1 */
1239 		  SUNXI_FUNCTION_IRQ(0x6, 27)),		/* EINT27 */
1240 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
1241 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1242 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1243 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */
1244 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RTS */
1245 		  SUNXI_FUNCTION_IRQ(0x6, 28)),		/* EINT28 */
1246 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
1247 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1248 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1249 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */
1250 		  SUNXI_FUNCTION(0x3, "uart2"),		/* CTS */
1251 		  SUNXI_FUNCTION_IRQ(0x6, 29)),		/* EINT29 */
1252 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
1253 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1254 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1255 		  SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */
1256 		  SUNXI_FUNCTION(0x3, "uart2"),		/* TX */
1257 		  SUNXI_FUNCTION_IRQ(0x6, 30)),		/* EINT30 */
1258 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
1259 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1260 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1261 		  SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */
1262 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RX */
1263 		  SUNXI_FUNCTION_IRQ(0x6, 31)),		/* EINT31 */
1264 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
1265 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1266 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1267 		  SUNXI_FUNCTION(0x2, "ps2"),		/* SCK0 */
1268 		  SUNXI_FUNCTION(0x3, "uart7"),		/* TX */
1269 		  SUNXI_FUNCTION_VARIANT(0x4, "hdmi",	/* HSCL */
1270 					 PINCTRL_SUN4I_A10 |
1271 					 PINCTRL_SUN7I_A20),
1272 		  SUNXI_FUNCTION_VARIANT(0x6, "pwm",	/* PWM2 */
1273 					 PINCTRL_SUN8I_R40)),
1274 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
1275 		  SUNXI_FUNCTION(0x0, "gpio_in"),
1276 		  SUNXI_FUNCTION(0x1, "gpio_out"),
1277 		  SUNXI_FUNCTION(0x2, "ps2"),		/* SDA0 */
1278 		  SUNXI_FUNCTION(0x3, "uart7"),		/* RX */
1279 		  SUNXI_FUNCTION_VARIANT(0x4, "hdmi",	/* HSDA */
1280 					 PINCTRL_SUN4I_A10 |
1281 					 PINCTRL_SUN7I_A20),
1282 		  SUNXI_FUNCTION_VARIANT(0x6, "pwm",	/* PWM3 */
1283 					 PINCTRL_SUN8I_R40)),
1284 };
1285 
1286 static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1287 	.pins = sun4i_a10_pins,
1288 	.npins = ARRAY_SIZE(sun4i_a10_pins),
1289 	.irq_banks = 1,
1290 	.irq_read_needs_mux = true,
1291 	.disable_strict_mode = true,
1292 };
1293 
sun4i_a10_pinctrl_probe(struct platform_device * pdev)1294 static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
1295 {
1296 	unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
1297 
1298 	return sunxi_pinctrl_init_with_variant(pdev, &sun4i_a10_pinctrl_data,
1299 					       variant);
1300 }
1301 
1302 static const struct of_device_id sun4i_a10_pinctrl_match[] = {
1303 	{
1304 		.compatible = "allwinner,sun4i-a10-pinctrl",
1305 		.data = (void *)PINCTRL_SUN4I_A10
1306 	},
1307 	{
1308 		.compatible = "allwinner,sun7i-a20-pinctrl",
1309 		.data = (void *)PINCTRL_SUN7I_A20
1310 	},
1311 	{
1312 		.compatible = "allwinner,sun8i-r40-pinctrl",
1313 		.data = (void *)PINCTRL_SUN8I_R40
1314 	},
1315 	{}
1316 };
1317 
1318 static struct platform_driver sun4i_a10_pinctrl_driver = {
1319 	.probe	= sun4i_a10_pinctrl_probe,
1320 	.driver	= {
1321 		.name		= "sun4i-pinctrl",
1322 		.of_match_table	= sun4i_a10_pinctrl_match,
1323 	},
1324 };
1325 builtin_platform_driver(sun4i_a10_pinctrl_driver);
1326