1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Mediatek ALSA SoC AFE platform driver for 2701
4 *
5 * Copyright (c) 2016 MediaTek Inc.
6 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
7 * Ir Lian <ir.lian@mediatek.com>
8 * Ryder Lee <ryder.lee@mediatek.com>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/module.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_runtime.h>
18
19 #include "mt2701-afe-common.h"
20 #include "mt2701-afe-clock-ctrl.h"
21 #include "../common/mtk-afe-platform-driver.h"
22 #include "../common/mtk-afe-fe-dai.h"
23
24 static const struct snd_pcm_hardware mt2701_afe_hardware = {
25 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
26 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
27 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
28 | SNDRV_PCM_FMTBIT_S32_LE,
29 .period_bytes_min = 1024,
30 .period_bytes_max = 1024 * 256,
31 .periods_min = 4,
32 .periods_max = 1024,
33 .buffer_bytes_max = 1024 * 1024,
34 .fifo_size = 0,
35 };
36
37 struct mt2701_afe_rate {
38 unsigned int rate;
39 unsigned int regvalue;
40 };
41
42 static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
43 { .rate = 8000, .regvalue = 0 },
44 { .rate = 12000, .regvalue = 1 },
45 { .rate = 16000, .regvalue = 2 },
46 { .rate = 24000, .regvalue = 3 },
47 { .rate = 32000, .regvalue = 4 },
48 { .rate = 48000, .regvalue = 5 },
49 { .rate = 96000, .regvalue = 6 },
50 { .rate = 192000, .regvalue = 7 },
51 { .rate = 384000, .regvalue = 8 },
52 { .rate = 7350, .regvalue = 16 },
53 { .rate = 11025, .regvalue = 17 },
54 { .rate = 14700, .regvalue = 18 },
55 { .rate = 22050, .regvalue = 19 },
56 { .rate = 29400, .regvalue = 20 },
57 { .rate = 44100, .regvalue = 21 },
58 { .rate = 88200, .regvalue = 22 },
59 { .rate = 176400, .regvalue = 23 },
60 { .rate = 352800, .regvalue = 24 },
61 };
62
63 static const unsigned int mt2701_afe_backup_list[] = {
64 AUDIO_TOP_CON0,
65 AUDIO_TOP_CON4,
66 AUDIO_TOP_CON5,
67 ASYS_TOP_CON,
68 AFE_CONN0,
69 AFE_CONN1,
70 AFE_CONN2,
71 AFE_CONN3,
72 AFE_CONN15,
73 AFE_CONN16,
74 AFE_CONN17,
75 AFE_CONN18,
76 AFE_CONN19,
77 AFE_CONN20,
78 AFE_CONN21,
79 AFE_CONN22,
80 AFE_DAC_CON0,
81 AFE_MEMIF_PBUF_SIZE,
82 };
83
mt2701_dai_num_to_i2s(struct mtk_base_afe * afe,int num)84 static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
85 {
86 struct mt2701_afe_private *afe_priv = afe->platform_priv;
87 int val = num - MT2701_IO_I2S;
88
89 if (val < 0 || val >= afe_priv->soc->i2s_num) {
90 dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
91 __func__, num, val);
92 return -EINVAL;
93 }
94 return val;
95 }
96
mt2701_afe_i2s_fs(unsigned int sample_rate)97 static int mt2701_afe_i2s_fs(unsigned int sample_rate)
98 {
99 int i;
100
101 for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
102 if (mt2701_afe_i2s_rates[i].rate == sample_rate)
103 return mt2701_afe_i2s_rates[i].regvalue;
104
105 return -EINVAL;
106 }
107
mt2701_afe_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)108 static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
109 struct snd_soc_dai *dai)
110 {
111 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
112 struct mt2701_afe_private *afe_priv = afe->platform_priv;
113 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
114 bool mode = afe_priv->soc->has_one_heart_mode;
115
116 if (i2s_num < 0)
117 return i2s_num;
118
119 return mt2701_afe_enable_mclk(afe, mode ? 1 : i2s_num);
120 }
121
mt2701_afe_i2s_path_disable(struct mtk_base_afe * afe,struct mt2701_i2s_path * i2s_path,int stream_dir)122 static int mt2701_afe_i2s_path_disable(struct mtk_base_afe *afe,
123 struct mt2701_i2s_path *i2s_path,
124 int stream_dir)
125 {
126 const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
127
128 if (--i2s_path->on[stream_dir] < 0)
129 i2s_path->on[stream_dir] = 0;
130
131 if (i2s_path->on[stream_dir])
132 return 0;
133
134 /* disable i2s */
135 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
136 ASYS_I2S_CON_I2S_EN, 0);
137
138 mt2701_afe_disable_i2s(afe, i2s_path, stream_dir);
139
140 return 0;
141 }
142
mt2701_afe_i2s_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)143 static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
144 struct snd_soc_dai *dai)
145 {
146 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
147 struct mt2701_afe_private *afe_priv = afe->platform_priv;
148 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
149 struct mt2701_i2s_path *i2s_path;
150 bool mode = afe_priv->soc->has_one_heart_mode;
151
152 if (i2s_num < 0)
153 return;
154
155 i2s_path = &afe_priv->i2s_path[i2s_num];
156
157 if (i2s_path->occupied[substream->stream])
158 i2s_path->occupied[substream->stream] = 0;
159 else
160 goto exit;
161
162 mt2701_afe_i2s_path_disable(afe, i2s_path, substream->stream);
163
164 /* need to disable i2s-out path when disable i2s-in */
165 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
166 mt2701_afe_i2s_path_disable(afe, i2s_path, !substream->stream);
167
168 exit:
169 /* disable mclk */
170 mt2701_afe_disable_mclk(afe, mode ? 1 : i2s_num);
171 }
172
mt2701_i2s_path_enable(struct mtk_base_afe * afe,struct mt2701_i2s_path * i2s_path,int stream_dir,int rate)173 static int mt2701_i2s_path_enable(struct mtk_base_afe *afe,
174 struct mt2701_i2s_path *i2s_path,
175 int stream_dir, int rate)
176 {
177 const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
178 struct mt2701_afe_private *afe_priv = afe->platform_priv;
179 int reg, fs, w_len = 1; /* now we support bck 64bits only */
180 unsigned int mask, val;
181
182 /* no need to enable if already done */
183 if (++i2s_path->on[stream_dir] != 1)
184 return 0;
185
186 fs = mt2701_afe_i2s_fs(rate);
187
188 mask = ASYS_I2S_CON_FS |
189 ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */
190 ASYS_I2S_CON_I2S_MODE |
191 ASYS_I2S_CON_WIDE_MODE;
192
193 val = ASYS_I2S_CON_FS_SET(fs) |
194 ASYS_I2S_CON_I2S_MODE |
195 ASYS_I2S_CON_WIDE_MODE_SET(w_len);
196
197 if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
198 mask |= ASYS_I2S_IN_PHASE_FIX;
199 val |= ASYS_I2S_IN_PHASE_FIX;
200 reg = ASMI_TIMING_CON1;
201 } else {
202 if (afe_priv->soc->has_one_heart_mode) {
203 mask |= ASYS_I2S_CON_ONE_HEART_MODE;
204 val |= ASYS_I2S_CON_ONE_HEART_MODE;
205 }
206 reg = ASMO_TIMING_CON1;
207 }
208
209 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
210
211 regmap_update_bits(afe->regmap, reg,
212 i2s_data->i2s_asrc_fs_mask
213 << i2s_data->i2s_asrc_fs_shift,
214 fs << i2s_data->i2s_asrc_fs_shift);
215
216 /* enable i2s */
217 mt2701_afe_enable_i2s(afe, i2s_path, stream_dir);
218
219 /* reset i2s hw status before enable */
220 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
221 ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
222 udelay(1);
223 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
224 ASYS_I2S_CON_RESET, 0);
225 udelay(1);
226 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
227 ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
228 return 0;
229 }
230
mt2701_afe_i2s_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)231 static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
232 struct snd_soc_dai *dai)
233 {
234 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
235 struct mt2701_afe_private *afe_priv = afe->platform_priv;
236 int ret, i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
237 struct mt2701_i2s_path *i2s_path;
238 bool mode = afe_priv->soc->has_one_heart_mode;
239
240 if (i2s_num < 0)
241 return i2s_num;
242
243 i2s_path = &afe_priv->i2s_path[i2s_num];
244
245 if (i2s_path->occupied[substream->stream])
246 return -EBUSY;
247
248 ret = mt2701_mclk_configuration(afe, mode ? 1 : i2s_num);
249 if (ret)
250 return ret;
251
252 i2s_path->occupied[substream->stream] = 1;
253
254 /* need to enable i2s-out path when enable i2s-in */
255 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
256 mt2701_i2s_path_enable(afe, i2s_path, !substream->stream,
257 substream->runtime->rate);
258
259 mt2701_i2s_path_enable(afe, i2s_path, substream->stream,
260 substream->runtime->rate);
261
262 return 0;
263 }
264
mt2701_afe_i2s_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)265 static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
266 unsigned int freq, int dir)
267 {
268 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
269 struct mt2701_afe_private *afe_priv = afe->platform_priv;
270 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
271 bool mode = afe_priv->soc->has_one_heart_mode;
272
273 if (i2s_num < 0)
274 return i2s_num;
275
276 /* mclk */
277 if (dir == SND_SOC_CLOCK_IN) {
278 dev_warn(dai->dev, "The SoCs doesn't support mclk input\n");
279 return -EINVAL;
280 }
281
282 afe_priv->i2s_path[mode ? 1 : i2s_num].mclk_rate = freq;
283
284 return 0;
285 }
286
mt2701_btmrg_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)287 static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
288 struct snd_soc_dai *dai)
289 {
290 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
291 struct mt2701_afe_private *afe_priv = afe->platform_priv;
292 int ret;
293
294 ret = mt2701_enable_btmrg_clk(afe);
295 if (ret)
296 return ret;
297
298 afe_priv->mrg_enable[substream->stream] = 1;
299
300 return 0;
301 }
302
mt2701_btmrg_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)303 static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
304 struct snd_pcm_hw_params *params,
305 struct snd_soc_dai *dai)
306 {
307 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
308 int stream_fs;
309 u32 val, msk;
310
311 stream_fs = params_rate(params);
312
313 if (stream_fs != 8000 && stream_fs != 16000) {
314 dev_err(afe->dev, "unsupported rate %d\n", stream_fs);
315 return -EINVAL;
316 }
317
318 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
319 AFE_MRGIF_CON_I2S_MODE_MASK,
320 AFE_MRGIF_CON_I2S_MODE_32K);
321
322 val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
323 | AFE_DAIBT_CON0_MRG_USE;
324 msk = val;
325
326 if (stream_fs == 16000)
327 val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
328
329 msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
330
331 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
332
333 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
334 AFE_DAIBT_CON0_DAIBT_EN,
335 AFE_DAIBT_CON0_DAIBT_EN);
336 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
337 AFE_MRGIF_CON_MRG_I2S_EN,
338 AFE_MRGIF_CON_MRG_I2S_EN);
339 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
340 AFE_MRGIF_CON_MRG_EN,
341 AFE_MRGIF_CON_MRG_EN);
342 return 0;
343 }
344
mt2701_btmrg_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)345 static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
346 struct snd_soc_dai *dai)
347 {
348 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
349 struct mt2701_afe_private *afe_priv = afe->platform_priv;
350
351 /* if the other direction stream is not occupied */
352 if (!afe_priv->mrg_enable[!substream->stream]) {
353 regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
354 AFE_DAIBT_CON0_DAIBT_EN, 0);
355 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
356 AFE_MRGIF_CON_MRG_EN, 0);
357 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
358 AFE_MRGIF_CON_MRG_I2S_EN, 0);
359 mt2701_disable_btmrg_clk(afe);
360 }
361
362 afe_priv->mrg_enable[substream->stream] = 0;
363 }
364
mt2701_simple_fe_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)365 static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
366 struct snd_soc_dai *dai)
367 {
368 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
369 struct mtk_base_afe_memif *memif_tmp;
370 int stream_dir = substream->stream;
371
372 /* can't run single DL & DLM at the same time */
373 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
374 memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
375 if (memif_tmp->substream) {
376 dev_warn(afe->dev, "memif is not available");
377 return -EBUSY;
378 }
379 }
380
381 return mtk_afe_fe_startup(substream, dai);
382 }
383
mt2701_simple_fe_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)384 static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
385 struct snd_pcm_hw_params *params,
386 struct snd_soc_dai *dai)
387 {
388 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
389 int stream_dir = substream->stream;
390
391 /* single DL use PAIR_INTERLEAVE */
392 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
393 regmap_update_bits(afe->regmap,
394 AFE_MEMIF_PBUF_SIZE,
395 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
396 AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
397
398 return mtk_afe_fe_hw_params(substream, params, dai);
399 }
400
mt2701_dlm_fe_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)401 static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
402 struct snd_soc_dai *dai)
403 {
404 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
405 struct mtk_base_afe_memif *memif_tmp;
406 const struct mtk_base_memif_data *memif_data;
407 int i;
408
409 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
410 memif_tmp = &afe->memif[i];
411 if (memif_tmp->substream)
412 return -EBUSY;
413 }
414
415 /* enable agent for all signal DL (due to hw design) */
416 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
417 memif_data = afe->memif[i].data;
418 regmap_update_bits(afe->regmap,
419 memif_data->agent_disable_reg,
420 1 << memif_data->agent_disable_shift,
421 0 << memif_data->agent_disable_shift);
422 }
423
424 return mtk_afe_fe_startup(substream, dai);
425 }
426
mt2701_dlm_fe_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)427 static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
428 struct snd_soc_dai *dai)
429 {
430 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
431 const struct mtk_base_memif_data *memif_data;
432 int i;
433
434 for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
435 memif_data = afe->memif[i].data;
436 regmap_update_bits(afe->regmap,
437 memif_data->agent_disable_reg,
438 1 << memif_data->agent_disable_shift,
439 1 << memif_data->agent_disable_shift);
440 }
441
442 return mtk_afe_fe_shutdown(substream, dai);
443 }
444
mt2701_dlm_fe_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)445 static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
446 struct snd_pcm_hw_params *params,
447 struct snd_soc_dai *dai)
448 {
449 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
450 int channels = params_channels(params);
451
452 regmap_update_bits(afe->regmap,
453 AFE_MEMIF_PBUF_SIZE,
454 AFE_MEMIF_PBUF_SIZE_DLM_MASK,
455 AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
456 regmap_update_bits(afe->regmap,
457 AFE_MEMIF_PBUF_SIZE,
458 AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
459 AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
460 regmap_update_bits(afe->regmap,
461 AFE_MEMIF_PBUF_SIZE,
462 AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
463 AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
464
465 return mtk_afe_fe_hw_params(substream, params, dai);
466 }
467
mt2701_dlm_fe_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)468 static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
469 int cmd, struct snd_soc_dai *dai)
470 {
471 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
472 struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
473
474 switch (cmd) {
475 case SNDRV_PCM_TRIGGER_START:
476 case SNDRV_PCM_TRIGGER_RESUME:
477 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
478 1 << memif_tmp->data->enable_shift,
479 1 << memif_tmp->data->enable_shift);
480 mtk_afe_fe_trigger(substream, cmd, dai);
481 return 0;
482 case SNDRV_PCM_TRIGGER_STOP:
483 case SNDRV_PCM_TRIGGER_SUSPEND:
484 mtk_afe_fe_trigger(substream, cmd, dai);
485 regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
486 1 << memif_tmp->data->enable_shift, 0);
487
488 return 0;
489 default:
490 return -EINVAL;
491 }
492 }
493
mt2701_memif_fs(struct snd_pcm_substream * substream,unsigned int rate)494 static int mt2701_memif_fs(struct snd_pcm_substream *substream,
495 unsigned int rate)
496 {
497 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
498 int fs;
499
500 if (asoc_rtd_to_cpu(rtd, 0)->id != MT2701_MEMIF_ULBT)
501 fs = mt2701_afe_i2s_fs(rate);
502 else
503 fs = (rate == 16000 ? 1 : 0);
504
505 return fs;
506 }
507
mt2701_irq_fs(struct snd_pcm_substream * substream,unsigned int rate)508 static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
509 {
510 return mt2701_afe_i2s_fs(rate);
511 }
512
513 /* FE DAIs */
514 static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
515 .startup = mt2701_simple_fe_startup,
516 .shutdown = mtk_afe_fe_shutdown,
517 .hw_params = mt2701_simple_fe_hw_params,
518 .hw_free = mtk_afe_fe_hw_free,
519 .prepare = mtk_afe_fe_prepare,
520 .trigger = mtk_afe_fe_trigger,
521 };
522
523 static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
524 .startup = mt2701_dlm_fe_startup,
525 .shutdown = mt2701_dlm_fe_shutdown,
526 .hw_params = mt2701_dlm_fe_hw_params,
527 .hw_free = mtk_afe_fe_hw_free,
528 .prepare = mtk_afe_fe_prepare,
529 .trigger = mt2701_dlm_fe_trigger,
530 };
531
532 /* I2S BE DAIs */
533 static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
534 .startup = mt2701_afe_i2s_startup,
535 .shutdown = mt2701_afe_i2s_shutdown,
536 .prepare = mt2701_afe_i2s_prepare,
537 .set_sysclk = mt2701_afe_i2s_set_sysclk,
538 };
539
540 /* MRG BE DAIs */
541 static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
542 .startup = mt2701_btmrg_startup,
543 .shutdown = mt2701_btmrg_shutdown,
544 .hw_params = mt2701_btmrg_hw_params,
545 };
546
547 static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
548 /* FE DAIs: memory intefaces to CPU */
549 {
550 .name = "PCMO0",
551 .id = MT2701_MEMIF_DL1,
552 .playback = {
553 .stream_name = "DL1",
554 .channels_min = 1,
555 .channels_max = 2,
556 .rates = SNDRV_PCM_RATE_8000_192000,
557 .formats = (SNDRV_PCM_FMTBIT_S16_LE
558 | SNDRV_PCM_FMTBIT_S24_LE
559 | SNDRV_PCM_FMTBIT_S32_LE)
560 },
561 .ops = &mt2701_single_memif_dai_ops,
562 },
563 {
564 .name = "PCM_multi",
565 .id = MT2701_MEMIF_DLM,
566 .playback = {
567 .stream_name = "DLM",
568 .channels_min = 1,
569 .channels_max = 8,
570 .rates = SNDRV_PCM_RATE_8000_192000,
571 .formats = (SNDRV_PCM_FMTBIT_S16_LE
572 | SNDRV_PCM_FMTBIT_S24_LE
573 | SNDRV_PCM_FMTBIT_S32_LE)
574
575 },
576 .ops = &mt2701_dlm_memif_dai_ops,
577 },
578 {
579 .name = "PCM0",
580 .id = MT2701_MEMIF_UL1,
581 .capture = {
582 .stream_name = "UL1",
583 .channels_min = 1,
584 .channels_max = 2,
585 .rates = SNDRV_PCM_RATE_8000_48000,
586 .formats = (SNDRV_PCM_FMTBIT_S16_LE
587 | SNDRV_PCM_FMTBIT_S24_LE
588 | SNDRV_PCM_FMTBIT_S32_LE)
589 },
590 .ops = &mt2701_single_memif_dai_ops,
591 },
592 {
593 .name = "PCM1",
594 .id = MT2701_MEMIF_UL2,
595 .capture = {
596 .stream_name = "UL2",
597 .channels_min = 1,
598 .channels_max = 2,
599 .rates = SNDRV_PCM_RATE_8000_192000,
600 .formats = (SNDRV_PCM_FMTBIT_S16_LE
601 | SNDRV_PCM_FMTBIT_S24_LE
602 | SNDRV_PCM_FMTBIT_S32_LE)
603
604 },
605 .ops = &mt2701_single_memif_dai_ops,
606 },
607 {
608 .name = "PCM_BT_DL",
609 .id = MT2701_MEMIF_DLBT,
610 .playback = {
611 .stream_name = "DLBT",
612 .channels_min = 1,
613 .channels_max = 1,
614 .rates = (SNDRV_PCM_RATE_8000
615 | SNDRV_PCM_RATE_16000),
616 .formats = SNDRV_PCM_FMTBIT_S16_LE,
617 },
618 .ops = &mt2701_single_memif_dai_ops,
619 },
620 {
621 .name = "PCM_BT_UL",
622 .id = MT2701_MEMIF_ULBT,
623 .capture = {
624 .stream_name = "ULBT",
625 .channels_min = 1,
626 .channels_max = 1,
627 .rates = (SNDRV_PCM_RATE_8000
628 | SNDRV_PCM_RATE_16000),
629 .formats = SNDRV_PCM_FMTBIT_S16_LE,
630 },
631 .ops = &mt2701_single_memif_dai_ops,
632 },
633 /* BE DAIs */
634 {
635 .name = "I2S0",
636 .id = MT2701_IO_I2S,
637 .playback = {
638 .stream_name = "I2S0 Playback",
639 .channels_min = 1,
640 .channels_max = 2,
641 .rates = SNDRV_PCM_RATE_8000_192000,
642 .formats = (SNDRV_PCM_FMTBIT_S16_LE
643 | SNDRV_PCM_FMTBIT_S24_LE
644 | SNDRV_PCM_FMTBIT_S32_LE)
645
646 },
647 .capture = {
648 .stream_name = "I2S0 Capture",
649 .channels_min = 1,
650 .channels_max = 2,
651 .rates = SNDRV_PCM_RATE_8000_192000,
652 .formats = (SNDRV_PCM_FMTBIT_S16_LE
653 | SNDRV_PCM_FMTBIT_S24_LE
654 | SNDRV_PCM_FMTBIT_S32_LE)
655
656 },
657 .ops = &mt2701_afe_i2s_ops,
658 .symmetric_rate = 1,
659 },
660 {
661 .name = "I2S1",
662 .id = MT2701_IO_2ND_I2S,
663 .playback = {
664 .stream_name = "I2S1 Playback",
665 .channels_min = 1,
666 .channels_max = 2,
667 .rates = SNDRV_PCM_RATE_8000_192000,
668 .formats = (SNDRV_PCM_FMTBIT_S16_LE
669 | SNDRV_PCM_FMTBIT_S24_LE
670 | SNDRV_PCM_FMTBIT_S32_LE)
671 },
672 .capture = {
673 .stream_name = "I2S1 Capture",
674 .channels_min = 1,
675 .channels_max = 2,
676 .rates = SNDRV_PCM_RATE_8000_192000,
677 .formats = (SNDRV_PCM_FMTBIT_S16_LE
678 | SNDRV_PCM_FMTBIT_S24_LE
679 | SNDRV_PCM_FMTBIT_S32_LE)
680 },
681 .ops = &mt2701_afe_i2s_ops,
682 .symmetric_rate = 1,
683 },
684 {
685 .name = "I2S2",
686 .id = MT2701_IO_3RD_I2S,
687 .playback = {
688 .stream_name = "I2S2 Playback",
689 .channels_min = 1,
690 .channels_max = 2,
691 .rates = SNDRV_PCM_RATE_8000_192000,
692 .formats = (SNDRV_PCM_FMTBIT_S16_LE
693 | SNDRV_PCM_FMTBIT_S24_LE
694 | SNDRV_PCM_FMTBIT_S32_LE)
695 },
696 .capture = {
697 .stream_name = "I2S2 Capture",
698 .channels_min = 1,
699 .channels_max = 2,
700 .rates = SNDRV_PCM_RATE_8000_192000,
701 .formats = (SNDRV_PCM_FMTBIT_S16_LE
702 | SNDRV_PCM_FMTBIT_S24_LE
703 | SNDRV_PCM_FMTBIT_S32_LE)
704 },
705 .ops = &mt2701_afe_i2s_ops,
706 .symmetric_rate = 1,
707 },
708 {
709 .name = "I2S3",
710 .id = MT2701_IO_4TH_I2S,
711 .playback = {
712 .stream_name = "I2S3 Playback",
713 .channels_min = 1,
714 .channels_max = 2,
715 .rates = SNDRV_PCM_RATE_8000_192000,
716 .formats = (SNDRV_PCM_FMTBIT_S16_LE
717 | SNDRV_PCM_FMTBIT_S24_LE
718 | SNDRV_PCM_FMTBIT_S32_LE)
719 },
720 .capture = {
721 .stream_name = "I2S3 Capture",
722 .channels_min = 1,
723 .channels_max = 2,
724 .rates = SNDRV_PCM_RATE_8000_192000,
725 .formats = (SNDRV_PCM_FMTBIT_S16_LE
726 | SNDRV_PCM_FMTBIT_S24_LE
727 | SNDRV_PCM_FMTBIT_S32_LE)
728 },
729 .ops = &mt2701_afe_i2s_ops,
730 .symmetric_rate = 1,
731 },
732 {
733 .name = "MRG BT",
734 .id = MT2701_IO_MRG,
735 .playback = {
736 .stream_name = "BT Playback",
737 .channels_min = 1,
738 .channels_max = 1,
739 .rates = (SNDRV_PCM_RATE_8000
740 | SNDRV_PCM_RATE_16000),
741 .formats = SNDRV_PCM_FMTBIT_S16_LE,
742 },
743 .capture = {
744 .stream_name = "BT Capture",
745 .channels_min = 1,
746 .channels_max = 1,
747 .rates = (SNDRV_PCM_RATE_8000
748 | SNDRV_PCM_RATE_16000),
749 .formats = SNDRV_PCM_FMTBIT_S16_LE,
750 },
751 .ops = &mt2701_btmrg_ops,
752 .symmetric_rate = 1,
753 }
754 };
755
756 static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
757 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
758 };
759
760 static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
761 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
762 };
763
764 static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
765 SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
766 };
767
768 static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
769 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
770 };
771
772 static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
773 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
774 };
775
776 static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
777 SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
778 };
779
780 static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
781 SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
782 };
783
784 static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
785 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
786 };
787
788 static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
789 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
790 };
791
792 static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
793 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
794 };
795
796 static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
797 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
798 };
799
800 static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
801 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
802 };
803
804 static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
805 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
806 };
807
808 static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
809 SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
810 };
811
812 static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
813 SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
814 };
815
816 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
817 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
818 ASYS_I2SO1_CON, 26, 1, 0),
819 };
820
821 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
822 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
823 ASYS_I2SO2_CON, 26, 1, 0),
824 };
825
826 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
827 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
828 PWR2_TOP_CON, 17, 1, 0),
829 };
830
831 static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
832 SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
833 PWR2_TOP_CON, 18, 1, 0),
834 };
835
836 static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
837 /* inter-connections */
838 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
839 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
840 SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
841 ARRAY_SIZE(mt2701_afe_i02_mix)),
842 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
843 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
844 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
845 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
846 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
847 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
848 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
849 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
850 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
851 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
852 SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
853
854 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
855 ARRAY_SIZE(mt2701_afe_o00_mix)),
856 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
857 ARRAY_SIZE(mt2701_afe_o01_mix)),
858 SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
859 ARRAY_SIZE(mt2701_afe_o02_mix)),
860 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
861 ARRAY_SIZE(mt2701_afe_o03_mix)),
862 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
863 ARRAY_SIZE(mt2701_afe_o14_mix)),
864 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
865 ARRAY_SIZE(mt2701_afe_o15_mix)),
866 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
867 ARRAY_SIZE(mt2701_afe_o16_mix)),
868 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
869 ARRAY_SIZE(mt2701_afe_o17_mix)),
870 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
871 ARRAY_SIZE(mt2701_afe_o18_mix)),
872 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
873 ARRAY_SIZE(mt2701_afe_o19_mix)),
874 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
875 ARRAY_SIZE(mt2701_afe_o20_mix)),
876 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
877 ARRAY_SIZE(mt2701_afe_o21_mix)),
878 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
879 ARRAY_SIZE(mt2701_afe_o22_mix)),
880 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
881 ARRAY_SIZE(mt2701_afe_o31_mix)),
882
883 SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
884 mt2701_afe_multi_ch_out_i2s0,
885 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
886 SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
887 mt2701_afe_multi_ch_out_i2s1,
888 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
889 SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
890 mt2701_afe_multi_ch_out_i2s2,
891 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
892 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
893 mt2701_afe_multi_ch_out_i2s3,
894 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
895 };
896
897 static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
898 {"I12", NULL, "DL1"},
899 {"I13", NULL, "DL1"},
900 {"I35", NULL, "DLBT"},
901
902 {"I2S0 Playback", NULL, "O15"},
903 {"I2S0 Playback", NULL, "O16"},
904 {"I2S1 Playback", NULL, "O17"},
905 {"I2S1 Playback", NULL, "O18"},
906 {"I2S2 Playback", NULL, "O19"},
907 {"I2S2 Playback", NULL, "O20"},
908 {"I2S3 Playback", NULL, "O21"},
909 {"I2S3 Playback", NULL, "O22"},
910 {"BT Playback", NULL, "O31"},
911
912 {"UL1", NULL, "O00"},
913 {"UL1", NULL, "O01"},
914 {"UL2", NULL, "O02"},
915 {"UL2", NULL, "O03"},
916 {"ULBT", NULL, "O14"},
917
918 {"I00", NULL, "I2S0 Capture"},
919 {"I01", NULL, "I2S0 Capture"},
920 {"I02", NULL, "I2S1 Capture"},
921 {"I03", NULL, "I2S1 Capture"},
922 /* I02,03 link to UL2, also need to open I2S0 */
923 {"I02", "I2S0 Switch", "I2S0 Capture"},
924
925 {"I26", NULL, "BT Capture"},
926
927 {"I12I13", "Multich I2S0 Out Switch", "DLM"},
928 {"I14I15", "Multich I2S1 Out Switch", "DLM"},
929 {"I16I17", "Multich I2S2 Out Switch", "DLM"},
930 {"I18I19", "Multich I2S3 Out Switch", "DLM"},
931
932 { "I12", NULL, "I12I13" },
933 { "I13", NULL, "I12I13" },
934 { "I14", NULL, "I14I15" },
935 { "I15", NULL, "I14I15" },
936 { "I16", NULL, "I16I17" },
937 { "I17", NULL, "I16I17" },
938 { "I18", NULL, "I18I19" },
939 { "I19", NULL, "I18I19" },
940
941 { "O00", "I00 Switch", "I00" },
942 { "O01", "I01 Switch", "I01" },
943 { "O02", "I02 Switch", "I02" },
944 { "O03", "I03 Switch", "I03" },
945 { "O14", "I26 Switch", "I26" },
946 { "O15", "I12 Switch", "I12" },
947 { "O16", "I13 Switch", "I13" },
948 { "O17", "I14 Switch", "I14" },
949 { "O18", "I15 Switch", "I15" },
950 { "O19", "I16 Switch", "I16" },
951 { "O20", "I17 Switch", "I17" },
952 { "O21", "I18 Switch", "I18" },
953 { "O22", "I19 Switch", "I19" },
954 { "O31", "I35 Switch", "I35" },
955 };
956
mt2701_afe_pcm_probe(struct snd_soc_component * component)957 static int mt2701_afe_pcm_probe(struct snd_soc_component *component)
958 {
959 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
960
961 snd_soc_component_init_regmap(component, afe->regmap);
962
963 return 0;
964 }
965
966 static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
967 .probe = mt2701_afe_pcm_probe,
968 .name = "mt2701-afe-pcm-dai",
969 .dapm_widgets = mt2701_afe_pcm_widgets,
970 .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
971 .dapm_routes = mt2701_afe_pcm_routes,
972 .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
973 .suspend = mtk_afe_suspend,
974 .resume = mtk_afe_resume,
975 };
976
977 static const struct mtk_base_memif_data memif_data_array[MT2701_MEMIF_NUM] = {
978 {
979 .name = "DL1",
980 .id = MT2701_MEMIF_DL1,
981 .reg_ofs_base = AFE_DL1_BASE,
982 .reg_ofs_cur = AFE_DL1_CUR,
983 .fs_reg = AFE_DAC_CON1,
984 .fs_shift = 0,
985 .fs_maskbit = 0x1f,
986 .mono_reg = AFE_DAC_CON3,
987 .mono_shift = 16,
988 .enable_reg = AFE_DAC_CON0,
989 .enable_shift = 1,
990 .hd_reg = AFE_MEMIF_HD_CON0,
991 .hd_shift = 0,
992 .agent_disable_reg = AUDIO_TOP_CON5,
993 .agent_disable_shift = 6,
994 .msb_reg = -1,
995 },
996 {
997 .name = "DL2",
998 .id = MT2701_MEMIF_DL2,
999 .reg_ofs_base = AFE_DL2_BASE,
1000 .reg_ofs_cur = AFE_DL2_CUR,
1001 .fs_reg = AFE_DAC_CON1,
1002 .fs_shift = 5,
1003 .fs_maskbit = 0x1f,
1004 .mono_reg = AFE_DAC_CON3,
1005 .mono_shift = 17,
1006 .enable_reg = AFE_DAC_CON0,
1007 .enable_shift = 2,
1008 .hd_reg = AFE_MEMIF_HD_CON0,
1009 .hd_shift = 2,
1010 .agent_disable_reg = AUDIO_TOP_CON5,
1011 .agent_disable_shift = 7,
1012 .msb_reg = -1,
1013 },
1014 {
1015 .name = "DL3",
1016 .id = MT2701_MEMIF_DL3,
1017 .reg_ofs_base = AFE_DL3_BASE,
1018 .reg_ofs_cur = AFE_DL3_CUR,
1019 .fs_reg = AFE_DAC_CON1,
1020 .fs_shift = 10,
1021 .fs_maskbit = 0x1f,
1022 .mono_reg = AFE_DAC_CON3,
1023 .mono_shift = 18,
1024 .enable_reg = AFE_DAC_CON0,
1025 .enable_shift = 3,
1026 .hd_reg = AFE_MEMIF_HD_CON0,
1027 .hd_shift = 4,
1028 .agent_disable_reg = AUDIO_TOP_CON5,
1029 .agent_disable_shift = 8,
1030 .msb_reg = -1,
1031 },
1032 {
1033 .name = "DL4",
1034 .id = MT2701_MEMIF_DL4,
1035 .reg_ofs_base = AFE_DL4_BASE,
1036 .reg_ofs_cur = AFE_DL4_CUR,
1037 .fs_reg = AFE_DAC_CON1,
1038 .fs_shift = 15,
1039 .fs_maskbit = 0x1f,
1040 .mono_reg = AFE_DAC_CON3,
1041 .mono_shift = 19,
1042 .enable_reg = AFE_DAC_CON0,
1043 .enable_shift = 4,
1044 .hd_reg = AFE_MEMIF_HD_CON0,
1045 .hd_shift = 6,
1046 .agent_disable_reg = AUDIO_TOP_CON5,
1047 .agent_disable_shift = 9,
1048 .msb_reg = -1,
1049 },
1050 {
1051 .name = "DL5",
1052 .id = MT2701_MEMIF_DL5,
1053 .reg_ofs_base = AFE_DL5_BASE,
1054 .reg_ofs_cur = AFE_DL5_CUR,
1055 .fs_reg = AFE_DAC_CON1,
1056 .fs_shift = 20,
1057 .fs_maskbit = 0x1f,
1058 .mono_reg = AFE_DAC_CON3,
1059 .mono_shift = 20,
1060 .enable_reg = AFE_DAC_CON0,
1061 .enable_shift = 5,
1062 .hd_reg = AFE_MEMIF_HD_CON0,
1063 .hd_shift = 8,
1064 .agent_disable_reg = AUDIO_TOP_CON5,
1065 .agent_disable_shift = 10,
1066 .msb_reg = -1,
1067 },
1068 {
1069 .name = "DLM",
1070 .id = MT2701_MEMIF_DLM,
1071 .reg_ofs_base = AFE_DLMCH_BASE,
1072 .reg_ofs_cur = AFE_DLMCH_CUR,
1073 .fs_reg = AFE_DAC_CON1,
1074 .fs_shift = 0,
1075 .fs_maskbit = 0x1f,
1076 .mono_reg = -1,
1077 .mono_shift = -1,
1078 .enable_reg = AFE_DAC_CON0,
1079 .enable_shift = 7,
1080 .hd_reg = AFE_MEMIF_PBUF_SIZE,
1081 .hd_shift = 28,
1082 .agent_disable_reg = AUDIO_TOP_CON5,
1083 .agent_disable_shift = 12,
1084 .msb_reg = -1,
1085 },
1086 {
1087 .name = "UL1",
1088 .id = MT2701_MEMIF_UL1,
1089 .reg_ofs_base = AFE_VUL_BASE,
1090 .reg_ofs_cur = AFE_VUL_CUR,
1091 .fs_reg = AFE_DAC_CON2,
1092 .fs_shift = 0,
1093 .fs_maskbit = 0x1f,
1094 .mono_reg = AFE_DAC_CON4,
1095 .mono_shift = 0,
1096 .enable_reg = AFE_DAC_CON0,
1097 .enable_shift = 10,
1098 .hd_reg = AFE_MEMIF_HD_CON1,
1099 .hd_shift = 0,
1100 .agent_disable_reg = AUDIO_TOP_CON5,
1101 .agent_disable_shift = 0,
1102 .msb_reg = -1,
1103 },
1104 {
1105 .name = "UL2",
1106 .id = MT2701_MEMIF_UL2,
1107 .reg_ofs_base = AFE_UL2_BASE,
1108 .reg_ofs_cur = AFE_UL2_CUR,
1109 .fs_reg = AFE_DAC_CON2,
1110 .fs_shift = 5,
1111 .fs_maskbit = 0x1f,
1112 .mono_reg = AFE_DAC_CON4,
1113 .mono_shift = 2,
1114 .enable_reg = AFE_DAC_CON0,
1115 .enable_shift = 11,
1116 .hd_reg = AFE_MEMIF_HD_CON1,
1117 .hd_shift = 2,
1118 .agent_disable_reg = AUDIO_TOP_CON5,
1119 .agent_disable_shift = 1,
1120 .msb_reg = -1,
1121 },
1122 {
1123 .name = "UL3",
1124 .id = MT2701_MEMIF_UL3,
1125 .reg_ofs_base = AFE_UL3_BASE,
1126 .reg_ofs_cur = AFE_UL3_CUR,
1127 .fs_reg = AFE_DAC_CON2,
1128 .fs_shift = 10,
1129 .fs_maskbit = 0x1f,
1130 .mono_reg = AFE_DAC_CON4,
1131 .mono_shift = 4,
1132 .enable_reg = AFE_DAC_CON0,
1133 .enable_shift = 12,
1134 .hd_reg = AFE_MEMIF_HD_CON0,
1135 .hd_shift = 0,
1136 .agent_disable_reg = AUDIO_TOP_CON5,
1137 .agent_disable_shift = 2,
1138 .msb_reg = -1,
1139 },
1140 {
1141 .name = "UL4",
1142 .id = MT2701_MEMIF_UL4,
1143 .reg_ofs_base = AFE_UL4_BASE,
1144 .reg_ofs_cur = AFE_UL4_CUR,
1145 .fs_reg = AFE_DAC_CON2,
1146 .fs_shift = 15,
1147 .fs_maskbit = 0x1f,
1148 .mono_reg = AFE_DAC_CON4,
1149 .mono_shift = 6,
1150 .enable_reg = AFE_DAC_CON0,
1151 .enable_shift = 13,
1152 .hd_reg = AFE_MEMIF_HD_CON0,
1153 .hd_shift = 6,
1154 .agent_disable_reg = AUDIO_TOP_CON5,
1155 .agent_disable_shift = 3,
1156 .msb_reg = -1,
1157 },
1158 {
1159 .name = "UL5",
1160 .id = MT2701_MEMIF_UL5,
1161 .reg_ofs_base = AFE_UL5_BASE,
1162 .reg_ofs_cur = AFE_UL5_CUR,
1163 .fs_reg = AFE_DAC_CON2,
1164 .fs_shift = 20,
1165 .mono_reg = AFE_DAC_CON4,
1166 .mono_shift = 8,
1167 .fs_maskbit = 0x1f,
1168 .enable_reg = AFE_DAC_CON0,
1169 .enable_shift = 14,
1170 .hd_reg = AFE_MEMIF_HD_CON0,
1171 .hd_shift = 8,
1172 .agent_disable_reg = AUDIO_TOP_CON5,
1173 .agent_disable_shift = 4,
1174 .msb_reg = -1,
1175 },
1176 {
1177 .name = "DLBT",
1178 .id = MT2701_MEMIF_DLBT,
1179 .reg_ofs_base = AFE_ARB1_BASE,
1180 .reg_ofs_cur = AFE_ARB1_CUR,
1181 .fs_reg = AFE_DAC_CON3,
1182 .fs_shift = 10,
1183 .fs_maskbit = 0x1f,
1184 .mono_reg = AFE_DAC_CON3,
1185 .mono_shift = 22,
1186 .enable_reg = AFE_DAC_CON0,
1187 .enable_shift = 8,
1188 .hd_reg = AFE_MEMIF_HD_CON0,
1189 .hd_shift = 14,
1190 .agent_disable_reg = AUDIO_TOP_CON5,
1191 .agent_disable_shift = 13,
1192 .msb_reg = -1,
1193 },
1194 {
1195 .name = "ULBT",
1196 .id = MT2701_MEMIF_ULBT,
1197 .reg_ofs_base = AFE_DAI_BASE,
1198 .reg_ofs_cur = AFE_DAI_CUR,
1199 .fs_reg = AFE_DAC_CON2,
1200 .fs_shift = 30,
1201 .fs_maskbit = 0x1,
1202 .mono_reg = -1,
1203 .mono_shift = -1,
1204 .enable_reg = AFE_DAC_CON0,
1205 .enable_shift = 17,
1206 .hd_reg = AFE_MEMIF_HD_CON1,
1207 .hd_shift = 20,
1208 .agent_disable_reg = AUDIO_TOP_CON5,
1209 .agent_disable_shift = 16,
1210 .msb_reg = -1,
1211 },
1212 };
1213
1214 static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
1215 {
1216 .id = MT2701_IRQ_ASYS_IRQ1,
1217 .irq_cnt_reg = ASYS_IRQ1_CON,
1218 .irq_cnt_shift = 0,
1219 .irq_cnt_maskbit = 0xffffff,
1220 .irq_fs_reg = ASYS_IRQ1_CON,
1221 .irq_fs_shift = 24,
1222 .irq_fs_maskbit = 0x1f,
1223 .irq_en_reg = ASYS_IRQ1_CON,
1224 .irq_en_shift = 31,
1225 .irq_clr_reg = ASYS_IRQ_CLR,
1226 .irq_clr_shift = 0,
1227 },
1228 {
1229 .id = MT2701_IRQ_ASYS_IRQ2,
1230 .irq_cnt_reg = ASYS_IRQ2_CON,
1231 .irq_cnt_shift = 0,
1232 .irq_cnt_maskbit = 0xffffff,
1233 .irq_fs_reg = ASYS_IRQ2_CON,
1234 .irq_fs_shift = 24,
1235 .irq_fs_maskbit = 0x1f,
1236 .irq_en_reg = ASYS_IRQ2_CON,
1237 .irq_en_shift = 31,
1238 .irq_clr_reg = ASYS_IRQ_CLR,
1239 .irq_clr_shift = 1,
1240 },
1241 {
1242 .id = MT2701_IRQ_ASYS_IRQ3,
1243 .irq_cnt_reg = ASYS_IRQ3_CON,
1244 .irq_cnt_shift = 0,
1245 .irq_cnt_maskbit = 0xffffff,
1246 .irq_fs_reg = ASYS_IRQ3_CON,
1247 .irq_fs_shift = 24,
1248 .irq_fs_maskbit = 0x1f,
1249 .irq_en_reg = ASYS_IRQ3_CON,
1250 .irq_en_shift = 31,
1251 .irq_clr_reg = ASYS_IRQ_CLR,
1252 .irq_clr_shift = 2,
1253 }
1254 };
1255
1256 static const struct mt2701_i2s_data mt2701_i2s_data[][2] = {
1257 {
1258 { ASYS_I2SO1_CON, 0, 0x1f },
1259 { ASYS_I2SIN1_CON, 0, 0x1f },
1260 },
1261 {
1262 { ASYS_I2SO2_CON, 5, 0x1f },
1263 { ASYS_I2SIN2_CON, 5, 0x1f },
1264 },
1265 {
1266 { ASYS_I2SO3_CON, 10, 0x1f },
1267 { ASYS_I2SIN3_CON, 10, 0x1f },
1268 },
1269 {
1270 { ASYS_I2SO4_CON, 15, 0x1f },
1271 { ASYS_I2SIN4_CON, 15, 0x1f },
1272 },
1273 /* TODO - extend control registers supported by newer SoCs */
1274 };
1275
mt2701_asys_isr(int irq_id,void * dev)1276 static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
1277 {
1278 int id;
1279 struct mtk_base_afe *afe = dev;
1280 struct mtk_base_afe_memif *memif;
1281 struct mtk_base_afe_irq *irq;
1282 u32 status;
1283
1284 regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
1285 regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
1286
1287 for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
1288 memif = &afe->memif[id];
1289 if (memif->irq_usage < 0)
1290 continue;
1291
1292 irq = &afe->irqs[memif->irq_usage];
1293 if (status & 1 << irq->irq_data->irq_clr_shift)
1294 snd_pcm_period_elapsed(memif->substream);
1295 }
1296
1297 return IRQ_HANDLED;
1298 }
1299
mt2701_afe_runtime_suspend(struct device * dev)1300 static int mt2701_afe_runtime_suspend(struct device *dev)
1301 {
1302 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1303
1304 return mt2701_afe_disable_clock(afe);
1305 }
1306
mt2701_afe_runtime_resume(struct device * dev)1307 static int mt2701_afe_runtime_resume(struct device *dev)
1308 {
1309 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1310
1311 return mt2701_afe_enable_clock(afe);
1312 }
1313
mt2701_afe_pcm_dev_probe(struct platform_device * pdev)1314 static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1315 {
1316 struct mtk_base_afe *afe;
1317 struct mt2701_afe_private *afe_priv;
1318 struct device *dev;
1319 int i, irq_id, ret;
1320
1321 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1322 if (!afe)
1323 return -ENOMEM;
1324
1325 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1326 GFP_KERNEL);
1327 if (!afe->platform_priv)
1328 return -ENOMEM;
1329
1330 afe_priv = afe->platform_priv;
1331 afe_priv->soc = of_device_get_match_data(&pdev->dev);
1332 afe->dev = &pdev->dev;
1333 dev = afe->dev;
1334
1335 afe_priv->i2s_path = devm_kcalloc(dev,
1336 afe_priv->soc->i2s_num,
1337 sizeof(struct mt2701_i2s_path),
1338 GFP_KERNEL);
1339 if (!afe_priv->i2s_path)
1340 return -ENOMEM;
1341
1342 irq_id = platform_get_irq_byname(pdev, "asys");
1343 if (irq_id < 0)
1344 return irq_id;
1345
1346 ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
1347 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1348 if (ret) {
1349 dev_err(dev, "could not request_irq for asys-isr\n");
1350 return ret;
1351 }
1352
1353 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1354 if (IS_ERR(afe->regmap)) {
1355 dev_err(dev, "could not get regmap from parent\n");
1356 return PTR_ERR(afe->regmap);
1357 }
1358
1359 mutex_init(&afe->irq_alloc_lock);
1360
1361 /* memif initialize */
1362 afe->memif_size = MT2701_MEMIF_NUM;
1363 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1364 GFP_KERNEL);
1365 if (!afe->memif)
1366 return -ENOMEM;
1367
1368 for (i = 0; i < afe->memif_size; i++) {
1369 afe->memif[i].data = &memif_data_array[i];
1370 afe->memif[i].irq_usage = -1;
1371 }
1372
1373 /* irq initialize */
1374 afe->irqs_size = MT2701_IRQ_ASYS_END;
1375 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1376 GFP_KERNEL);
1377 if (!afe->irqs)
1378 return -ENOMEM;
1379
1380 for (i = 0; i < afe->irqs_size; i++)
1381 afe->irqs[i].irq_data = &irq_data[i];
1382
1383 /* I2S initialize */
1384 for (i = 0; i < afe_priv->soc->i2s_num; i++) {
1385 afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_PLAYBACK] =
1386 &mt2701_i2s_data[i][SNDRV_PCM_STREAM_PLAYBACK];
1387 afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_CAPTURE] =
1388 &mt2701_i2s_data[i][SNDRV_PCM_STREAM_CAPTURE];
1389 }
1390
1391 afe->mtk_afe_hardware = &mt2701_afe_hardware;
1392 afe->memif_fs = mt2701_memif_fs;
1393 afe->irq_fs = mt2701_irq_fs;
1394 afe->reg_back_up_list = mt2701_afe_backup_list;
1395 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
1396 afe->runtime_resume = mt2701_afe_runtime_resume;
1397 afe->runtime_suspend = mt2701_afe_runtime_suspend;
1398
1399 /* initial audio related clock */
1400 ret = mt2701_init_clock(afe);
1401 if (ret) {
1402 dev_err(dev, "init clock error\n");
1403 return ret;
1404 }
1405
1406 platform_set_drvdata(pdev, afe);
1407
1408 pm_runtime_enable(dev);
1409 if (!pm_runtime_enabled(dev)) {
1410 ret = mt2701_afe_runtime_resume(dev);
1411 if (ret)
1412 goto err_pm_disable;
1413 }
1414 pm_runtime_get_sync(dev);
1415
1416 ret = devm_snd_soc_register_component(&pdev->dev, &mtk_afe_pcm_platform,
1417 NULL, 0);
1418 if (ret) {
1419 dev_warn(dev, "err_platform\n");
1420 goto err_platform;
1421 }
1422
1423 ret = devm_snd_soc_register_component(&pdev->dev,
1424 &mt2701_afe_pcm_dai_component,
1425 mt2701_afe_pcm_dais,
1426 ARRAY_SIZE(mt2701_afe_pcm_dais));
1427 if (ret) {
1428 dev_warn(dev, "err_dai_component\n");
1429 goto err_platform;
1430 }
1431
1432 return 0;
1433
1434 err_platform:
1435 pm_runtime_put_sync(dev);
1436 err_pm_disable:
1437 pm_runtime_disable(dev);
1438
1439 return ret;
1440 }
1441
mt2701_afe_pcm_dev_remove(struct platform_device * pdev)1442 static void mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
1443 {
1444 pm_runtime_put_sync(&pdev->dev);
1445 pm_runtime_disable(&pdev->dev);
1446 if (!pm_runtime_status_suspended(&pdev->dev))
1447 mt2701_afe_runtime_suspend(&pdev->dev);
1448 }
1449
1450 static const struct mt2701_soc_variants mt2701_soc_v1 = {
1451 .i2s_num = 4,
1452 };
1453
1454 static const struct mt2701_soc_variants mt2701_soc_v2 = {
1455 .has_one_heart_mode = true,
1456 .i2s_num = 4,
1457 };
1458
1459 static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
1460 { .compatible = "mediatek,mt2701-audio", .data = &mt2701_soc_v1 },
1461 { .compatible = "mediatek,mt7622-audio", .data = &mt2701_soc_v2 },
1462 {},
1463 };
1464 MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
1465
1466 static const struct dev_pm_ops mt2701_afe_pm_ops = {
1467 SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
1468 mt2701_afe_runtime_resume, NULL)
1469 };
1470
1471 static struct platform_driver mt2701_afe_pcm_driver = {
1472 .driver = {
1473 .name = "mt2701-audio",
1474 .of_match_table = mt2701_afe_pcm_dt_match,
1475 .pm = &mt2701_afe_pm_ops,
1476 },
1477 .probe = mt2701_afe_pcm_dev_probe,
1478 .remove_new = mt2701_afe_pcm_dev_remove,
1479 };
1480
1481 module_platform_driver(mt2701_afe_pcm_driver);
1482
1483 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1484 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1485 MODULE_LICENSE("GPL v2");
1486