1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #include <common.h>
7 #include <clk.h>
8 #include <div64.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #include <generic-phy.h>
12 #include <reset.h>
13 #include <syscon.h>
14 #include <usb.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17 #include <power/regulator.h>
18
19 /* USBPHYC registers */
20 #define STM32_USBPHYC_PLL 0x0
21 #define STM32_USBPHYC_MISC 0x8
22
23 /* STM32_USBPHYC_PLL bit fields */
24 #define PLLNDIV GENMASK(6, 0)
25 #define PLLNDIV_SHIFT 0
26 #define PLLFRACIN GENMASK(25, 10)
27 #define PLLFRACIN_SHIFT 10
28 #define PLLEN BIT(26)
29 #define PLLSTRB BIT(27)
30 #define PLLSTRBYP BIT(28)
31 #define PLLFRACCTL BIT(29)
32 #define PLLDITHEN0 BIT(30)
33 #define PLLDITHEN1 BIT(31)
34
35 /* STM32_USBPHYC_MISC bit fields */
36 #define SWITHOST BIT(0)
37
38 #define MAX_PHYS 2
39
40 #define PLL_LOCK_TIME_US 100
41 #define PLL_PWR_DOWN_TIME_US 5
42 #define PLL_FVCO 2880 /* in MHz */
43 #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
44 #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
45
46 struct pll_params {
47 u8 ndiv;
48 u16 frac;
49 };
50
51 struct stm32_usbphyc {
52 fdt_addr_t base;
53 struct clk clk;
54 struct stm32_usbphyc_phy {
55 struct udevice *vdd;
56 struct udevice *vdda1v1;
57 struct udevice *vdda1v8;
58 int index;
59 bool init;
60 bool powered;
61 } phys[MAX_PHYS];
62 };
63
stm32_usbphyc_get_pll_params(u32 clk_rate,struct pll_params * pll_params)64 void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
65 {
66 unsigned long long fvco, ndiv, frac;
67
68 /*
69 * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
70 * | FVCO = 2880MHz
71 * | NDIV = integer part of input bits to set the LDF
72 * | FRACT = fractional part of input bits to set the LDF
73 * => PLLNDIV = integer part of (FVCO / (INFF*2))
74 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
75 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
76 */
77 fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
78
79 ndiv = fvco;
80 do_div(ndiv, (clk_rate * 2));
81 pll_params->ndiv = (u8)ndiv;
82
83 frac = fvco * (1 << 16);
84 do_div(frac, (clk_rate * 2));
85 frac = frac - (ndiv * (1 << 16));
86 pll_params->frac = (u16)frac;
87 }
88
stm32_usbphyc_pll_init(struct stm32_usbphyc * usbphyc)89 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
90 {
91 struct pll_params pll_params;
92 u32 clk_rate = clk_get_rate(&usbphyc->clk);
93 u32 usbphyc_pll;
94
95 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
96 pr_debug("%s: input clk freq (%dHz) out of range\n",
97 __func__, clk_rate);
98 return -EINVAL;
99 }
100
101 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
102
103 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
104 usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
105
106 if (pll_params.frac) {
107 usbphyc_pll |= PLLFRACCTL;
108 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
109 & PLLFRACIN);
110 }
111
112 writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
113
114 pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
115 clk_rate, pll_params.ndiv, pll_params.frac);
116
117 return 0;
118 }
119
stm32_usbphyc_is_init(struct stm32_usbphyc * usbphyc)120 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
121 {
122 int i;
123
124 for (i = 0; i < MAX_PHYS; i++) {
125 if (usbphyc->phys[i].init)
126 return true;
127 }
128
129 return false;
130 }
131
stm32_usbphyc_is_powered(struct stm32_usbphyc * usbphyc)132 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
133 {
134 int i;
135
136 for (i = 0; i < MAX_PHYS; i++) {
137 if (usbphyc->phys[i].powered)
138 return true;
139 }
140
141 return false;
142 }
143
stm32_usbphyc_phy_init(struct phy * phy)144 static int stm32_usbphyc_phy_init(struct phy *phy)
145 {
146 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
147 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
148 bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
149 true : false;
150 int ret;
151
152 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
153 /* Check if one phy port has already configured the pll */
154 if (pllen && stm32_usbphyc_is_init(usbphyc))
155 goto initialized;
156
157 if (pllen) {
158 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
159 udelay(PLL_PWR_DOWN_TIME_US);
160 }
161
162 ret = stm32_usbphyc_pll_init(usbphyc);
163 if (ret)
164 return ret;
165
166 setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
167
168 /*
169 * We must wait PLL_LOCK_TIME_US before checking that PLLEN
170 * bit is still set
171 */
172 udelay(PLL_LOCK_TIME_US);
173
174 if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
175 return -EIO;
176
177 initialized:
178 usbphyc_phy->init = true;
179
180 return 0;
181 }
182
stm32_usbphyc_phy_exit(struct phy * phy)183 static int stm32_usbphyc_phy_exit(struct phy *phy)
184 {
185 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
186 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
187
188 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
189 usbphyc_phy->init = false;
190
191 /* Check if other phy port requires pllen */
192 if (stm32_usbphyc_is_init(usbphyc))
193 return 0;
194
195 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
196
197 /*
198 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
199 * bit is still clear
200 */
201 udelay(PLL_PWR_DOWN_TIME_US);
202
203 if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
204 return -EIO;
205
206 return 0;
207 }
208
stm32_usbphyc_phy_power_on(struct phy * phy)209 static int stm32_usbphyc_phy_power_on(struct phy *phy)
210 {
211 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
212 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
213 int ret;
214
215 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
216 if (usbphyc_phy->vdda1v1) {
217 ret = regulator_set_enable(usbphyc_phy->vdda1v1, true);
218 if (ret)
219 return ret;
220 }
221
222 if (usbphyc_phy->vdda1v8) {
223 ret = regulator_set_enable(usbphyc_phy->vdda1v8, true);
224 if (ret)
225 return ret;
226 }
227 if (usbphyc_phy->vdd) {
228 ret = regulator_set_enable(usbphyc_phy->vdd, true);
229 if (ret)
230 return ret;
231 }
232
233 usbphyc_phy->powered = true;
234
235 return 0;
236 }
237
stm32_usbphyc_phy_power_off(struct phy * phy)238 static int stm32_usbphyc_phy_power_off(struct phy *phy)
239 {
240 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
241 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
242 int ret;
243
244 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
245 usbphyc_phy->powered = false;
246
247 if (stm32_usbphyc_is_powered(usbphyc))
248 return 0;
249
250 if (usbphyc_phy->vdda1v1) {
251 ret = regulator_set_enable(usbphyc_phy->vdda1v1, false);
252 if (ret)
253 return ret;
254 }
255
256 if (usbphyc_phy->vdda1v8) {
257 ret = regulator_set_enable(usbphyc_phy->vdda1v8, false);
258 if (ret)
259 return ret;
260 }
261
262 if (usbphyc_phy->vdd) {
263 ret = regulator_set_enable(usbphyc_phy->vdd, false);
264 if (ret)
265 return ret;
266 }
267
268 return 0;
269 }
270
stm32_usbphyc_get_regulator(struct udevice * dev,ofnode node,char * supply_name,struct udevice ** regulator)271 static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
272 char *supply_name,
273 struct udevice **regulator)
274 {
275 struct ofnode_phandle_args regulator_phandle;
276 int ret;
277
278 ret = ofnode_parse_phandle_with_args(node, supply_name,
279 NULL, 0, 0,
280 ®ulator_phandle);
281 if (ret) {
282 dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
283 return ret;
284 }
285
286 ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
287 regulator_phandle.node,
288 regulator);
289
290 if (ret) {
291 dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
292 return ret;
293 }
294
295 return 0;
296 }
297
stm32_usbphyc_of_xlate(struct phy * phy,struct ofnode_phandle_args * args)298 static int stm32_usbphyc_of_xlate(struct phy *phy,
299 struct ofnode_phandle_args *args)
300 {
301 if (args->args_count > 1) {
302 pr_debug("%s: invalid args_count: %d\n", __func__,
303 args->args_count);
304 return -EINVAL;
305 }
306
307 if (args->args[0] >= MAX_PHYS)
308 return -ENODEV;
309
310 if (args->args_count)
311 phy->id = args->args[0];
312 else
313 phy->id = 0;
314
315 return 0;
316 }
317
318 static const struct phy_ops stm32_usbphyc_phy_ops = {
319 .init = stm32_usbphyc_phy_init,
320 .exit = stm32_usbphyc_phy_exit,
321 .power_on = stm32_usbphyc_phy_power_on,
322 .power_off = stm32_usbphyc_phy_power_off,
323 .of_xlate = stm32_usbphyc_of_xlate,
324 };
325
stm32_usbphyc_probe(struct udevice * dev)326 static int stm32_usbphyc_probe(struct udevice *dev)
327 {
328 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
329 struct reset_ctl reset;
330 ofnode node;
331 int i, ret;
332
333 usbphyc->base = dev_read_addr(dev);
334 if (usbphyc->base == FDT_ADDR_T_NONE)
335 return -EINVAL;
336
337 /* Enable clock */
338 ret = clk_get_by_index(dev, 0, &usbphyc->clk);
339 if (ret)
340 return ret;
341
342 ret = clk_enable(&usbphyc->clk);
343 if (ret)
344 return ret;
345
346 /* Reset */
347 ret = reset_get_by_index(dev, 0, &reset);
348 if (!ret) {
349 reset_assert(&reset);
350 udelay(2);
351 reset_deassert(&reset);
352 }
353
354 /*
355 * parse all PHY subnodes in order to populate regulator associated
356 * to each PHY port
357 */
358 node = dev_read_first_subnode(dev);
359 for (i = 0; i < MAX_PHYS; i++) {
360 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
361
362 usbphyc_phy->index = i;
363 usbphyc_phy->init = false;
364 usbphyc_phy->powered = false;
365 ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
366 &usbphyc_phy->vdd);
367 if (ret)
368 return ret;
369
370 ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v1-supply",
371 &usbphyc_phy->vdda1v1);
372 if (ret)
373 return ret;
374
375 ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v8-supply",
376 &usbphyc_phy->vdda1v8);
377 if (ret)
378 return ret;
379
380 node = dev_read_next_subnode(node);
381 }
382
383 /* Check if second port has to be used for host controller */
384 if (dev_read_bool(dev, "st,port2-switch-to-host"))
385 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
386
387 return 0;
388 }
389
390 static const struct udevice_id stm32_usbphyc_of_match[] = {
391 { .compatible = "st,stm32mp1-usbphyc", },
392 { },
393 };
394
395 U_BOOT_DRIVER(stm32_usb_phyc) = {
396 .name = "stm32-usbphyc",
397 .id = UCLASS_PHY,
398 .of_match = stm32_usbphyc_of_match,
399 .ops = &stm32_usbphyc_phy_ops,
400 .probe = stm32_usbphyc_probe,
401 .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
402 };
403