xref: /openbmc/u-boot/drivers/gpio/stm32f7_gpio.c (revision 7f941868)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5  */
6 
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/stm32.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 
18 #define MODE_BITS(gpio_pin)		(gpio_pin * 2)
19 #define MODE_BITS_MASK			3
20 #define BSRR_BIT(gpio_pin, value)	BIT(gpio_pin + (value ? 0 : 16))
21 
22 #ifndef CONFIG_SPL_BUILD
23 /*
24  * convert gpio offset to gpio index taking into account gpio holes
25  * into gpio bank
26  */
stm32_offset_to_index(struct udevice * dev,unsigned int offset)27 int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
28 {
29 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
30 	int idx = 0;
31 	int i;
32 
33 	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
34 		if (priv->gpio_range & BIT(i)) {
35 			if (idx == offset)
36 				return idx;
37 			idx++;
38 		}
39 	}
40 	/* shouldn't happen */
41 	return -EINVAL;
42 }
43 
stm32_gpio_direction_input(struct udevice * dev,unsigned offset)44 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
45 {
46 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
47 	struct stm32_gpio_regs *regs = priv->regs;
48 	int bits_index;
49 	int mask;
50 	int idx;
51 
52 	idx = stm32_offset_to_index(dev, offset);
53 	if (idx < 0)
54 		return idx;
55 
56 	bits_index = MODE_BITS(idx);
57 	mask = MODE_BITS_MASK << bits_index;
58 
59 	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index);
60 
61 	return 0;
62 }
63 
stm32_gpio_direction_output(struct udevice * dev,unsigned offset,int value)64 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
65 				       int value)
66 {
67 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
68 	struct stm32_gpio_regs *regs = priv->regs;
69 	int bits_index;
70 	int mask;
71 	int idx;
72 
73 	idx = stm32_offset_to_index(dev, offset);
74 	if (idx < 0)
75 		return idx;
76 
77 	bits_index = MODE_BITS(idx);
78 	mask = MODE_BITS_MASK << bits_index;
79 
80 	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
81 
82 	writel(BSRR_BIT(idx, value), &regs->bsrr);
83 
84 	return 0;
85 }
86 
stm32_gpio_get_value(struct udevice * dev,unsigned offset)87 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
88 {
89 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
90 	struct stm32_gpio_regs *regs = priv->regs;
91 	int idx;
92 
93 	idx = stm32_offset_to_index(dev, offset);
94 	if (idx < 0)
95 		return idx;
96 
97 	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
98 }
99 
stm32_gpio_set_value(struct udevice * dev,unsigned offset,int value)100 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
101 {
102 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
103 	struct stm32_gpio_regs *regs = priv->regs;
104 	int idx;
105 
106 	idx = stm32_offset_to_index(dev, offset);
107 	if (idx < 0)
108 		return idx;
109 
110 	writel(BSRR_BIT(idx, value), &regs->bsrr);
111 
112 	return 0;
113 }
114 
stm32_gpio_get_function(struct udevice * dev,unsigned int offset)115 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
116 {
117 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
118 	struct stm32_gpio_regs *regs = priv->regs;
119 	int bits_index;
120 	int mask;
121 	int idx;
122 	u32 mode;
123 
124 	idx = stm32_offset_to_index(dev, offset);
125 	if (idx < 0)
126 		return idx;
127 
128 	bits_index = MODE_BITS(idx);
129 	mask = MODE_BITS_MASK << bits_index;
130 
131 	mode = (readl(&regs->moder) & mask) >> bits_index;
132 	if (mode == STM32_GPIO_MODE_OUT)
133 		return GPIOF_OUTPUT;
134 	if (mode == STM32_GPIO_MODE_IN)
135 		return GPIOF_INPUT;
136 	if (mode == STM32_GPIO_MODE_AN)
137 		return GPIOF_UNUSED;
138 
139 	return GPIOF_FUNC;
140 }
141 
142 static const struct dm_gpio_ops gpio_stm32_ops = {
143 	.direction_input	= stm32_gpio_direction_input,
144 	.direction_output	= stm32_gpio_direction_output,
145 	.get_value		= stm32_gpio_get_value,
146 	.set_value		= stm32_gpio_set_value,
147 	.get_function		= stm32_gpio_get_function,
148 };
149 #endif
150 
gpio_stm32_probe(struct udevice * dev)151 static int gpio_stm32_probe(struct udevice *dev)
152 {
153 	struct stm32_gpio_priv *priv = dev_get_priv(dev);
154 	struct clk clk;
155 	fdt_addr_t addr;
156 	int ret;
157 
158 	addr = dev_read_addr(dev);
159 	if (addr == FDT_ADDR_T_NONE)
160 		return -EINVAL;
161 
162 	priv->regs = (struct stm32_gpio_regs *)addr;
163 
164 #ifndef CONFIG_SPL_BUILD
165 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
166 	struct ofnode_phandle_args args;
167 	const char *name;
168 	int i;
169 
170 	name = dev_read_string(dev, "st,bank-name");
171 	if (!name)
172 		return -EINVAL;
173 	uc_priv->bank_name = name;
174 
175 	i = 0;
176 	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
177 					 NULL, 3, i, &args);
178 
179 	if (ret == -ENOENT) {
180 		uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
181 		priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
182 	}
183 
184 	while (ret != -ENOENT) {
185 		priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
186 				    args.args[0]);
187 
188 		uc_priv->gpio_count += args.args[2];
189 
190 		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
191 						 ++i, &args);
192 	}
193 
194 	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
195 		(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
196 		priv->gpio_range);
197 #endif
198 	ret = clk_get_by_index(dev, 0, &clk);
199 	if (ret < 0)
200 		return ret;
201 
202 	ret = clk_enable(&clk);
203 
204 	if (ret) {
205 		dev_err(dev, "failed to enable clock\n");
206 		return ret;
207 	}
208 	debug("clock enabled for device %s\n", dev->name);
209 
210 	return 0;
211 }
212 
213 static const struct udevice_id stm32_gpio_ids[] = {
214 	{ .compatible = "st,stm32-gpio" },
215 	{ }
216 };
217 
218 U_BOOT_DRIVER(gpio_stm32) = {
219 	.name	= "gpio_stm32",
220 	.id	= UCLASS_GPIO,
221 	.of_match = stm32_gpio_ids,
222 	.probe	= gpio_stm32_probe,
223 #ifndef CONFIG_SPL_BUILD
224 	.ops	= &gpio_stm32_ops,
225 #endif
226 	.flags	= DM_UC_FLAG_SEQ_ALIAS,
227 	.priv_auto_alloc_size	= sizeof(struct stm32_gpio_priv),
228 };
229